JPS57197848A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS57197848A JPS57197848A JP8212181A JP8212181A JPS57197848A JP S57197848 A JPS57197848 A JP S57197848A JP 8212181 A JP8212181 A JP 8212181A JP 8212181 A JP8212181 A JP 8212181A JP S57197848 A JPS57197848 A JP S57197848A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystal
- layer
- type
- single crystal
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 238000010894 electron beam technology Methods 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 abstract 1
- 230000010354 integration Effects 0.000 abstract 1
- 238000010884 ion-beam technique Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Recrystallisation Techniques (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To use polycrystal Si as a resistance layer by heating the surface of a single crystal Si layer on a SOS substrate and forming the polycrystal Si. CONSTITUTION:In a material of which a P type region 2 and N<+> diffusion regions 3 are formed onto the SOS substrate, electron beams, ion beams and laser rays are irradiated using a Si3N4 film 11 and a SiO2 film 10 as masks, and the single crystal Si layer 2 is degenerated into the polycrystal Si 5. The polycrystal Si 5 may be shaped by changing a very small amount of an N type impurity into an N type conduction type through diffusion to an N<+>-N junction. A gate electrode 4 and a metallic wiring layer 8 are formed through a conventional process. Accordingly, since the process of the resistance layer which has been manufactured through deposition can be omitted and the thickness of a polycrystal silicon layer can be controlled, the controllability of resistance value is improved, and integration is enabled to a high degree.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8212181A JPS57197848A (en) | 1981-05-29 | 1981-05-29 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8212181A JPS57197848A (en) | 1981-05-29 | 1981-05-29 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57197848A true JPS57197848A (en) | 1982-12-04 |
Family
ID=13765575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8212181A Pending JPS57197848A (en) | 1981-05-29 | 1981-05-29 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57197848A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996025765A1 (en) * | 1995-02-16 | 1996-08-22 | Peregrine Semiconductor Corporation | Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon-on-sapphire |
| WO1996026536A1 (en) * | 1995-02-20 | 1996-08-29 | Rohm Co., Ltd. | Semiconductor apparatus with crystal defects and process for its fabrication |
| US5863823A (en) * | 1993-07-12 | 1999-01-26 | Peregrine Semiconductor Corporation | Self-aligned edge control in silicon on insulator |
| US5864162A (en) * | 1993-07-12 | 1999-01-26 | Peregrine Seimconductor Corporation | Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire |
| US5930638A (en) * | 1993-07-12 | 1999-07-27 | Peregrine Semiconductor Corp. | Method of making a low parasitic resistor on ultrathin silicon on insulator |
| US5973363A (en) * | 1993-07-12 | 1999-10-26 | Peregrine Semiconductor Corp. | CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator |
-
1981
- 1981-05-29 JP JP8212181A patent/JPS57197848A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5863823A (en) * | 1993-07-12 | 1999-01-26 | Peregrine Semiconductor Corporation | Self-aligned edge control in silicon on insulator |
| US5864162A (en) * | 1993-07-12 | 1999-01-26 | Peregrine Seimconductor Corporation | Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire |
| US5930638A (en) * | 1993-07-12 | 1999-07-27 | Peregrine Semiconductor Corp. | Method of making a low parasitic resistor on ultrathin silicon on insulator |
| US5973363A (en) * | 1993-07-12 | 1999-10-26 | Peregrine Semiconductor Corp. | CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator |
| WO1996025765A1 (en) * | 1995-02-16 | 1996-08-22 | Peregrine Semiconductor Corporation | Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon-on-sapphire |
| WO1996026536A1 (en) * | 1995-02-20 | 1996-08-29 | Rohm Co., Ltd. | Semiconductor apparatus with crystal defects and process for its fabrication |
| US5808352A (en) * | 1995-02-20 | 1998-09-15 | Rohm Co., Ltd. | Semiconductor apparatus having crystal defects |
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