JPS5656648A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5656648A
JPS5656648A JP13325279A JP13325279A JPS5656648A JP S5656648 A JPS5656648 A JP S5656648A JP 13325279 A JP13325279 A JP 13325279A JP 13325279 A JP13325279 A JP 13325279A JP S5656648 A JPS5656648 A JP S5656648A
Authority
JP
Japan
Prior art keywords
layer
film
oxidized
type island
changed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13325279A
Other languages
Japanese (ja)
Other versions
JPS5831730B2 (en
Inventor
Masabumi Kubota
Kazutoshi Nagano
Seiji Onaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13325279A priority Critical patent/JPS5831730B2/en
Publication of JPS5656648A publication Critical patent/JPS5656648A/en
Publication of JPS5831730B2 publication Critical patent/JPS5831730B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain the device fine and high in performance by a method wherein a P layer surrounded by an N layer is provided on an N<+> type substrate, an N type island layer formed in the P layer, which is covered selectively with HF resisting film, thus made porous and insulated, and the surface of the N type island is thereby flattened to remove a crystal strain. CONSTITUTION:A P layer 51 and N layer 52 are subjected to epitaxial formation on an N<+> type substrate 50, and the N layer 52 is changed to the P layer 51 through B diffusion by means of two layers of oxidized film and nitrified film. Next, an N layer 57 and a part of peripheral P layer 60 and N layer 58 are covered with a nitrified film mask 59, and a light 61 is irradiated thereto to anodizing. A porosity beings from an opening 54' and develops quick sideways under the N type island 58, thus producing a uniform porous layer 62. Then, it is changed to an oxidized film 63 in a short time through heat treatment in an oxidized atmosphere, thus the N layer 58 is isolated. In this case the surface of the N layer 58 is flat to accept a fine working thereon, a crystal of the N layer 58 has little strain to allow a large carrier mobility, thus obtaining such device as is high in density and performance.
JP13325279A 1979-10-15 1979-10-15 Manufacturing method of semiconductor device Expired JPS5831730B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13325279A JPS5831730B2 (en) 1979-10-15 1979-10-15 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13325279A JPS5831730B2 (en) 1979-10-15 1979-10-15 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5656648A true JPS5656648A (en) 1981-05-18
JPS5831730B2 JPS5831730B2 (en) 1983-07-08

Family

ID=15100257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13325279A Expired JPS5831730B2 (en) 1979-10-15 1979-10-15 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5831730B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4628591A (en) * 1984-10-31 1986-12-16 Texas Instruments Incorporated Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon
WO2005031810A3 (en) * 2003-09-12 2005-06-23 Ibm Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer
JP2008504704A (en) * 2004-07-02 2008-02-14 インターナショナル・ビジネス・マシーンズ・コーポレーション Strained silicon-on-insulator by anodic oxidation of buried p + silicon-germanium layer
US7566482B2 (en) 2003-09-30 2009-07-28 International Business Machines Corporation SOI by oxidation of porous silicon

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4628591A (en) * 1984-10-31 1986-12-16 Texas Instruments Incorporated Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon
WO2005031810A3 (en) * 2003-09-12 2005-06-23 Ibm Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer
CN100429761C (en) * 2003-09-12 2008-10-29 国际商业机器公司 Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer
US7566482B2 (en) 2003-09-30 2009-07-28 International Business Machines Corporation SOI by oxidation of porous silicon
JP2008504704A (en) * 2004-07-02 2008-02-14 インターナショナル・ビジネス・マシーンズ・コーポレーション Strained silicon-on-insulator by anodic oxidation of buried p + silicon-germanium layer

Also Published As

Publication number Publication date
JPS5831730B2 (en) 1983-07-08

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