JPS5831730B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5831730B2
JPS5831730B2 JP13325279A JP13325279A JPS5831730B2 JP S5831730 B2 JPS5831730 B2 JP S5831730B2 JP 13325279 A JP13325279 A JP 13325279A JP 13325279 A JP13325279 A JP 13325279A JP S5831730 B2 JPS5831730 B2 JP S5831730B2
Authority
JP
Japan
Prior art keywords
type
region
porous
manufacturing
island region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13325279A
Other languages
Japanese (ja)
Other versions
JPS5656648A (en
Inventor
正文 久保田
清司 大仲
数利 長野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13325279A priority Critical patent/JPS5831730B2/en
Publication of JPS5656648A publication Critical patent/JPS5656648A/en
Publication of JPS5831730B2 publication Critical patent/JPS5831730B2/en
Expired legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/7627Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281Lateral isolation by selective oxidation of silicon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Description

【発明の詳細な説明】 本発明は複数の島領域が互いに絶縁分離されてなる半導
体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device in which a plurality of island regions are insulated and isolated from each other.

近年、集積回路の高密度化が進むとともにゲート当りの
遅延時間の短縮、低消費電力化が大きな流れとなってい
る。
In recent years, as the density of integrated circuits has increased, there has been a major trend toward shorter delay times and lower power consumption per gate.

特に、後者を達成するために、浮遊容量が小さく、リー
ク電流の小さい絶縁分離された島領域に能動部分を形成
する技術(例えば5ilcon on 5apphir
e技術など)が注目をあびており、このような技術の一
つとして多孔質シリコンを用いた絶縁分離法が例えば特
願昭51133371号等で提案されている。
In particular, in order to achieve the latter, techniques for forming active parts in isolated island regions with low stray capacitance and low leakage current (e.g. 5ilcon on 5apphir
e technology, etc.) are attracting attention, and as one such technology, an insulation isolation method using porous silicon has been proposed, for example, in Japanese Patent Application No. 51133371.

本発明は、多孔質シリコンを用いた絶縁分離構造を製造
するにあたってキャリア移動度が太きくしかも絶縁特性
の極めて良好な構造を実現する製造方法を提供するもの
である。
The present invention provides a manufacturing method for manufacturing an insulation isolation structure using porous silicon, which realizes a structure with high carrier mobility and extremely good insulation properties.

第1図A−Eは従来からの絶縁分離法により集積回路用
基板を横取する場合の工程図の一例を示したものである
FIGS. 1A to 1E show an example of process diagrams for seizing integrated circuit boards using the conventional insulation separation method.

まずn型シリコン基板1上にP型層2、N型層3を順次
エピタキシャル族長する(第1図A 、、B )。
First, a P-type layer 2 and an N-type layer 3 are epitaxially grown in sequence on an n-type silicon substrate 1 (FIGS. 1A and 1B).

次に熱酸化してN型層3の表面にシリコン酸化膜4を形
成し、通常の写真食刻により拡散窓5を開孔する(同図
C)。
Next, a silicon oxide film 4 is formed on the surface of the N-type layer 3 by thermal oxidation, and a diffusion window 5 is opened by ordinary photolithography (FIG. 3C).

その後、熱拡散またはイオン打込み等によって、拡散窓
5からホウ素等のP型不純物を拡散し、N型エピタキシ
ャル層3を横切ってP型エピタキシャル層2に達するよ
うにP型不純物領域6を形成する。
Thereafter, a P-type impurity such as boron is diffused from the diffusion window 5 by thermal diffusion or ion implantation, and a P-type impurity region 6 is formed so as to cross the N-type epitaxial layer 3 and reach the P-type epitaxial layer 2.

その結果、側面および底面をP型領域2,6に囲まれた
n型島領域7が形成される(同図D)。
As a result, an n-type island region 7 whose side and bottom surfaces are surrounded by the P-type regions 2 and 6 is formed (D in the same figure).

次に上記の基板を電解液たとえばフッ化水素酸水溶液に
浸漬して陽極処理を施こし、前記P型領域2,6のみを
多孔質シリコン8,9に変成する(同図E)。
Next, the above-mentioned substrate is immersed in an electrolytic solution such as a hydrofluoric acid aqueous solution and anodized, thereby converting only the P-type regions 2 and 6 into porous silicon 8 and 9 (FIG. 3E).

さらに上記基板を酸化性雰囲気中で熱処理すると多孔質
シリコン8,9は容易に酸化膜10.11となり底面、
側面を酸化膜10.11で絶縁分離された複数のn型島
領域7を有する集積回路用基板が構成される(同図F)
Further, when the above-mentioned substrate is heat-treated in an oxidizing atmosphere, the porous silicon 8, 9 easily becomes an oxide film 10, 11 on the bottom surface.
An integrated circuit substrate is constructed having a plurality of n-type island regions 7 whose side surfaces are insulated and separated by oxide films 10 and 11 (FIG. F).
.

このようにして得られたN型島領域7には、種種の半導
体装置、例えばJ−FET 、 I2L 、 MOSな
どを形成することができ、それらの半導体装置を形成す
るために必要であれば、あらかじめ上記N型島領域内に
N型及びP型領域を形成しておくことも可能である。
Various types of semiconductor devices, such as J-FET, I2L, MOS, etc., can be formed in the N-type island region 7 obtained in this way, and if necessary for forming these semiconductor devices, It is also possible to form N-type and P-type regions in advance within the N-type island region.

このような方法で形成された絶縁分離された島の集合か
ら成る集積回路は、リーク電流が少なく浮遊容量が小さ
いため、高速でしかも低消費電力という特徴を有してい
る。
An integrated circuit consisting of a collection of isolated islands formed by such a method has low leakage current and small stray capacitance, and is therefore characterized by high speed and low power consumption.

しかしながら、上述した従来方法によるとP型領域2,
6の多孔質化は不均一に生じ、その結果、多孔質シリコ
ン領域8,9を酸化した際に、酸化膜10の膜厚が不均
一となり、ひいてはN型島領域7に歪を与えることが実
験的に確められた。
However, according to the conventional method described above, the P-type region 2,
The porosity of 6 occurs non-uniformly, and as a result, when the porous silicon regions 8 and 9 are oxidized, the thickness of the oxide film 10 becomes non-uniform, which in turn may cause distortion to the N-type island region 7. confirmed experimentally.

このような歪は、半導体装置をこの島領域に形成した場
合、キャリア移動度μの減小、結晶欠陥によるリーク電
流増加などをもたらし、素子の高速性低消費電力性など
の特徴を著しく悪化させる原因となっていた。
When a semiconductor device is formed in this island region, such distortion causes a decrease in carrier mobility μ and an increase in leakage current due to crystal defects, which significantly deteriorates characteristics such as high speed and low power consumption of the device. It was the cause.

このような問題に鑑みてなされたのが本発明である。The present invention has been made in view of such problems.

このような多孔質シリコン領域が不均一になる現象につ
いて、第2図A、Bを用いて説明する。
The phenomenon in which the porous silicon region becomes non-uniform will be explained using FIGS. 2A and 2B.

第2図Aは第1図りからEへの過渡的な状態を模式的に
示したものである。
FIG. 2A schematically shows a transitional state from the first diagram to E.

多孔質化は、通常フッ化水素酸系水溶液の中に浸漬して
陽極処理することによって行なわれ、反応を速めるため
に、光13を照射する場合が多い。
The formation of porosity is usually carried out by immersing it in a hydrofluoric acid-based aqueous solution and anodizing it, and in many cases irradiating it with light 13 to speed up the reaction.

N型島領域となるべき部分7の表面は、シリコン窒化膜
等14を選択的に被着形成しておき、陽極処理中にその
表面が荒れるのを防ぐ(第2図A)。
A silicon nitride film or the like 14 is selectively deposited on the surface of the portion 7 to become the N-type island region to prevent the surface from becoming rough during anodization (FIG. 2A).

この場合、シリコンの多孔質化は、窒化膜14の開口部
5のP型領域から始まり、深さ方向に進行し、P型領域
2の底面に達すると横方向に進む。
In this case, silicon becomes porous starting from the P-type region of the opening 5 of the nitride film 14, progressing in the depth direction, and progressing laterally when reaching the bottom surface of the P-type region 2.

この際、多孔質化に寄与する電流の大部分は、P型領域
2とN型基板1で構成されるPN接合の空乏層中で生成
される光電流であり、そのほとんどは矢印12で示すよ
うな経路で流れる。
At this time, most of the current that contributes to porosity is a photocurrent generated in the depletion layer of the PN junction composed of the P-type region 2 and the N-type substrate 1, and most of it is shown by arrow 12. It flows along a similar path.

しかしながら、多孔質化された領域8と基板1の間でも
、低速ながらも多孔質化が進行するため、N型基板1の
界面も多孔質化され、N型島領域7の下部で多孔質化層
8がつながる時点では、N型島領域7の中央直下の多孔
質シリコンの厚みと、開口部5のその厚みの差は無視で
きない値となる(第2図A)。
However, since the porous state progresses at a slow rate between the porous region 8 and the substrate 1, the interface of the N-type substrate 1 also becomes porous, and the lower part of the N-type island region 7 becomes porous. At the time when the layers 8 are connected, the difference between the thickness of the porous silicon directly under the center of the N-type island region 7 and the thickness of the opening 5 becomes a non-negligible value (FIG. 2A).

そして酸化を行なうと酸化膜10の厚みが不均一となり
N型島領域7に凸状の歪を生じることになる(第2図B
)。
When oxidation is performed, the thickness of the oxide film 10 becomes non-uniform, resulting in convex distortion in the N-type island region 7 (see Fig. 2B).
).

また、N型島領域7の中央直下のP型領域15は光電流
の通路を考えるとわかるように左右から進行してきた多
孔質領域がてなかった時点では完全には多孔質化されず
に残り、その部分だけ酸化膜が薄くなるため、N型島領
域7とN型基板1のノ 耐圧を低下させる原因にもなっ
ていた。
Furthermore, as can be seen from the perspective of the path of photocurrent, the P-type region 15 directly below the center of the N-type island region 7 is not completely made porous and remains at the time when the porous regions that have progressed from the left and right have not formed. Since the oxide film becomes thinner in that portion, this also causes a decrease in the withstand voltage of the N-type island region 7 and the N-type substrate 1.

本発明の上記の問題点を解決しようとするものである。The present invention is intended to solve the above problems.

第3図A、Bを用いて本発明を説明する。本発明では多
孔質化すべきP型領域32 、33に接し、N型基板3
1よりも不純物濃度の低いN5 型領域30を設け、し
かも30に隣接したP型領域32の表面を陽極処理を行
う際の電解液であるフッ化水素酸に対して耐性のある例
えば窒化シリコン膜14で被うことを特徴としている(
第3図A)。
The present invention will be explained using FIGS. 3A and 3B. In the present invention, the N-type substrate 3 is in contact with the P-type regions 32 and 33 to be made porous.
An N5 type region 30 having an impurity concentration lower than that of 1 is provided, and the surface of the P type region 32 adjacent to 30 is made of, for example, a silicon nitride film that is resistant to hydrofluoric acid, which is an electrolytic solution used in anodizing. It is characterized by covering 14 (
Figure 3A).

このようにして陽極処理を行なうと、多孔フ 質化に寄
与する光電流34のほとんどは空乏層の広がりの大きい
P型領域32,33とN型領域30とで形成されるP−
N接合からのものとなり、N型島領域7直下での多孔質
化は横方向に速く進む。
When anodizing is performed in this way, most of the photocurrent 34 that contributes to the formation of porous oxides is generated by the P-type regions 32 and 33 with large depletion layers and the N-type region 30.
This is from an N-junction, and the porosity immediately below the N-type island region 7 progresses quickly in the lateral direction.

N型基板31とN型領域30の不純物濃度を適当5 に
選ぶことにより、N型基板31への多孔質化は極めて小
さくすることができ、従ってN型島領域7の下部での多
孔質化が従来例に比べてはるかに均一に行なわれるため
、先に述べた二点の問題は解決される。
By appropriately selecting the impurity concentration of the N-type substrate 31 and the N-type region 30 to 5, it is possible to minimize the formation of porosity in the N-type substrate 31, and therefore, the formation of porosity in the lower part of the N-type island region 7 can be minimized. Since this is done much more uniformly than in the conventional example, the two problems mentioned above are solved.

もちろん、N型基板31への多孔質フ 化が完全に除去
されるのではないため、通常は、第2図りに示したよう
に酸化後表面に多少の凹凸が残る。
Of course, since the porous fluoride on the N-type substrate 31 is not completely removed, some unevenness usually remains on the surface after oxidation, as shown in the second diagram.

しかしながら、N型島領域7はその凹凸の一つの斜面上
に乗った状態となるので、島領域7にはほとんど応力は
加わらない。
However, since the N-type island region 7 rests on one slope of the unevenness, almost no stress is applied to the island region 7.

そのため、こ5 のような島領域7に形成された集積回
路は、絶縁分離による低リーク電流、低容量といった特
性に基づいた、高速かつ低消費電力の特徴を備えたもの
となる。
Therefore, the integrated circuit formed in the island region 7 as shown in FIG. 5 has the characteristics of high speed and low power consumption based on the characteristics such as low leakage current and low capacitance due to insulation separation.

また、N型領域30の不純物濃度が、N型基板)31の
濃度に比べて大きい場合にも本発明の効果は得られる。
Further, the effects of the present invention can also be obtained when the impurity concentration of the N-type region 30 is higher than the concentration of the N-type substrate 31.

しかしながら、この場合、N型基板31への多孔質化速
度は比較的大きくなるから、先に述べた表面の凹凸が大
きくなる傾向がある。
However, in this case, since the rate at which the N-type substrate 31 becomes porous is relatively high, the above-mentioned surface irregularities tend to become large.

本発明による絶縁分離されたN型島領域の製造工程の一
実施例を第4図AからHにわたって示す。
An embodiment of the manufacturing process for an isolated N-type island region according to the present invention is shown in FIGS. 4A to 4H.

まずN型シリコン基板50上にP型層51.N型層52
をエピタキシャル成長にて設ける(同図A、B)。
First, a P-type layer 51 is placed on an N-type silicon substrate 50. N-type layer 52
is provided by epitaxial growth (A and B in the same figure).

この場合、エピタキシャルによらずイオン打込み等の池
の方法によってもよい。
In this case, other methods such as ion implantation may be used instead of epitaxial method.

次に熱酸化してN型層52の表面に酸化膜を形成し、さ
らに上からCVD法等でシリコン窒化膜を形成し、窒化
膜と酸化膜の2層構造膜53とする。
Next, an oxide film is formed on the surface of the N-type layer 52 by thermal oxidation, and a silicon nitride film is further formed on the surface by CVD or the like to form a two-layer structure film 53 of a nitride film and an oxide film.

これに写真食刻によって拡散窓54を開口する(同図C
)この拡散窓54から熱拡散またはイオン打込み等の方
法でホウ素等のP型不純物を拡散し、N型エピタキシャ
ル層52を横切ってP型エピクキシャル層51に達する
ようにする(同図D)。
A diffusion window 54 is opened in this by photoetching (C
) A P-type impurity such as boron is diffused from this diffusion window 54 by a method such as thermal diffusion or ion implantation so that it traverses the N-type epitaxial layer 52 and reaches the P-type epitaxial layer 51 (D in the same figure).

次に、N型島領域58とその周辺のP壁領域および将来
多孔質化を行なう際に開口部となる開口部54′をホト
レジスト56で選択的に被い、リンのようなN型不純物
をイオン打込みし、ホトレジストを除去した後アニール
して、基板50よりも不純物濃度の低いN型領域57を
形成する(同図E)。
Next, the N-type island region 58, the surrounding P-wall region, and the opening 54' that will become the opening when making the porous structure in the future are selectively covered with a photoresist 56, and an N-type impurity such as phosphorus is coated with the photoresist 56. After ion implantation and removal of the photoresist, annealing is performed to form an N-type region 57 having a lower impurity concentration than the substrate 50 (FIG. 5E).

さらに、シリコン窒化膜等の陽極処理の際にマスクとな
る膜59でN型領域57とその周辺のP壁領域60およ
びN型島領域58の一部を被い、光61を照射しつつ陽
極処理を行なう(同図F)。
Furthermore, a film 59 such as a silicon nitride film that serves as a mask during anodization is used to cover the N-type region 57 and a portion of the surrounding P-wall region 60 and N-type island region 58, and while irradiating light 61, the anodization is performed. Processing is performed (FIG. F).

開口部54′より多孔質化が始まり、先の第3図A、B
を用いて説明したようにほぼ均一な多孔質領域62が得
られる(同図G)。
Porous formation begins from the opening 54', as shown in FIGS. 3A and B above.
As described above, a substantially uniform porous region 62 is obtained (G in the same figure).

さらに、酸化雰囲気中で熱処理すれば、多孔質領域62
は極めて短時間に酸化膜63となり、絶縁分離されたN
型島領域58が得られる(同図H)。
Furthermore, if heat treatment is performed in an oxidizing atmosphere, the porous region 62
becomes an oxide film 63 in a very short time, and the isolated N
A mold island region 58 is obtained (H in the figure).

先にも述べたように、このような工程を経て形成された
N型島領域58は、従来の製造方法によって形成された
同様の構造のものに比べて、■ 結晶に歪が少ないので
、キャリアの移動度が大きく、高速度作に適する。
As mentioned earlier, the N-type island region 58 formed through such a process has less distortion in the crystal compared to a similar structure formed by a conventional manufacturing method, so that the carrier It has high mobility and is suitable for high-speed production.

■ 島領域の同辺は完全に多孔質化され、絶縁膜となる
ため、シリコン基板との耐圧が大きく、リーク電流が小
さい。
■ The same side of the island region is completely porous and becomes an insulating film, so the withstand voltage with the silicon substrate is high and the leakage current is low.

■ シリコン基板表面が、比較的平担となるから微細加
工が可能である。
■ Microfabrication is possible because the silicon substrate surface is relatively flat.

などの特徴がある。It has such characteristics.

この池、光電流の発生源として形成されたN型領域(例
えば、第3図57)はN子基板に達しているため、この
領域にP壁領域を形成し、保護ダイオードや拡散抵抗を
形成することができ、シリコン基板を有効に利用するこ
とができる。
Since this N-type region (for example, 57 in Fig. 3), which is formed as a source of photocurrent, reaches the N-type substrate, a P-wall region is formed in this region, and a protective diode and a diffused resistor are formed. Therefore, the silicon substrate can be used effectively.

第5図に本発明による製造方法を用いて形成した絶縁分
離された接合形FETを示す。
FIG. 5 shows an isolated junction FET formed using the manufacturing method according to the present invention.

P影領域の多孔質化の際の光電流源として形成したN型
領域101にはP壁領域102が形成され、ゲートと接
続して、保護ダイオードとしている。
A P wall region 102 is formed in an N type region 101 formed as a photocurrent source when the P shadow region is made porous, and is connected to the gate to serve as a protection diode.

多孔質酸化膜103に囲まれたN型島領域107には、
N型のソース106及びドレイン104、P型のゲート
105が形成され、接合型FETを構成している。
In the N-type island region 107 surrounded by the porous oxide film 103,
An N-type source 106 and drain 104 and a P-type gate 105 are formed to constitute a junction FET.

本発明の方法で形成した本構造の素子は結晶の歪が小さ
いため電流担体の移動度μが犬きく、シかも寄生容量が
小さいため、高置波特性がすぐれている。
The element having this structure formed by the method of the present invention has a small crystal strain, so the mobility μ of current carriers is high, and the parasitic capacitance is small, so it has excellent high-frequency wave characteristics.

このように、本発明の方法を用いれば、高性能の絶縁分
離された素子から成る集積回路を比較的容易にしかも安
価に生産することができる。
As described above, by using the method of the present invention, an integrated circuit consisting of high-performance isolated elements can be produced relatively easily and at low cost.

なお、本文中、多孔質シリコンを絶縁物に変成するにあ
たって、酸化をする場合について述べたが、アンモニア
ガス雰囲気中で高温(1000〜1100℃)熱処理し
て窒化膜に変成することもできる。
In this text, we have described the case where porous silicon is oxidized to transform it into an insulator, but it can also be transformed into a nitride film by heat treatment at a high temperature (1000 to 1100° C.) in an ammonia gas atmosphere.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A−Fは従来の多孔質化を用いたシリコン絶縁分
離の方法を説明するための図、第2図A。 Bは従来法の原理的説明図、第3図A、Bは本発明の詳
細な説明図、第4図A−Hは本発明による絶縁分離構造
の製造方法の説明図、第5図は本発明方法を用いて形成
した絶縁分離された半導体装置の断面図である。 50・・・・・・N型基板、53.59・・・・・・耐
フツ化水素酸性のある薄膜(例えばシリコン窒化膜等)
、57・・・・・・多孔質化の際の充電流供給源となる
N型領域、58・・・・・・N型島領域、60・・・・
・・多孔質層となるP壁領域、63・・・・・・シリコ
ン酸化膜。
FIGS. 1A to 1F are diagrams for explaining a conventional silicon insulation isolation method using porous formation, and FIG. B is an explanatory diagram of the principle of the conventional method, FIGS. 3A and B are detailed explanatory diagrams of the present invention, FIGS. FIG. 2 is a cross-sectional view of an isolated semiconductor device formed using the method of the invention. 50...N-type substrate, 53.59...Hydrofluoride acid-resistant thin film (for example, silicon nitride film, etc.)
, 57... N-type region serving as a charging current supply source during porous formation, 58... N-type island region, 60...
...P wall region to become a porous layer, 63...Silicon oxide film.

Claims (1)

【特許請求の範囲】 1 N型導電型半導体基板上に形成されたP型溝電型半
導体層にN型島領域を形成する工程と、前記P型溝電型
半導体層の少なくとも一部に前記N型導電型半導体基板
に達するN型導電型領域を形成する工程と、前記N型導
電型領域と前記N型導電型島領域の間にはさまれた前記
P型溝電型半導体層の表面を含んだ領域に耐フツ化水素
酸性の被膜を形成する工程と、前記P型溝電型半導体層
を前記被膜の形成されていない側から前記被膜の形成さ
れた側へ向って多孔質化する工程と、前記多孔質化した
領域を絶縁物に変質する工程を含むことを特徴とする半
導体装置の製造方法。 2、特許請求の範囲第1項記載の半導体装置の製造方法
において、N型導電型半導体基板に達するN型導電型領
域のN型不純物濃度をN型導電型半導体基板の濃度より
も低くシ、光照射を行なって多孔質化することを特徴と
する半導体装置の製造方法。
[Claims] 1. A step of forming an N-type island region in a P-type trench type semiconductor layer formed on an N-type conductivity type semiconductor substrate, and a step of forming an N-type island region in at least a part of the P-type trench type semiconductor layer. a step of forming an N-type conductivity type region reaching an N-type conductivity type semiconductor substrate; and a surface of the P-type groove conductivity type semiconductor layer sandwiched between the N-type conductivity type region and the N-type conductivity type island region. a step of forming a hydrofluoric acid-resistant film on a region containing the film, and making the P-type trench type semiconductor layer porous from the side where the film is not formed toward the side where the film is formed. A method for manufacturing a semiconductor device, comprising: a step of changing the porous region into an insulator. 2. In the method for manufacturing a semiconductor device according to claim 1, the N-type impurity concentration of the N-type conductivity type region reaching the N-type conductivity type semiconductor substrate is lowered than the concentration of the N-type conductivity type semiconductor substrate; A method for manufacturing a semiconductor device, comprising making it porous by irradiating it with light.
JP13325279A 1979-10-15 1979-10-15 Manufacturing method of semiconductor device Expired JPS5831730B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13325279A JPS5831730B2 (en) 1979-10-15 1979-10-15 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13325279A JPS5831730B2 (en) 1979-10-15 1979-10-15 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5656648A JPS5656648A (en) 1981-05-18
JPS5831730B2 true JPS5831730B2 (en) 1983-07-08

Family

ID=15100257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13325279A Expired JPS5831730B2 (en) 1979-10-15 1979-10-15 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5831730B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4628591A (en) * 1984-10-31 1986-12-16 Texas Instruments Incorporated Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon
US7125458B2 (en) * 2003-09-12 2006-10-24 International Business Machines Corporation Formation of a silicon germanium-on-insulator structure by oxidation of a buried porous silicon layer
US7566482B2 (en) 2003-09-30 2009-07-28 International Business Machines Corporation SOI by oxidation of porous silicon
US7172930B2 (en) * 2004-07-02 2007-02-06 International Business Machines Corporation Strained silicon-on-insulator by anodization of a buried p+ silicon germanium layer

Also Published As

Publication number Publication date
JPS5656648A (en) 1981-05-18

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