JPS5550657A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPS5550657A JPS5550657A JP12413278A JP12413278A JPS5550657A JP S5550657 A JPS5550657 A JP S5550657A JP 12413278 A JP12413278 A JP 12413278A JP 12413278 A JP12413278 A JP 12413278A JP S5550657 A JPS5550657 A JP S5550657A
- Authority
- JP
- Japan
- Prior art keywords
- region
- layers
- type
- layer
- films
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE: To improve high-frequency characteristics, by contracting a circuit element by surrounding epitaxial layers grown on a buried region with thick SiO2 films by means of LOCOS method and by selectively forming base, emitter and collector drawing regions on the SiO2 films.
CONSTITUTION: An n+-type collector buried region 2 is diffusion-made up to a p-type Si substrate 1, n-type layers 3 are grown on the whole surface in epitaxial shapes, p-type separation regions 4 are mounted to both end portions and the layers 3 are insularly built up. Thick SiO2 films 5 are formed around the layers 3 on the region 2 by means of a LOCOS method, and a polycrystal Si layer 6 and an impurities transmission interrupting layer 8 are stacked and coated on the whole surface. An opening 8' is bored to the layer 8 while bringing the opening near the one film 5 side, ions are injected transmitting the layer 6 and a p-type base drawing region 9 and a p-type base region 10 contacting with the region 9 are made up in the layers 3. The layer 8 is changed into insulating films 11 and similarly covered with interrupting layers 13, an opening 13' is installed and a n+-type emitter region 14 is diffusion-built up into the region 10 and a n+-type collector drawing region 15 into the layers 3 respectively.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12413278A JPS5550657A (en) | 1978-10-11 | 1978-10-11 | Preparation of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12413278A JPS5550657A (en) | 1978-10-11 | 1978-10-11 | Preparation of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5550657A true JPS5550657A (en) | 1980-04-12 |
JPS576703B2 JPS576703B2 (en) | 1982-02-06 |
Family
ID=14877703
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12413278A Granted JPS5550657A (en) | 1978-10-11 | 1978-10-11 | Preparation of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5550657A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS642206Y2 (en) * | 1981-02-18 | 1989-01-19 | ||
JPS58190769U (en) * | 1982-06-14 | 1983-12-19 | 三洋電機株式会社 | coin handling equipment |
-
1978
- 1978-10-11 JP JP12413278A patent/JPS5550657A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS576703B2 (en) | 1982-02-06 |
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