JPH0340948B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, a method for manufacturing a semiconductor device, and more specifically, a method for forming a groove having a U-shaped cross section (hereinafter referred to as a U-groove) in a semiconductor substrate and filling the groove with an insulating material. The present invention relates to a method of forming an insulating separation layer by burying it.

(2) Background of the technology The method of forming an insulating separation layer using a U-groove is a method of filling a U-groove formed in a semiconductor substrate with polycrystalline silicon (polysilicon) as an insulator, and is suitable for high integration. . The step of forming an insulating separation layer will be explained below with reference to FIG. _1. First, as shown in _FIG . N ₄ ) Form a film 3. Thereafter, a mask pattern is formed, a U-groove 4 is dug by reactive ion etching (RIE), and then a SiO ₂ film 5 is formed on the wall surface of the U-groove 4 by, for example, thermal oxidation.

Next, polysilicon 6 is grown by chemical vapor deposition (CVD) to fill the U-groove 4 (see figure b), and finally the polysilicon 6 on the nitride film 3 is removed and planarized by polishing ( Figure c).

By the way, in the above-described method of forming an insulating separation layer, it is desired that the U-groove 4 be completely buried in the polysilicon 6 and that the surface after polishing be flat.

(3) Prior art and problems In the conventional method for forming an insulating separation layer described above, a chemically unstable portion is created in the polysilicon buried in the U-groove, and potassium hydroxide (KOH)
When polishing using an alkaline solution such as the above, there was a problem in that the surface was left with voids (areas where voids existed) and flattening was not achieved. To explain this in more detail with reference to FIG. 2, after forming the U groove 4,
The growth of polysilicon 6 by the CVD method is shown in Figure a.
As shown by the broken lines with symbols 7, 8 and 9,
Film growth progresses at the same speed at all locations on the wall surface of the U-groove 4, that is, on the SiO ₂ film 5 and the surface nitride film 3, and the polysilicon film 6 is gradually formed in the order of broken line 7, broken line 8, and then broken line 9. be done. In the film growth process indicated by the broken lines 7, 8, and 9, grains are formed with chemically stable bonds in the growth direction.

On the other hand, as the film growth progresses, the cavity in the U-groove 4 is gradually narrowed by the polysilicon film grown from the wall surface, and finally the film surface grown from the wall surface meets at the position of the broken line 10 and the U-groove 4 is filled. .

However, in the film growth process near the broken line 10, the newly grown grains are fitted between the surfaces of the previously grown film, so the degree of freedom of bonding is lost and a chemically unstable interface is formed. As a result, the above-mentioned interface is etched with an alkaline solution during polishing, and cracks are generated in this area, resulting in the formation of slits 11 on the surface after flattening, as shown in FIG. This step 11 causes wire breakage in the wiring process, resulting in a problem of lowering the yield in the manufacture of semiconductor devices.

On the other hand, when forming a U-groove using RIE, it is ideal that the angle θ shown in Figure a is 90 degrees and the wall surface is vertical. It has been experienced that a wide U-groove can be formed. In such a case, the chemical bond at the interface becomes even weaker, and in some cases, cavities may remain, making planarization more difficult. Due to the above-mentioned situation, there was also a problem in that the rate at which U-groove filling and planarization were achieved in the prior art was reduced.

(4) Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention provides a method for forming an insulating separation layer using a U-groove, in which the opening of the U-groove filled with polysilicon is flattened regardless of the shape of the U-groove. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can perform the following steps.

(5) Structure of the Invention According to the present invention, the purpose is to form an insulating film by forming a groove having a U-shaped cross section in a semiconductor substrate, forming an oxide film on the surface of the groove, and then filling the groove with polycrystalline silicon. The separation layer is formed by growing the polycrystalline silicon to a thickness that fills the trench and covering the entire surface of the semiconductor substrate, and annealing the polycrystalline silicon in an inert atmosphere at a temperature below the melting point of the semiconductor substrate. The grains of the polycrystalline silicon at the chemically unstable interface that occurs in the polycrystalline silicon in the groove are realigned to form an interface that is resistant to chemical etching, and the entire surface of the polycrystalline silicon, including the top of the groove, is removed with an alkaline solution. This is achieved by providing a method for manufacturing a semiconductor device, characterized in that polycrystalline silicon is removed by a polish containing polycrystalline silicon, leaving polycrystalline silicon in the trench.

(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

As described in the above structure, the present invention provides chemical strength by aligning the interface, which has conventionally been chemically weak, by annealing after polysilicon growth. The process will be explained in detail below.

First, as in the prior art, as shown in FIG. 1a, a SiO ₂ film 2 and a Si ₃ N ₄ film 3 are formed on a silicon substrate 1, and then an etching mask is formed and RIE is performed.
A U-groove 4 is dug, and then a SiO ₂ film 5 is formed on the wall surface. In this process, the opening width W of the U groove
is, for example, 3 μm to 7 μm, and the SiO ₂ film 5 on the wall surface is formed by a thermal oxidation method, and the temperature is
The temperature is 900°C to 1000°C, and the film thickness formed is 500 to 3000 Å.

Next, the pressure of polysilicon 6 is reduced as shown in Figure 3.
It grows to a thickness of 2 μm to 3 μm by CVD method and buries the U groove 4. At this time, an interface 12 having a weak chemical bond is formed within the polysilicon 6. Next, annealing is performed in a nitrogen (N ₂ ) atmosphere at a temperature of 700° C. to 1200° C. for an appropriately determined time. For example, according to the inventor of the present application, it has been confirmed that sufficient effects can be obtained when the temperature is set at 900° C. or higher and the time is set at 30 minutes or longer. Such annealing causes the grains to realign at the interface 12, resulting in a chemically strong interface that will not be attacked by an alkaline solution. It has also been confirmed that by performing the annealing, even if a cavity exists at the interface 12, this cavity can be eliminated.

On the other hand, since the above-mentioned annealing does not require a processing temperature higher than the melting point of the silicon substrate (approximately 1320° C.), it has the advantage of aligning grains and strengthening chemical bonds at the interface without melting the substrate.

After the above-mentioned annealing, planarization is performed by polishing as in the conventional method. In this case, the interface within the polysilicon has already been chemically strengthened, so the second
Flattening as shown in FIG. 1c is achieved without the occurrence of the spots indicated by reference numeral 11 in FIG. 1b. The present invention also provides a second
If the angle θ shown in Figure a is 90 degrees or less, flattening can be achieved even if a cavity remains in the polysilicon, so U
This can be carried out regardless of the shape of the groove.

Note that the temperature and time for annealing are not limited to those in the above embodiments, but are appropriately set at a temperature below the melting temperature of the silicon substrate.

(7) Effects of the invention As explained in detail above, according to the present invention, U
In the method of forming an insulating separation layer used in a trench, embedding with polysilicon and flattening of the surface can be achieved regardless of the shape of the U-groove, so that the insulation separation of semiconductor elements formed on the substrate can be ensured, and the surface can be flattened. Therefore, disconnection in the wiring process can be prevented, which is highly effective in increasing the integration and reliability of semiconductor devices and improving the yield in manufacturing semiconductor devices.

[Brief explanation of the drawing]

FIGS. 1, 2, and 3 are cross-sectional views of essential parts of a semiconductor device showing the step of forming an insulating isolation layer using a U-groove. 1... Silicon substrate, 2, 5... SiO ₂ film, 3
... _Si3N4 film, 4...U groove, 6...polysilicon, 11...su _, 12...interface.

Claims (1)

[Claims] 1. A method for forming an insulating isolation layer by forming a groove having a U-shaped cross section in a semiconductor substrate, forming an oxide film on the surface of the groove, and then filling the groove with polycrystalline silicon, Polycrystalline silicon is grown to a thickness that fills the trench and covers the entire surface of the semiconductor substrate, and is annealed in an inert atmosphere at a temperature below the melting point of the semiconductor substrate to remove the chemical produced in the polycrystalline silicon in the trench. The grains of the polycrystalline silicon are realigned at the physically unstable interface to form an interface that is resistant to chemical etching. A method for manufacturing a semiconductor device, characterized in that polycrystalline silicon is left behind.