JP3153632B2 - Manufacturing method of SOI structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing an SOI structure.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, generally,
An epitaxial growth layer is formed on a silicon substrate, and a circuit is formed on the epitaxial growth layer. By the way, in such a structure, the silicon substrate and the epitaxial growth layer form a PN junction and have a capacitance. The capacitance of the PN junction reduces the operation speed of the device. Therefore, the structure is not suitable for forming an element requiring high-speed operation.

In order to solve this problem, recently, an insulating layer is formed on a silicon substrate, and a silicon single crystal layer is further formed thereon (SOI (Semiconductor on Insula).
option) technology is desired. That is, the PN junction between the silicon single crystal layer and the silicon substrate is eliminated by insulating the silicon single crystal layer from the silicon substrate.

FIG. 4 shows an ELO (Epitaxial Lateral Over)
growth) method using conventional SOI technology (Lateral Ep)
itaxial Overgrowth of Silicon on SiO ₂ : D.Rathmanet.
al.:JOURNAL OF ELECTRON-CHEMICAL SOCIETY SOLID-STA
TE SCIENCE AND THECNOLOGY, October 1982, 2303
page). In this method, first, a silicon oxide film 4 is grown on the upper surface of the semiconductor substrate 2. Next, the silicon oxide film 4 is selectively etched using a photoresist to open a seed window 6 (see FIG. 4A). Further, selective epitaxial growth of silicon is performed in the vertical direction from the seed window 6. Subsequently, lateral epitaxial growth is performed to form an epitaxial layer 8 on the silicon oxide film 4 (see FIG. 4B). By doing so, the PN junction surface between the epitaxial layer 8 and the silicon substrate 2 can be reduced to the size of the seed window 6. Therefore, the PN junction capacitance can be reduced, and the operation speed of the device can be increased.

[0005] There is also a method called the SENTAXY method (Takahiro Yonehara et al., New SOI-Selective Nucleation E).
pitaxy, Proceedings of the 48th Japan Society of Applied Physics, 1987 (autumn), 19p-Q-15, p. 583). In this method, a plurality of silicon nuclei for crystal growth are artificially formed on an insulating layer such as a silicon oxide film, and epitaxial growth is performed from each nucleus. As a nucleus, a method of forming and using a silicon nitride film having a small area, a method of forming a nucleus by a focused ion beam (FIB) method, and the like are being studied. According to this method, the epitaxial layer and the silicon substrate can be insulated from each other by the oxide film, and the problem of the junction capacitance as described above can be solved.

[0006]

However, the above-mentioned conventional SOI technology has the following problems. In the ELO method shown in FIG. 4, although the joints are smaller, the joints are not completely eliminated. Therefore, further speeding up of the element has been hindered.

On the other hand, according to the SENTAXY method, an epitaxial layer and a silicon substrate in which the silicon substrate is insulated can be obtained, and there is no problem as described above. However, SE
According to the NTAXY method, the plane orientation of the epitaxial layer grown from each of the plurality of nuclei was different.
If the plane orientation of the epitaxial layer is different, the characteristics such as the oxidation rate are different, and there has been a problem that an element having desired characteristics cannot be formed uniformly.

The applicant of the present invention has proposed a method for manufacturing an SOI structure having a silicon single crystal layer in which a silicon single crystal layer is insulated from a substrate by an insulating layer and has a uniform plane orientation, as shown in FIGS. 6 was proposed. FIG.
First, a silicon oxide layer 4 is formed on a silicon substrate 2 (see FIG. 5A). Next, an opening 14 is provided in the silicon oxide layer 4 (see FIG. 5B). Then, silicon is grown to slightly protrude from the opening 14 to form a silicon seed crystal layer 16 (see FIG. 5C). Thereafter, after a nitride film 18 is formed on the surface of the silicon seed crystal layer 16, oxidation is performed (FIG. 5D).
reference). As a result, the silicon oxide layer 4 grows to become the field oxide layer 20, and the field oxide layer 20 is bonded at the bottom of the opening 14, so that the silicon seed crystal layer 16 is insulated from the silicon substrate 2 (FIG. e)). Thereafter, the silicon seed crystal layer 16 is epitaxially grown to obtain a silicon growth layer 22 (see FIG. 5F). (See Japanese Patent Application No. 3-138742) On the other hand, in the manufacturing method shown in FIG. 6, first, a silicon oxide layer 4 is formed on a silicon substrate 2 (see FIG. 6A). Next, an opening 14 is provided in the silicon oxide layer 4 (FIG. 6).
(B)). Then, silicon carbide is grown until it protrudes from opening 14 to form silicon carbide seed crystal layer 16.
(See FIGS. 6C and 6D), and oxidation is performed. Thereby, field oxide layer 20 is bonded below opening 14 and silicon carbide seed crystal layer 16 is insulated from silicon substrate 2 (see FIG. 6E). Thereafter, epitaxial growth is performed from the silicon carbide seed crystal layer 16 to obtain a silicon carbide growth layer 22 (see FIG. 6F). (See Japanese Patent Application No. 3-186280.) However, in the above prior art, when an epitaxial growth layer is enlarged in order to increase an element formation region, an oxidation step for element isolation for forming a field oxide film is performed. This lengthens the stress on the underlying silicon substrate. On the other hand, if an attempt is made to shorten the oxidation time in order to reduce the stress, the epitaxial growth layer must be made smaller, and as a result, the element formation region becomes smaller and the productivity decreases.

Further, the lateral length of the seed crystal silicon varies depending on the plane orientation of the underlying silicon substrate, and it is difficult to control the lateral growth of the seed crystal. Variations in dimensions occur, reducing the degree of freedom in design. In view of the above, an object of the present invention is to provide a method of manufacturing an SOI structure in which an oxidation time can be shortened, an element formation region can be formed with high accuracy, and the degree of freedom in design increases.

[0010]

According to the first aspect of the present invention, there is provided an SOI device.
The method of manufacturing the structure includes a step of forming a silicon oxide layer on a silicon substrate to a first thickness, forming a trench in a predetermined portion of the silicon oxide layer, and forming the silicon oxide layer at the bottom of the trench sufficiently than the first thickness. Forming a thin second thickness, depositing a silicon nitride layer on the entire surface so as to fill the trench, and then leaving the silicon nitride layer in contact with the trench side wall as a side wall; Etching until exposed, epitaxially growing silicon of the silicon substrate exposed at the bottom of the trench as a seed crystal, forming an epitaxially grown layer in the trench, and growing a field oxide layer below the epitaxially grown layer,
The method is characterized by including a step of disconnecting the connection between the silicon substrate and the epitaxial growth layer.

According to a second aspect of the present invention, in the method for manufacturing an SOI structure according to the first aspect, the step of disconnecting the silicon substrate from the epitaxial growth layer includes the step of:
Before cutting off the connection between the silicon substrate and the epitaxial growth layer, a step of removing the entire silicon oxide layer, and after cutting off the connection between the silicon substrate and the epitaxial growth layer, removing the silicon oxide on the sidewalls and the epitaxial growth layer, The method is characterized by including a step of embedding silicon oxide between epitaxial growth layers.

[0012]

In the manufacturing method according to the first aspect of the present invention, a silicon nitride layer is deposited on the entire surface so as to fill the trench, and then the silicon nitride layer in contact with the trench side wall remains as a sidewall and the silicon at the bottom of the trench is formed. Etching is performed until the surface of the substrate is exposed, and the silicon of the silicon substrate exposed at the bottom of the trench is epitaxially grown as a seed crystal, and the epitaxial growth layer is formed in the trench.
That is, the width of the connection portion with the silicon substrate can be smaller than the width of the upper portion of the epitaxial growth layer.

As described above, by using the sidewalls, the width of the connection between the epitaxial growth layer and the silicon substrate can be narrowed and the oxidation distance can be shortened. Therefore, the field oxide layer is formed under the epitaxial growth layer by thermal oxidation. And a short oxidation time when disconnecting the connection between the silicon substrate and the epitaxial growth layer is required, and the stress on the silicon substrate can be reduced.

Further, the size of the epitaxial growth layer is set in consideration of the stress as in the related art, because the oxidation time for element isolation can be shortened to reduce the stress on the silicon substrate. This eliminates the necessity, so that the element formation region can be widened and the productivity can be improved. In the epitaxial growth step, since the seed crystal is grown in the trench to form an epitaxial growth layer, the lateral growth of the seed crystal is suppressed by the sidewall provided on the side wall of the trench, and the seed crystal grows vertically along the sidewall. . Therefore, the dimensional accuracy in the lateral direction of the epitaxial growth layer is improved.

In the side wall forming step, the width of the side wall can be easily controlled by controlling the thickness of the silicon nitride layer. To increase the degree of freedom in design. Further, in the manufacturing method according to the second aspect, before cutting off the connection between the silicon substrate and the epitaxial growth layer, the entire surface of the silicon oxide layer is removed, and the connection between the silicon substrate and the epitaxial growth layer is cut off. Since the silicon oxide is removed and the silicon oxide is buried between the epitaxial growth layers, an SOI substrate having a small stress and a wide element formation region with high productivity can be provided.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 3 is a sectional view showing an example of a semiconductor device having an SOI structure obtained by a manufacturing method according to one embodiment of the present invention. The structure of the semiconductor device will be described with reference to FIG.

As shown in FIG. 3, the semiconductor device has an SOI (S
emiconductor on Insulation) A plurality of (two in the figure) MOSFET (metal
oxide semiconductor feild effect trnsistor) 31 is provided. The SOI substrate 30 has a plane orientation (1
00) P-type silicon substrate 32 and P-type silicon substrate 3
2 formed on two element formation regions (2 in FIG.
) Epitaxial growth layer 33 and silicon substrate 32
Field oxide layer 34 which completely separates silicon oxide and epitaxial growth layer 33 from each other, and a plasma silicon oxide layer (hereinafter referred to as P-S
35 (referred to as an iO ₂ layer).

At the surface of each epitaxial growth layer 33, the N-type source region 36 and the N-type
A mold drain region 37 is formed with a channel region 38 interposed therebetween, and a gate insulating film 38 is formed on each channel region 38 so as to bridge each source region 36 and drain region 37. On each channel region 38, a gate 39 made of polysilicon is provided via a gate insulating film 38, and a gate electrode 40 is connected to the gate 39. A source electrode 41 is connected to each source region 36, and a drain electrode 42 is connected to each drain region 37. The electrodes 40, 41, and 42 are insulated from each other by an interlayer insulating film 43.
And the P-SiO ₂ layer 35, an insulating film 44 is interposed.

With the above configuration, the PN junction between the silicon substrate 32 and the epitaxial growth layer 33 is eliminated, and the device can operate at high speed. FIG. 1 is a sectional view showing a method for manufacturing an SOI structure in the order of steps. The method of manufacturing the SOI structure, that is, the SOI substrate 30, will be described with reference to FIG. First, as shown in FIG.
A silicon oxide layer 5 made of, for example, SiO _{2 having} a thickness of 4500 ° is formed on a P-type silicon substrate 32 having a plane orientation of (100).
OA is formed. The thermal oxidation conditions may be, for example, an oxidation temperature of 950 ° C. and an oxidation time of 90 minutes.

Then, as shown in FIG. 1B, after a resist 51 is applied on the silicon oxide layer 50A, the silicon oxide layer 50A in the element formation region is removed by etching to expose the silicon substrate 32. In this manner, for example, a trench 52 having a depth of 5000 ° is formed, and the silicon substrate 32 at the bottom of the trench 52 is exposed. Then, FIG.
As shown in (c), after removing the resist 51, thermal oxidation is performed to cover the entire surface of the silicon substrate 32 exposed at the bottom of the trench 52 with, for example, a 500-mm thick SiO 2.
_A thin silicon oxide layer 50B of 2 is formed. As the thermal oxidation conditions, for example, an oxidation temperature of 900 ° C. and an oxidation time of 3
It may be 0 minutes. As described above, the silicon oxide layer 50B is formed thinner in the next step.
This is to reduce the damage of the underlying silicon substrate 32 when depositing 3 at 4000 °.

Another method for forming a thin silicon oxide layer 50B at the bottom of the trench 52 is to form the trench 52 by etching.
The silicon oxide layer 50B may be formed thin by controlling the depth of the silicon oxide layer 50B. In the following description, the silicon oxide layer 50A and the silicon oxide layer 50B are collectively referred to as “silicon oxide layer 50”.

Next, as shown in FIG.
(chemical vapor deposition) method, etc.
Then, a silicon nitride layer 53 made of, for example, Si ₃ N ₄ is deposited to a thickness of 4000 ° over the entire surface so as to bury the layer 2. Thereafter, as shown in FIG. 1E, for example, RIE is performed so that the silicon nitride layer 53 in contact with the sidewall of the trench 52 remains in the shape of the sidewall 54 and the surface of the silicon substrate 32 at the bottom of the trench 52 is exposed. Etch back by anisotropic etching such as (reactive ion etching). The width of the side wall 54 can be freely set by the etching time and the reaction gas flow rate, but is preferably about 0.1 to 0.4 μm. If the underlying silicon oxide layer 50B remains in this step, the silicon oxide layer 50B may be removed by, for example, wet etching using HF or the like.

Subsequently, as shown in FIG. 1 (f), silicon of the silicon substrate 32 exposed at the bottom of the trench 52 is epitaxially grown to a thickness of, for example, 5000.degree. Next, an epitaxial growth layer 33 is formed. It is preferable that the epitaxial growth is performed at a temperature as low as possible at a growth temperature of about 1150 ° C. using, for example, a reaction gas SiCl ₄ . This is because stacking faults in the epitaxial growth layer 33 can be suppressed by performing epitaxial growth at a low temperature in this manner.

Then, for example, as shown in FIG.
Silicon oxide layer 5 by wet etching
0 is entirely removed. Next, as shown in FIG. 1H, the silicon of the silicon substrate 32 under the element formation region, that is, the epitaxial growth layer 33 is oxidized by thermal oxidation.
A field oxide layer 34 of iO ₂ is grown laterally and bonded below the epitaxial growth layer 33 to cut off the connection between the silicon substrate 32 and the epitaxial growth layer 33. At this time, the upper part of the epitaxial growth layer 33 is also oxidized to become the silicon oxide layer 55. As the thermal oxidation conditions, for example, an oxidation temperature of 1000 ° C. and an oxidation time of 90 minutes are preferable.

Then, for example, as shown in FIG.
The sidewalls (Si ₃ N ₄ ) 54 are removed by etching such as E (chemical dry etching). Then, for example, P-SiO ₂ is 5,000 by a plasma CVD method.
{Circle around (3)}, SOG is sequentially deposited, and then etched back by annealing and anisotropic etching.
The P-SiO ₂ layer 35 is flattened. At this time, the silicon oxide layer 55 on the epitaxial growth layer 33 is also removed.

In the steps shown in FIGS. 1D to 1G,
A silicon nitride layer 5 is formed on the entire surface so as to fill trench 52.
3 is deposited (see FIG. 1D), the silicon nitride layer 53 in contact with the side wall of the trench 52 is
Etching until the surface of the silicon substrate 32 at the bottom of the trench 52 is exposed (FIG. 1).
(See FIG. 1E), epitaxial growth is performed using the silicon of the silicon substrate 32 exposed at the bottom of the trench 52 as a seed crystal, and an epitaxial growth layer 33 is formed in the trench 52 (see FIG. 1F). Since the entire surface of the silicon layer 50 is removed (see FIG. 1G), as shown in FIG.
That is, the width W2 of the connection portion with the silicon substrate 32 can be smaller than the width W1 of the upper portion of the epitaxial growth layer 33. FIG. 2 is an enlarged sectional view at the end of the step of FIG.

As described above, by utilizing the side walls 54, the silicon substrate 3 of the epitaxial growth layer 33 is formed.
Since the oxidation distance can be shortened by narrowing the width W2 of the connection portion with the silicon substrate 32, the field oxide layer 34 is bonded under the epitaxial growth layer 33 by thermal oxidation in the step of FIG. Oxidation time when disconnecting the connection with the epitaxial growth layer 33 is short. Therefore, stress on the silicon substrate 32 can be reduced.

Further, since the oxidation time for element isolation can be shortened and the stress on the silicon substrate 32 can be reduced, the size of the epitaxial growth layer 33 can be reduced in consideration of the stress as in the related art. This eliminates the need for setting, and the element formation region can be widened. Therefore, productivity is also improved. Further, FIG.
In the epitaxial growth step, the seed crystal is grown in the trench 52 to form the epitaxial growth layer 33, so that the lateral growth of the seed crystal is suppressed by the sidewall 54 provided on the side wall of the trench 52, and along the side wall 54. Grow vertically. for that reason,
The dimensional accuracy in the lateral direction of the epitaxial growth layer 33 is improved.

1D and 1E, the width of the side wall 54 can be easily controlled by controlling the thickness of the silicon nitride layer 53. The size of
That is, the size of the element formation region can be arbitrarily set. Therefore, the degree of freedom in design increases. It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that many changes or modifications can be made within the scope of the present invention.

[0030]

As is apparent from the above description, in the manufacturing method according to the first aspect of the present invention, by utilizing the sidewall, the width of the connection portion between the epitaxial growth layer and the silicon substrate is reduced to reduce the oxidation distance. Since it can be shortened, the field oxidation layer is bonded under the epitaxial growth layer by thermal oxidation, and the oxidation time when disconnecting the silicon substrate from the epitaxial growth layer can be shortened, and the stress on the silicon substrate can be reduced. it can.

As described above, it is possible to reduce the stress on the silicon substrate by shortening the oxidation time for element isolation, and thereby to reduce the size of the epitaxial growth layer in consideration of the stress as in the related art. This eliminates the need for setting, and the element formation region can be widened, so that productivity is also improved. In the epitaxial growth step, the lateral growth of the seed crystal is suppressed by the sidewall provided on the sidewall of the trench, and the seed crystal grows vertically along the sidewall, so that the lateral dimensional accuracy of the epitaxial growth layer is improved.

In the side wall forming step, the width of the side wall can be easily controlled by controlling the thickness of the silicon nitride layer. Therefore, the size of the epitaxial growth layer, that is, the size of the element forming region can be arbitrarily set. To increase the degree of freedom in design. Further, according to the manufacturing method of the second aspect, it is possible to provide an SOI substrate having a small stress and a wide element formation region with high productivity.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method of manufacturing an SOI structure according to an embodiment of the present invention in the order of steps.

FIG. 2 is an enlarged cross-sectional view at the end of the step in FIG.

FIG. 3 is a cross-sectional view showing an example of a semiconductor device having an SOI structure obtained by a manufacturing method according to one embodiment of the present invention.

FIG. 4 is a diagram showing an SOI technique by a conventional ELO method.

FIG. 5 is a sectional view showing a method for manufacturing an SOI structure according to the prior art in the order of steps.

FIG. 6 is a cross-sectional view showing a method of manufacturing an SOI structure according to another prior art in the order of steps.

[Explanation of symbols]

 Reference Signs List 30 SOI substrate 32 Silicon substrate 33 Epitaxial growth layer 34 Field oxide layer 50, 50A, 50B Silicon oxide layer 52 Trench 53 Silicon nitride layer 54 Side wall

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/786 H01L 29/78 621

Claims (2)

(57) [Claims] A step of forming a silicon oxide layer on a silicon substrate to a first thickness, forming a trench in a predetermined portion of the silicon oxide layer, and making the silicon oxide layer at the bottom of the trench sufficiently thinner than the first thickness. Forming a silicon nitride layer on the entire surface so as to fill the trench, so that the silicon nitride layer in contact with the trench sidewall remains as a sidewall, and the silicon substrate surface at the bottom of the trench is exposed Etching the silicon substrate exposed at the bottom of the trench as a seed crystal, forming an epitaxially grown layer in the trench, and growing a field oxide layer below the epitaxially grown layer. Including a step of disconnecting the connection with the epitaxial growth layer Manufacturing method of OI structure. 2. The method for manufacturing an SOI structure according to claim 1, wherein the step of disconnecting the silicon substrate from the epitaxial growth layer includes removing the entire silicon oxide layer before disconnecting the silicon substrate from the epitaxial growth layer. Manufacturing an SOI structure, comprising cutting off the connection between the silicon substrate and the epitaxial growth layer, removing the silicon oxide on the sidewalls and the epitaxial growth layer, and embedding the silicon oxide between the epitaxial growth layers. Method.