JPH05343320A - Manufacture of soi structure - Google Patents

Abstract

PURPOSE:To provide an SOI structure for accurate active device regions, while reducing the time required for oxidation, by narrowing the contact area between an epitaxial layer and a silicon substrate with a side wall so that the length for oxidation may be shortened. CONSTITUTION:Silicon nitride 53 is deposited over trenches 52, and the silicon nitride is etched back to the surface of a silicon substrate 32 in such a manner that it remains to form side walls 54 on the sides of the trenches 52. In the trenches, Silicon is epitaxially grown from the silicon substrate. Then, a field oxide 34 is grown until it extends to the lower side of the epitaxial layer 33. As a result, the epitaxial layer is isolated from the silicon substrate by the field oxide; that is, an SOI structure is obtained. According to this method, the time for oxidation to isolate the epitaxial layer from the silicon substrate is shortened, so that the stresses on the substrate are reduced.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a method of manufacturing an SOI structure.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit,
An epitaxial growth layer is formed on a silicon substrate, and a circuit is formed on this epitaxial growth layer. By the way, in such a structure, the silicon substrate and the epitaxial growth layer form a PN junction and have a capacitance. The capacitance of this PN junction reduces the operating speed of the device. Therefore, the structure is not suitable for forming an element that requires high-speed operation.

In order to solve this problem, in recent years, an insulating layer is formed on a silicon substrate, and a silicon single crystal layer is further formed thereon (SOI (Semiconductor on Insula).
technology) is desired. That is, it is intended to eliminate the PN junction between the silicon single crystal layer and the silicon substrate by insulating the silicon single crystal layer from the silicon substrate.

FIG. 4 shows an ELO (Epitaxial Lateral Over
Conventional SOI technology using the growth method is shown (Lateral Ep
itaxial Overgrowth of Silicon on SiO ₂ : D.Rathmanet.
al.:JOURNAL OF ELECTRON-CHEMICAL SOCIETY SOLID-STA
TE SCIENCE AND THECNOLOGY, October 1982, 2303
page). In this method, first, the silicon oxide film 4 is grown on the upper surface of the semiconductor substrate 2. Next, the silicon oxide film 4 is selectively etched using a photoresist to open the seed window 6 (see FIG. 4A). Further, selective epitaxial growth of silicon is performed in the vertical direction from the seed window 6. Subsequent to this, lateral epitaxial growth is performed to form an epitaxial layer 8 on the silicon oxide film 4 (see FIG. 4B). By doing so, the PN junction surface between the epitaxial layer 8 and the silicon substrate 2 can be reduced to the size of the seed window 6. Therefore, the PN junction capacitance can be reduced, and the operation speed of the device can be increased.

There is also a method called SENTAXY method (Takahiro Yonehara et al., New SOI-Selective Nucleation E
pitaxy, 1987 (Autumn) Proceedings of the 48th Japan Society of Applied Physics, 19p-Q-15, p.583). This is a method in which a plurality of silicon nuclei for crystal growth are artificially formed in an insulating layer such as a silicon oxide film, and epitaxial growth is performed from each nuclei. As a nucleus, a method of forming and using a silicon nitride film having a minute area, a method of forming a nucleus by a FIB (Focused Ion Beam) method, and the like are being studied. According to this method, the epitaxial layer and the silicon substrate can be insulated from each other by the oxide film, and the problem of the junction capacitance as described above can be solved.

[0006]

However, the conventional SOI technology as described above has the following problems. In the ELO method shown in FIG. 4, although the joint portion is said to be small, the joint portion is not completely eliminated. Therefore, further speeding up of the device has been hindered.

On the other hand, according to the SENTAXY method, it is possible to obtain the one in which the epitaxial layer and the silicon substrate are insulated, and there is no problem as described above. However, SE
According to the NTAXY method, the plane directions of the epitaxial layers grown from the respective nuclei provided are different.
When the plane orientation of the epitaxial layer is different, the characteristics such as the oxidation rate are different, which causes a problem that elements having desired characteristics cannot be uniformly formed.

Therefore, the applicant of the present invention has previously described, as a method of manufacturing an SOI structure in which a silicon single crystal layer is insulated from a substrate by an insulating layer and a silicon single crystal layer has a uniform plane orientation, as shown in FIG. The manufacturing method shown in 6 was proposed. Figure 5
In the manufacturing method shown in, first, the silicon oxide layer 4 is formed on the silicon substrate 2 (see FIG. 5A). Next, the opening 14 is provided in the silicon oxide layer 4 (see FIG. 5B). Then, silicon is grown until it slightly projects from the opening 14 to form a silicon seed crystal layer 16 (see FIG. 5C). Then, after forming a nitride film 18 on the surface of the silicon seed crystal layer 16, oxidation is performed (FIG. 5D).
reference). As a result, the silicon oxide layer 4 grows to become the field oxide layer 20, and the field oxide layer 20 is bonded at the bottom of the opening 14 to insulate the silicon seed crystal layer 16 from the silicon substrate 2 (see FIG. See e)). Then, the silicon seed crystal layer 16 is epitaxially grown to obtain the silicon growth layer 22 (see FIG. 5F). (See Japanese Patent Application No. 3-138742) On the other hand, in the manufacturing method shown in FIG. 6, first, the silicon oxide layer 4 is formed on the silicon substrate 2 (see FIG. 6A). Next, an opening 14 is formed in the silicon oxide layer 4 (see FIG. 6).
(See (b)). Then, silicon carbide is grown until it projects from the opening 14 to form a silicon carbide seed crystal layer 16, and then the surface of the silicon carbide seed crystal layer 16 is covered with a nitride film 18.
(See FIGS. 6 (c) and 6 (d)) and oxidize. As a result, the field oxide layer 20 is bonded under the opening 14 and the silicon carbide seed crystal layer 16 is insulated from the silicon substrate 2 (see FIG. 6E). Thereafter, the silicon carbide seed crystal layer 16 is epitaxially grown to obtain a silicon carbide growth layer 22 (see FIG. 6F). (See Japanese Patent Application No. 3-186280) However, in the above-mentioned prior art, when the epitaxial growth layer is enlarged in order to increase the element formation region, the oxidation step for element isolation for forming the field oxide film is performed. It becomes longer, and stress on the underlying silicon substrate increases. On the other hand, if an attempt is made to shorten the oxidation time in order to reduce the stress, the epitaxial growth layer must be made smaller, resulting in a smaller element formation region and a reduction in productivity.

Further, the lateral length of the silicon serving as the seed crystal differs depending on the plane orientation of the underlying silicon substrate, which makes it difficult to control the lateral growth of the seed crystal. Variations in dimensions occur, reducing design flexibility. In view of the above, an object of the present invention is to provide a method for manufacturing an SOI structure which can shorten the oxidation time, can form an element formation region with high accuracy, and increase the degree of freedom in design.

[0010]

The SOI according to claim 1 of the present invention
The method of manufacturing the structure includes a step of forming a silicon oxide layer on a silicon substrate to have a first thickness, a trench is formed at a predetermined position of the silicon oxide layer, and the silicon oxide layer at the bottom of the trench is made sufficiently thicker than the first thickness. In the step of forming the thin second thickness, after depositing a silicon nitride layer on the entire surface so as to fill the trench, the silicon nitride layer contacting the sidewall of the trench is left as a sidewall, and the surface of the silicon substrate at the bottom of the trench is Etching until exposed, silicon epitaxially grown silicon of the silicon substrate exposed at the bottom of the trench as a seed crystal, forming an epitaxial growth layer in the trench, and growing a field oxide layer under the epitaxial growth layer,
The method is characterized by including a step of disconnecting the connection between the silicon substrate and the epitaxial growth layer.

The method of manufacturing an SOI structure according to claim 2 is the method of manufacturing an SOI structure according to claim 1, wherein the step of disconnecting the connection between the silicon substrate and the epitaxial growth layer comprises:
Before disconnecting the connection between the silicon substrate and the epitaxial growth layer, the step of completely removing the silicon oxide layer, and after disconnecting the connection between the silicon substrate and the epitaxial growth layer, removing the silicon oxide on the sidewalls and the epitaxial growth layer, The method is characterized by including a step of embedding silicon oxide between epitaxial growth layers.

[0012]

In the manufacturing method of the first aspect of the present invention, after depositing the silicon nitride layer on the entire surface so as to fill the trench, the silicon nitride layer contacting with the sidewall of the trench is left as the sidewall, and the silicon at the bottom of the trench is deposited. Etching is performed until the substrate surface is exposed at, the silicon of the silicon substrate exposed at the bottom of the trench is epitaxially grown as a seed crystal, and the epitaxial growth layer is formed in the trench.
That is, the width of the connection portion with the silicon substrate can be made narrower than the width of the upper portion of the epitaxial growth layer.

As described above, by utilizing the sidewall, the width of the connection portion of the epitaxial growth layer with the silicon substrate can be narrowed and the oxidation distance can be shortened. Therefore, the field oxidation layer is formed below the epitaxial growth layer by thermal oxidation. The bonding time can be shortened when the connection between the silicon substrate and the epitaxial growth layer is disconnected, and the stress on the silicon substrate can be reduced.

Further, since it becomes possible to reduce the stress on the silicon substrate by shortening the oxidation time for element isolation, the size of the epitaxial growth layer is set taking the stress into consideration as in the conventional case. It is not necessary, the element forming region can be widened, and the productivity is improved. In the epitaxial growth step, the seed crystal is grown in the trench to form an epitaxial growth layer, so that the lateral growth of the seed crystal is suppressed by the sidewall provided on the sidewall of the trench, and the seed crystal grows vertically along the sidewall. .. Therefore, the lateral dimensional accuracy of the epitaxial growth layer is improved.

In the side wall forming step, the width of the side wall can be easily controlled by controlling the thickness of the silicon nitride layer. Therefore, the size of the epitaxial growth layer, that is, the size of the element forming region is arbitrary. Can be set to increase the degree of freedom in design. Further, in the manufacturing method of claim 2, before disconnecting the connection between the silicon substrate and the epitaxial growth layer, the silicon oxide layer is entirely removed, and after disconnecting the connection between the silicon substrate and the epitaxial growth layer, the sidewall and the epitaxial growth layer are formed. Since the silicon oxide is removed and the silicon oxide is embedded between the epitaxial growth layers, it is possible to provide an SOI substrate having a wide element formation region with low stress and high productivity.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIGS. FIG. 3 is a sectional view showing an example of a semiconductor device having an SOI structure obtained by a manufacturing method according to an embodiment of the present invention. The structure of this semiconductor device will be described with reference to FIG.

As shown in FIG. 3, the above semiconductor device has an SOI (S
emiconductor on Insulation) A plurality of (two in the figure) MOSFETs (metals) are formed on the element formation region of the substrate 30.
Oxide semiconductor feild effect trnsistor) 31 is provided. The SOI substrate 30 has a plane orientation (1
00) P-type silicon substrate 32 and P-type silicon substrate 3
A plurality of elements (2 in the figure
Epitaxial growth layer 33 and silicon substrate 32
And the epitaxial growth layer 33 are completely separated from each other, and a plasma silicon oxide layer (hereinafter referred to as PS) that insulates the periphery between the epitaxial growth layer 33.
iO ₂ layer) 35.

In the surface layer portion of each epitaxial growth layer 33, the N-type source regions 36 and N of each MOSFET 31 are formed.
The mold drain regions 37 are formed so as to sandwich the channel region 38, and the gate insulating film 38 is formed on each channel region 38 so as to bridge the source region 36 and the drain region 37. A gate 39 made of polysilicon is provided on each channel region 38 via a gate insulating film 38, and a gate electrode 40 is connected to the gate 39. A source electrode 41 is connected to each source region 36, and a drain electrode 42 is connected to each drain region 37. The electrodes 40, 41, 42 are insulated from each other by an interlayer insulating film 43, and the source electrode 41 and the drain electrode 42 are each insulated.
An insulating film 44 is interposed between the P-SiO ₂ layer 35 and the P-SiO ₂ layer 35.

With the above structure, the PN junction between the silicon substrate 32 and the epitaxial growth layer 33 is eliminated, and the device can operate at high speed. 1A to 1D are cross-sectional views showing a method of manufacturing an SOI structure in the order of steps. A method of manufacturing the SOI structure, that is, the SOI substrate 30, will be described with reference to FIG. First, as shown in FIG. 1A, by thermal oxidation,
On the P-type silicon substrate 32 having a plane orientation (100), for example, a silicon oxide layer 5 made of SiO _{2 having} a thickness of 4500Å
Form 0A. The thermal oxidation conditions may be, for example, an oxidation temperature of 950 ° C. and an oxidation time of 90 minutes.

Then, as shown in FIG. 1B, after a resist 51 is applied on the silicon oxide layer 50A, the silicon oxide layer 50A in the element forming region is removed by etching to expose the silicon substrate 32. For example, a trench 52 having a depth of 5000 Å is formed and the silicon substrate 32 at the bottom of the trench 52 is exposed. Then, Figure 1
As shown in (c), after removing the resist 51, thermal oxidation is performed to cover the silicon substrate 32 exposed at the bottom of the trench 52 with SiO 2 having a thickness of, for example, 500 Å over the entire surface.
_The silicon oxide layer 50B made of 2 is thinly formed. The thermal oxidation conditions are, for example, an oxidation temperature of 900 ° C. and an oxidation time of 3
It should be 0 minutes. In this way, the silicon oxide layer 50B is further thinly formed in the next step.
This is to reduce damage to the underlying silicon substrate 32 when depositing 3 of 4000 Å.

As another method for thinly forming the silicon oxide layer 50B on the bottom of the trench 52, the trench 52 is formed when the trench 52 is formed by etching.
The silicon oxide layer 50B may be thinly formed by controlling the depth of. In the following description, the silicon oxide layer 50A and the silicon oxide layer 50B are collectively referred to as "silicon oxide layer 50".

Next, as shown in FIG. 1D, for example, CVD
(Chemical vapor deposition) method etc.
A silicon nitride layer 53 of, for example, Si ₃ N ₄ is deposited on the entire surface so as to be filled with 2 by 4000 Å. Thereafter, as shown in FIG. 1E, for example, RIE is performed so that the silicon nitride layer 53 contacting the sidewall of the trench 52 remains in the shape of the sidewall 54 and the surface of the silicon substrate 32 at the bottom of the trench 52 is exposed. Etch back by anisotropic etching such as (reactive ion etching). The width of the sidewall 54 can be freely set by the etching time and the reaction gas flow rate, but is preferably about 0.1 to 0.4 μm. If the underlying silicon oxide layer 50B remains in this step, the silicon oxide layer 50B may be removed by, for example, wet etching with HF or the like.

Subsequently, as shown in FIG. 1 (f), the silicon of the silicon substrate 32 exposed at the bottom of the trench 52 is used as a seed crystal to grow epitaxially in the vertical direction to a thickness of 5000 Å, for example. Then, the epitaxial growth layer 33 is formed. It is preferable that the epitaxial growth conditions are, for example, using reaction gas SiCl ₄ at a growth temperature of about 1150 ° C., which is as low as possible. By performing the epitaxial growth at a low temperature in this way, stacking faults of the epitaxial growth layer 33 can be suppressed.

Then, as shown in FIG. 1 (g), for example, HF
The silicon oxide layer 5 is formed by wet etching with
0 is entirely removed. Next, as shown in FIG. 1H, the element formation region, that is, the silicon of the silicon substrate 32 below the epitaxial growth layer 33 is oxidized by thermal oxidation, and S
A field oxide layer 34 made of iO ₂ is laterally grown and bonded under the epitaxial growth layer 33, and the connection between the silicon substrate 32 and the epitaxial growth layer 33 is cut off. At this time, the upper portion of the epitaxial growth layer 33 is also oxidized and becomes the silicon oxide layer 55. As the thermal oxidation conditions, for example, an oxidation temperature of 1000 ° C. and an oxidation time of 90 minutes are preferable.

Then, as shown in FIG. 1 (i), for example, a CD
The sidewalls (Si ₃ N ₄ ) 54 are removed by etching such as E (chemical dry etching). Then, for example, the P-SiO _{2 is set} to 5000 by the plasma CVD method.
After Å and SOG were deposited in order of 3000 Å, etch back was performed by annealing and anisotropic etching.
The P-SiO ₂ layer 35 is flattened. At this time, the silicon oxide layer 55 on the epitaxial growth layer 33 is also removed.

In the steps shown in FIGS. 1 (d) to 1 (g),
A silicon nitride layer 5 is formed on the entire surface so as to fill the trench 52.
3 is deposited (see FIG. 1D), the silicon nitride layer 53 contacting the sidewall of the trench 52 becomes the sidewall 54.
And the surface of the silicon substrate 32 at the bottom of the trench 52 is exposed (see FIG. 1).
(See (e)), the silicon of the silicon substrate 32 exposed at the bottom of the trench 52 is epitaxially grown as a seed crystal to form an epitaxial growth layer 33 in the trench 52 (see FIG. 1 (f)), and is oxidized by etching. Since the entire surface of the silicon layer 50 is removed (see FIG. 1G), as shown in FIG.
That is, the width W2 of the connection portion with the silicon substrate 32 can be made narrower than the width W1 of the upper portion of the epitaxial growth layer 33. Note that FIG. 2 is an enlarged cross-sectional view at the end of the process of FIG.

As described above, by utilizing the sidewall 54, the silicon substrate 3 of the epitaxial growth layer 33 is formed.
Since the width W2 of the connection portion with 2 can be narrowed to shorten the oxidation distance, the field oxide layer 34 is bonded under the epitaxial growth layer 33 by thermal oxidation in the step of FIG. A short oxidation time is required when the connection between the epitaxial growth layer 33 and the epitaxial growth layer 33 is cut off. Therefore, the stress on the silicon substrate 32 can be reduced.

Further, since it becomes possible to shorten the oxidation time for element isolation and reduce the stress on the silicon substrate 32, the size of the epitaxial growth layer 33 can be reduced in consideration of the stress as in the conventional case. It is not necessary to set, and the element formation region can be widened. Therefore, productivity is also improved. Furthermore, FIG. 1 (f)
In the epitaxial growth step, since the seed crystal is grown in the trench 52 to form the epitaxial growth layer 33, the lateral growth of the seed crystal is suppressed by the sidewall 54 provided on the sidewall of the trench 52, and the seed crystal is grown along the sidewall 54. Grow vertically. for that reason,
The lateral dimension accuracy of the epitaxial growth layer 33 is improved.

In the sidewall forming step shown in FIGS. 1D and 1E, the width of the sidewall 54 can be easily controlled by controlling the thickness of the silicon nitride layer 53. Therefore, the epitaxial growth layer 33 is formed. The size of
That is, the size of the element formation region can be set arbitrarily. Therefore, the degree of freedom in design is increased. It should be noted that the present invention is not limited to the above embodiment, and many changes and modifications can be made within the scope of the present invention.

[0030]

As is apparent from the above description, in the manufacturing method according to the first aspect of the present invention, the side wall is used to narrow the width of the connecting portion of the epitaxial growth layer with the silicon substrate to reduce the oxidation distance. Since it can be shortened, thermal oxidation can combine the field oxide layer under the epitaxial growth layer to shorten the oxidation time when disconnecting the connection between the silicon substrate and the epitaxial growth layer and reduce stress on the silicon substrate. it can.

As described above, since it becomes possible to shorten the oxidation time for element isolation and reduce the stress on the silicon substrate, the size of the epitaxial growth layer can be reduced by taking the stress into consideration as in the conventional case. Since it is not necessary to set it and the element formation region can be widened, the productivity is also improved. In the epitaxial growth process, the lateral growth of the seed crystal is suppressed by the sidewalls provided on the sidewalls of the trenches, and the lateral growth of the seed crystal in the vertical direction is performed, so that the lateral dimensional accuracy of the epitaxial growth layer is improved.

In the side wall forming step, the width of the side wall can be easily controlled by controlling the thickness of the silicon nitride layer. Therefore, the size of the epitaxial growth layer, that is, the size of the element forming region can be arbitrarily set. Can be set to increase the degree of freedom in design. Further, according to the manufacturing method of the second aspect, it is possible to provide the SOI substrate having a wide element formation region with less stress and high productivity.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing an SOI structure according to an embodiment of the present invention in the order of steps.

FIG. 2 is an enlarged cross-sectional view at the end of the process of FIG.

FIG. 3 is a sectional view showing an example of a semiconductor device having an SOI structure obtained by a manufacturing method according to an embodiment of the present invention.

FIG. 4 is a diagram showing a conventional SOI technique by an ELO method.

FIG. 5 is a cross-sectional view showing a method of manufacturing an SOI structure according to the prior art in the order of steps.

FIG. 6 is a cross-sectional view showing a method of manufacturing an SOI structure according to another prior art step by step.

[Explanation of reference numerals] 30 SOI substrate 32 Silicon substrate 33 Epitaxial growth layer 34 Field oxide layer 50, 50A, 50B Silicon oxide layer 52 Trench 53 Silicon nitride layer 54 Side wall

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (2)

[Claims] 1. A step of forming a silicon oxide layer on a silicon substrate to a first thickness, a trench is formed at a predetermined position of the silicon oxide layer, and the silicon oxide layer at the bottom of the trench is sufficiently thinner than the first thickness. Step of forming to a second thickness, after depositing a silicon nitride layer on the entire surface so as to fill the trench, the silicon nitride layer contacting the sidewall of the trench remains as a sidewall, and the surface of the silicon substrate at the bottom of the trench is exposed Until the silicon substrate is exposed at the bottom of the trench, the silicon of the silicon substrate exposed at the bottom of the trench is epitaxially grown as a seed crystal to form an epitaxial growth layer in the trench, and a field oxide layer is grown under the epitaxial growth layer to form a silicon substrate. Characterized by including a step of disconnecting the connection with the epitaxial growth layer Manufacturing method of OI structure. 2. The method for manufacturing an SOI structure according to claim 1, wherein in the step of disconnecting the connection between the silicon substrate and the epitaxial growth layer, the silicon oxide layer is entirely removed before disconnecting the connection between the silicon substrate and the epitaxial growth layer. And a step of removing the silicon oxide on the sidewalls and the epitaxial growth layer and burying the silicon oxide between the epitaxial growth layers after disconnecting the connection between the silicon substrate and the epitaxial growth layer. Method.