JPS58168259A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPS58168259A
JPS58168259A JP5186282A JP5186282A JPS58168259A JP S58168259 A JPS58168259 A JP S58168259A JP 5186282 A JP5186282 A JP 5186282A JP 5186282 A JP5186282 A JP 5186282A JP S58168259 A JPS58168259 A JP S58168259A
Authority
JP
Japan
Prior art keywords
silicon
film
oxygen
groove
filmlike
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5186282A
Other languages
Japanese (ja)
Inventor
Takashi Morie
隆 森江
「峰」岸 一茂
Kazushige Minegishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP5186282A priority Critical patent/JPS58168259A/en
Publication of JPS58168259A publication Critical patent/JPS58168259A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

PURPOSE:To isolate elements with each other via a complete filmlike silicon oxidized film by thermally oxidizing an oxygen-added thin silicon film formed in the groove formed on the surface of a silicon substrate, thereby eliminating an air gap presented in the oxygen-added thin silicon film and improper filmlike part. CONSTITUTION:An oxygen added thin silicon film 7 is thermally oxidized in dipped oxidative atmosphere to form a completely filmlike silicon oxidized film 72 having 2 of oxygen composition ratio to silicon. Air gap is compressed due to the volumetric expansion of the case that the film 72 is varied to obtain a completely filmlike property so that the volumetric expansion becomes small amount. Thus, no dislocation of crystal is produced in the silicon substrate 1. Then, the film 72 except the groove is removed by anisotropic etching, thereby forming a silicon oxidized film 73 only in the groove 4, and removing a silicon nitrided film 6 and a silicon oxidized film 5 on an element region 3. A silicon oxidized film 51, a silicon nitrided film 61 and a silicon oxidized film 73 are formed only in the inner surface of the groove 4, these insulators can isolate elements with each other, and the substrate 1 can be exposed on an element region 3.

Description

【発明の詳細な説明】 本発明は半導体集積回路装置の製造方法に係り、特に半
導体基板内に形成される台素子間を絶縁物により電気的
に分離する方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for electrically isolating base elements formed in a semiconductor substrate using an insulator.

従来、微細な素子間の分離法として、半導体基板の表厘
層の所定領域に溝を形成し、この溝の内部を電気的絶縁
物で充填する方法が知られている。
Conventionally, as a method for finely separating elements, a method is known in which a groove is formed in a predetermined region of a surface layer of a semiconductor substrate, and the inside of the groove is filled with an electrical insulator.

この分離方法の概要を第1図および第2図に遣い−ca
mすると、まず、嬉imlに示すように、シリラン基@
1上O素十Mを分離すべ暑所定領域K。
An overview of this separation method is shown in Figures 1 and 2.
m, first, as shown in happy iml, the silyran group @
1. A predetermined area K to separate O element 10 M.

レジストなどをマスタにして飼えば平行平板電極形グツ
ズ!エツナy 、、、l@置などを扇い九エツチング遮
直に方向懺をもクエツチング法(以下、異方性エツチン
グと−う)Kよ)壽を形成し、次いでシリコン酸化膜2
を化学的気相成長法(以下、OVD機と略記すh)Kよ
って堆積する。しかる後、嬉211に示すように、シリ
;ン酸化112を異方性エツチングにより除資すること
により、上記溝の内部にのみシリコン酸化膜21を形成
して素子間を分離する方法が行われて−る。
If you keep it as a master with resist etc., it will become a parallel plate electrode type dog! A silicon oxide film 2 is formed using a quenching method (hereinafter referred to as anisotropic etching) to directly etch the etching surface, and then a silicon oxide film 2.
is deposited by a chemical vapor deposition method (hereinafter abbreviated as OVD machine). Thereafter, as shown in Figure 211, a method was used in which the silicon oxide film 21 was removed by anisotropic etching to form a silicon oxide film 21 only inside the trenches, thereby isolating the elements. -ru.

しかし、このような従来の分離方法においては、第31
1に示すように、シリーン酸化属1oOVD法における
堆積の際溝の中央部に空隙および膜質O嵐くないシリコ
ン酸化物22が形成されやすい。
However, in such conventional separation methods, the 31st
As shown in FIG. 1, silicon oxide 22 without voids and a filmy O storm is likely to be formed in the center of the groove during deposition in the silicon oxide metal 1oOVD method.

そして、314図に示すように、上記異方性エツチング
の@Km不嵐不買膜質部分の部分に比べて適くエツチン
グされる九めに、エツチング後の溝の中央11KIII
い切れこみが発生するという欠点がめり九。
As shown in Fig. 314, the center 11KIII of the groove after etching is located at the ninth part, which is properly etched compared to the anisotropically etched @Km unfavorable film part.
The main drawback is that it causes cuts.

本発明は、上記した従乗の欠点を除去するため、シリコ
ン基板の素子間を分離すべき領域に層成した溝に、シリ
コンに対する酸素O鳳成比が2よりは小さい酸素添加シ
リコン薄膜を堆積し、この酸素添加シリコン薄膜を熱酸
化して上記鳳成比が20シリコン酸化膜を形成すること
により、上記酸素添加シリコン薄膜中に存在し九!Ig
Iおよび膜質O不良な部分をなくして完全な膜質のシリ
コン亀化膜にて素子間を分離することができる半導体集
積囲路装置の製造方法を提供するものでbる。
In order to eliminate the above-mentioned quadratic defect, the present invention deposits an oxygen-doped silicon thin film with an oxygen-to-silicon ratio of less than 2 in a groove layered in a region of a silicon substrate where devices are to be separated. Then, by thermally oxidizing this oxygen-doped silicon thin film to form a silicon oxide film with the above-mentioned oxidation ratio of 20, the oxygen-doped silicon thin film contains 9! Ig
The present invention provides a method for manufacturing a semiconductor integrated circuit device in which elements can be separated by a silicon oxide film of perfect film quality by eliminating portions with poor I and O film quality.

以下、本発明の実施例を図面について説明する。Embodiments of the present invention will be described below with reference to the drawings.

箒511PJI第9図は本発明による製造方法の一部1
1IA11i1を説明する丸めの素子間分嶋部の一部工
程断面図である。まず、11g5図に示すように、導電
形がP形でかつキャリア#I度にして1O14〜10”
m−’s*のシリョン基I[1,上の素子領域3以外の
素子間を分離すべき領域K114を形成する。このと亀
、溝4の形成に際してはシリコン基板1上にパターニン
グし友レジストを九はシリコン酸化膜等の耐エッチll
薄膜を!スフにして平行平板電1i拳グテズマエッチン
グ装置等を用いてシリコンaWtを異方性エツチングす
ればよい。例えば、上WiAシリコン基IEI上にパタ
ーニングし九厚さ1.8aslljlE()■−137
0からなるレジストを!スフとし、上記グッズマエッチ
ングatにより圧力50〜500siTorrのもとで
反応ガスCCI、F。
Broom 511PJI Figure 9 is part 1 of the manufacturing method according to the present invention.
1IA11i1 is a partial step cross-sectional view of a rounded inter-element dividing area. First, as shown in Figure 11g5, the conductivity type is P type and carrier #I degree is 1O14~10''
A region K114 is formed in which elements other than the element region 3 above the m-'s* series group I[1 are to be separated. In this case, when forming the grooves 4, patterning is performed on the silicon substrate 1 and a resist is used to resist etching of the silicon oxide film, etc.
Thin film! The silicon aWt may be anisotropically etched using a parallel plate electrode 1i etching apparatus or the like. For example, patterning on WiA silicon base IEI with a thickness of 1.8 aslljlE()■-137
A resist consisting of 0! The reactant gas CCI, F was applied to the above-mentioned Goods Ma etching at a pressure of 50 to 500 siTorr.

を用いてシリコン基41[1を^方性エツチングするこ
とによn、5saK示す如龜凹形状の濤4を形成で龜る
By etching the silicon base 41[1] laterally using etching, a concave shape 4 having a thickness of n,5saK is formed.

次に、III@IIK示すように、上記#$4の内部お
よび素子領域3上にシリコン基板1の界面状態を改善す
るため、熱酸化によりて基板温度900〜1100”o
o4とf厚1200〜2oooim度。
Next, as shown in III@IIK, in order to improve the interface state of the silicon substrate 1 inside the #$4 and on the element region 3, the substrate temperature was increased to 900 to 1100'' by thermal oxidation.
o4 and f thickness 1200~2ooooim degree.

シリコン酸化膜5を形成し、さらにその上KOvD法等
によって基板温度700−1000″C,反応ガスとし
てシランとアン毫ニアを用いて厚1B 00〜2ooo
!楢度のシリコン窒化1146を耐酸化性薄膜として形
成する。次いで、第7図に示すようK。
A silicon oxide film 5 is formed, and then a silicon oxide film 5 is formed on the film by KOvD method or the like at a substrate temperature of 700-1000''C and a thickness of 1B00-2ooo using silane and ammonia as reaction gases.
! A high-grade silicon nitride 1146 is formed as an oxidation-resistant thin film. Then, K as shown in FIG.

OVD法にヨp基[11j[700〜1000’ol 
反応カスとしてシラン、00..H,を用いてシリコン
に対する酸素の一成比が2よりは小さい酸素添加シリフ
ン薄属(8i0x 、 0 <x< 2 )7を゛堆積
する。このと艷]素添加シリコン薄jl[Tの膜厚はs
4j@”の2倍機度にする。を九、上記酸−添加シリコ
ン薄膜Tの堆積の1.そ□の内部に空隙を含む不要膜質
部分子1が#14の中央11KMi成されることがら”
          7.Ht、   □る・ そして、−8図に示すように、1m嵩添加シリ□コン薄
膜7を基板温g900〜1100℃のもとで湿った酸化
雰囲気中にて熱酸化し、シリコ/に対する酸素の組成比
が2となる完全な膜質のシリコン酸化1172を形成す
る。これにより、この熱酸化1橘におい−Cd、酸素添
加7す、2薄膜Tシ□リコン酸化11?2に変化する際
の体積膨張のために□不良膜質部分11中に存在した空
隙は圧縮され、不良膜質藪71彊膜質−向上して、完全
な膜質のシリコン酸化膜72が得られる。tた、上記0
1に応力を発生させることはなく、シたがって、結晶欠
陥も生じなくなる。
In the OVD method, the iop group [11j[700-1000'ol
Silane as reaction residue, 00. .. A thin layer of oxygen-doped silicon (8i0x, 0 < x < 2) 7 is deposited using H, in which the ratio of oxygen to silicon is less than 2. The film thickness of element-doped silicon is s
4j@". 9. 1. In the deposition of the acid-doped silicon thin film T, unnecessary film molecules 1 containing voids are formed at the center of #14 at a depth of 11 KMi. ”
7. Ht, □ Ru・ Then, as shown in Figure -8, the 1 m bulk-added silicon □ thin film 7 was thermally oxidized in a moist oxidizing atmosphere at a substrate temperature of 900 to 1100°C, and the oxygen A complete film of silicon oxide 1172 having a composition ratio of 2 is formed. As a result, the voids existing in the poor film quality portion 11 are compressed due to the volume expansion when the thermal oxidation 1 -Cd, oxygen addition 7, 2 thin film T silicon oxidation 11?2. , the poor film quality 71 is improved, and a silicon oxide film 72 with perfect film quality is obtained. t, above 0
No stress is generated in 1, and therefore no crystal defects are generated.

次いで、飼えば反応懺スパッタエッチン装置を用い、圧
力1−100storr、反応ガスとしてo′IP4と
H鳳を用い九J%方憔エッチ/グにょIf@9図に示す
よ□うに、溝部以外のシリコン酸化膜T2を除去するこ
とによりa $4の内部にのみシリコン酸化膜13を形
成し、最後に素子領域3上のシリーコン窒化属6および
シリ:1)酸化膳5を除去することによLIl14の内
直にのみシリコン酸化膜51゜シリコン窒化膜@1およ
寝シリコン酸化膜13が形成1れてこれら絶縁物にて素
子間を分離できるとと4に、素子領域3に′シリコン基
板1を露出させることかで自る。
Next, using a reaction sputter etching device, a pressure of 1-100 storr was used, and o'IP4 and H-ho were used as reaction gases. By removing the silicon oxide film T2, a silicon oxide film 13 is formed only inside a $4, and finally by removing the silicon nitride 6 and silicon oxide layer 5 on the element region 3, LIl 14 is formed. A silicon oxide film 51°, a silicon nitride film @1 and a silicon oxide film 13 are formed only directly within the element region 3, and these insulators can isolate the elements. You can be self-sufficient by exposing yourself.

なお、上述し九実施例ではJ114の内部を含むシリコ
ン基板面上にシリコン酸化膜5および耐酸化性薄膜とし
てのシリコン窒化膜6を積層して形成する場合について
示したが、本発明はこれに限定されるものではなく、シ
リコン基板の界面状態に応じて上記シリコン酸化膜5.
耐酸化性薄膜を適宜遥択した9、またシリコン基板もn
形のものを用い九9することなど種々の変更を行い得る
ことは勿論でbる。
In the above-mentioned nine embodiments, the silicon oxide film 5 and the silicon nitride film 6 as an oxidation-resistant thin film are laminated and formed on the silicon substrate surface including the inside of J114, but the present invention is not limited to this. The above-mentioned silicon oxide film 5.
A suitable oxidation-resistant thin film was selected9, and a silicon substrate was also used.
Of course, various changes can be made, such as using different shapes.

以上l!明したように本部@によれば、シリコン基板上
の表面に形成した壽の内部に酸素添加シリコン薄膜を形
成し、この酸素添加シリコン薄膜を熱酸化することによ
り、上記酸素添加シリコン薄膜の形成時に生じ丸溝中央
部の空隙および不実膜質部分を除去し得るので、完全な
膜質のシリコン酸化膜のみで溝を充填できるとともに、
平坦な分離領域を形成できる。また、上記熱酸化の際の
酸素添加シリコン薄膜の体積膨張はわずかであるので、
多結晶シリコンを熱酸化し九ときのようなシリコン基板
内の結晶欠陥は生じなくなるなどの効果がある。
That’s all! As explained, according to Headquarters @, an oxygen-doped silicon thin film is formed inside the container formed on the surface of a silicon substrate, and by thermally oxidizing this oxygen-doped silicon thin film, during the formation of the oxygen-doped silicon thin film, Since it is possible to remove the void in the center of the round groove and the unreliable film part, the groove can be filled with only a perfect silicon oxide film, and
A flat isolation region can be formed. In addition, since the volumetric expansion of the oxygen-doped silicon thin film during the above thermal oxidation is small,
This method has the effect of eliminating crystal defects in the silicon substrate, which occur when polycrystalline silicon is thermally oxidized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃I第4図は従来例を説明するための素子間分離
部の一部工程断面111、Ms図乃11j19図は本発
明による製造方法の一実施例をaf!Aする丸めの素子
間分離部の一部工程断面図である。 )・・シリコン基板、3・・・・素子領域、4・・・・
シリ:2y基41[#IlI画の溝、5.51・・・・
熱鹸化によって形成され九シリコン酸化膜、6、@1・
・・・シリコン酸化膜、7・・・・酸素511Aシリコ
ン薄属、71・・・・酸素添加シリコン薄膜T中に専在
する空隙を含む不嵐属質部分、72.73・・・・酸素
添加シリコン基板Tを熱鹸化して形成し九完全なシリコ
ン酸化膜。 特許出願人  日本電信電話公社 代理人 山 川 政 樹
FIGS. 1 to 4 are partial process cross-sections 111 of an element isolation section for explaining a conventional example, and FIGS. FIG. 6 is a partial process cross-sectional view of the rounded element isolation section shown in FIG. )...Silicon substrate, 3...Element area, 4...
Siri: 2y group 41 [#IlI picture groove, 5.51...
Silicon oxide film formed by thermal saponification, 6, @1.
...Silicon oxide film, 7..Oxygen 511A silicon thin metal, 71..Unstormy metal part containing voids exclusively in oxygen-added silicon thin film T, 72.73..Oxygen A complete silicon oxide film is formed by thermally saponifying the doped silicon substrate T. Patent applicant: Masaki Yamakawa, agent of Nippon Telegraph and Telephone Public Corporation

Claims (1)

【特許請求の範囲】[Claims] シリーン基板O主面の素子間を分離すべ龜領域に溝を形
成し、少くとも上記溝の内部な會むシリコン基板漏止に
、シリコンに対す為酸素の縄成比が2よpは小さい酸素
添加シリコン薄膜を形成し、酸化雰囲気中の熱処理によ
)上記親成比が20シリーン酸化膜に変える1鴨を含み
、上記シリコン酸化膜により素子間分離領域を作成する
ことを特徴とする半導体集積回路装置の製造方法。
A groove is formed in the area where the elements are to be separated on the main surface of the silicon substrate O, and at least the silicon substrate that meets the inside of the groove is leak-tight. A semiconductor integrated circuit comprising forming an additive silicon thin film and converting it into a silicate oxide film having an affinity ratio of 20 (by heat treatment in an oxidizing atmosphere), and creating an isolation region between elements with the silicon oxide film. A method of manufacturing a circuit device.
JP5186282A 1982-03-30 1982-03-30 Manufacture of semiconductor integrated circuit device Pending JPS58168259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5186282A JPS58168259A (en) 1982-03-30 1982-03-30 Manufacture of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5186282A JPS58168259A (en) 1982-03-30 1982-03-30 Manufacture of semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS58168259A true JPS58168259A (en) 1983-10-04

Family

ID=12898674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5186282A Pending JPS58168259A (en) 1982-03-30 1982-03-30 Manufacture of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS58168259A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124840A (en) * 1983-12-09 1985-07-03 Fujitsu Ltd Manufacture of semiconductor device
JPS6386449A (en) * 1986-09-30 1988-04-16 Toshiba Corp Manufacture of semiconductor device
JPS6392045A (en) * 1986-10-06 1988-04-22 Toshiba Corp Manufacture of semiconductor device
WO2005088694A1 (en) * 2004-03-16 2005-09-22 Ishikawajima-Harima Heavy Industries Co., Ltd. Process for fabricating semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124840A (en) * 1983-12-09 1985-07-03 Fujitsu Ltd Manufacture of semiconductor device
JPH0340948B2 (en) * 1983-12-09 1991-06-20
JPS6386449A (en) * 1986-09-30 1988-04-16 Toshiba Corp Manufacture of semiconductor device
JPS6392045A (en) * 1986-10-06 1988-04-22 Toshiba Corp Manufacture of semiconductor device
WO2005088694A1 (en) * 2004-03-16 2005-09-22 Ishikawajima-Harima Heavy Industries Co., Ltd. Process for fabricating semiconductor device
CN100466197C (en) * 2004-03-16 2009-03-04 石川岛播磨重工业株式会社 Method of manufacturing semiconductor device
US7645677B2 (en) 2004-03-16 2010-01-12 Ishikawajima-Harima Heavy Industries Co., Ltd. Method for manufacturing semiconductor device

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