JPS61288462A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the structure in which the periphery of the side planes and the bottom of the groove processed on a surface of a semiconductor substrate by self-alignment is surrounded with an impurity-doped layer by utilizing high-energy ion implantation. CONSTITUTION:By using an ion implantation mask 4 formed on an Si substrate 1 as a mask, boron ions B<+> are implanted by amout 3 MeV to form an ion implantation layer 3 about 5mum deep. By the lateral scattering of the ions implanted at that time, the ion implantation layer 3 shows a shape expanding in the inside of the substrate compared with the ion implantation mask 4. Next, a groove 2 is formed in the substrate 1 by reactive ion etching using the ion implantation mask 4 as a mask. At this time, the size shift of the groove 2 from the mask 4 due to RIE can be made smaller than that of the ion implantation layer 3, so that an impurity-doped layer 5 is formed on side walls of the groove 2. By the ion implantation with high energy, the ion implantation layer 3 which is much larger than the mask 4 in the deeper part of the substrate 1.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of manufacturing a semiconductor device.

This article relates to a semiconductor device manufacturing method that uses high-energy ion implantation technology to form a trench whose side surfaces are surrounded by an impurity-doped layer in a semiconductor substrate. ration structure can be formed.

[Background of the invention]

Conventionally, as a method of doping impurities into the side surfaces of a trench formed in a semiconductor substrate, PSG (Pho
A method of depositing a spho-3ijicate Glass (phosphosilicate glass) film and diffusing phosphorus from this PSG film to the side surfaces of the groove [IDM Technical Digest EDM Technical Dig
est +E, Arail (1983) 2-11
l Or a method of diffusing antimony by vapor phase diffusion of antimony [(1) Electro Chemical Society Journal J, Plectro, -chem, Soc.
+M, Namba et al. (1981)
128 (2) + 420 i (2) Electro Chemical Society J, Electroche'm,
Sac, M., Namba et al. (198
4) 131(1), 190 El, etc. have been proposed.

However, with any of these methods, it is difficult to diffuse impurities with low concentration and with high precision. The reason for this is due to the theoretical limit of thermal diffusion, and generally ±5% when the impurity concentration is lower than the solid solubility.
This is because it is technically almost impossible to control the concentration with an accuracy within 1.

For this purpose, a method is generally adopted in which a low concentration diffusion layer is formed using ion implantation technology.

According to the ion implantation method, since the amount of ion implantation can be controlled by the integrated current value, the concentration can be controlled with an accuracy of approximately ±1%. However, with conventional ion implantation techniques, it is nearly impossible to dope the side surfaces of a trench formed in a semiconductor substrate with impurities. The reason for this is due to the straightness of the implanted ions, as shown in Figure 2.
In order to form the impurity doped layer 9 in the groove 8 formed in the substrate 7, if the width of the opening of the groove 8 is W and the depth is d, the implantation angle θ is ian"-" (w/a). It is necessary to do the following. For example, in order to completely dope the side wall of a groove with a width W of 1 μm and a depth d of 5 μm with impurities, the implantation angle θ needs to be about 10 degrees or less. On the other hand, since the side surfaces of the groove to be doped with impurities may be oriented in any direction, the implantation angle θ needs to be changed three-dimensionally. In other words, 2 For example, the wafer is θ with respect to the ion beam.
Tilt, so-called.

It is necessary to have misosuri exercise. however.

This method is fundamentally limited in two ways.

One point is that it is difficult to dope the bottom of the groove.
Another point is that the amount of ion implantation cannot be accurately controlled. That is, the total number of ions implanted into the semiconductor substrate can be monitored;

It is nearly impossible to accurately measure the number of ions implanted into the side surfaces of the groove, so it is impossible to form a doped layer with the desired characteristics by implanting ions from an oblique direction as described above. Can not.

[Purpose of the invention]

The present invention was made in order to solve the above-mentioned problems in the conventional technology, and it forms a groove in a semiconductor substrate whose entire side surface including the bottom surface is surrounded by a precisely controlled impurity doped layer. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can perform the following steps.

[Summary of the invention]

In order to achieve the above object, the present invention includes a step of forming an ion implantation mask on a semiconductor substrate.

A step of performing ion implantation using the ion implantation mask as a mask to form an impurity-doped layer in the semiconductor substrate, and etching the semiconductor substrate in a portion not covered with the mask so that the impurity-doped layer is formed around the side surfaces. The manufacturing method includes the step of forming a groove surrounded by.

The principle of the present invention will be specifically explained using FIG. 1st
In the figure, boron ions B+ are implanted at 3 MeV using an ion implantation mask 4 formed on a silicon substrate 1 as a mask.
This figure shows the state in which an ion implantation layer 3 having a depth of 5 μm was formed by implantation. At this time, the ion implantation layer 3 is caused by lateral scattering of the implanted ions.

FIG. 1(b), which has a shape that is wider inside the substrate than the ion implantation mask 4, is a groove formed in the substrate l by two-reactive ion etching (hereinafter abbreviated as R1B) using the ion implantation mask 4 as a mask. 2 is shown. At this time,
From Mask 4 by RIE.

Since the dimensional shift of the groove 2 can be smaller than that of the ion implantation layer 3, the impurity doped layer 5 can be formed on the sidewall of the groove 2. By performing ion implantation with high energy, it is possible to form an ion implantation layer 3 that is sufficiently wider than the mask 4 in the deep part of the substrate 1, but it may not necessarily be possible to form an ion implantation layer 1 minute wider near the surface of the substrate 1. Subsequent etching may remove the impurity doped layer.

However, the depth of the portion where the impurity doped layer is removed is approximately 0.5 μm at most, and this portion can be sufficiently doped by ordinary channel doping, etc., so this does not pose a particular problem.

[Embodiments of the invention]

Two embodiments of the present invention will be described below.

Example 1 FIG. 3(a) shows a resistivity of 1OΩ and my silicon substrate 1o.
A thermal oxide film 11 with a thickness of 20 nm is deposited on the p-type (100) plane of the
After growing, a silicon nitride (Si3H4) film 15 is grown to a thickness of 120 mm using a chemical vapor deposition (OVD) method.
nm deposited, further forming an ion implantation mask 12,
Apply 2.5 B+ to the area not covered by this mask 12.
This figure shows the state in which the ion implantation layer 13 was formed by implanting at MeV and an implantation amount of 3 x 10"F-2. Under these implantation conditions, a maximum concentration of 2.5 017c was implanted at a depth of about 3 μm.
Four B+ ion-implanted layers 13 having a concentration of rIL-3 and a junction depth of approximately 4 μm are formed. Furthermore, the lateral spread of the ion implantation layer 13 at the maximum concentration depth is approximately 0.7 μm.
Met.

FIG. 3(b) shows a state in which the silicon substrate 10 is etched by parallel plate type RIE using the ion implantation mask 12 to form a groove 14 with a depth of 3.5 μm.

Bromide trifluoride methane (0BrFa) was used as the reaction gas, and processing was carried out under the conditions of a pressure of 0.3 Torr and a reaction power of 100W. With these etching conditions, groove 1
The dimensional shift of No. 4 from the mask 12 is 0.1 μm or less.

A sufficient amount of the doped layer 13 could be left on the side wall of the groove 14.

FIG. 3(c) shows that after removing the ion implantation mask 12, the inner wall of the groove 14 is etched for a leap second with an etching solution of hydrofluoric acid:nitric acid=1:200 (volume ratio) to remove damage caused by RIB. The damaged layer of approximately 0.05 μm is removed, and then oxidized again to form a 0.2 μm thick layer on the inner surface of the groove.
A thermal oxide film 16 is grown, and a polycrystalline silicon layer is further deposited by the CVD method to fill the voids in the trench, and the excess polycrystalline silicon is removed to form a trench-burying layer 17. .

According to this embodiment, a good trench isolation structure can be formed. When used in, for example, a C-MOS, the threshold voltage vTH of the isolation structure is 2QV or more, resulting in complete isolation. In addition.

In the above embodiment, it has been described that the trench 14 is filled with polycrystalline silicon, but 2 ordinary silicon dioxide (sloQ) is used.

It goes without saying that it is also possible to fill in the groove 14 by CVD of an insulating film such as PSG, and it is also possible to completely fill the trench 14 only by thermal oxidation.

Example 2 This example is an example in which p-type and p-type impurity doped layers are left on the sidewalls of the trench.

Figure 4(a) shows p-type (100) plane, resistivity 10Ω-m.
A thermal oxide film 11 with a thickness of 20 nm is formed on a silicon substrate 10 of
5IBN4 film with a thickness of 50 nm15. After depositing 2 PSG films 1 with a thickness of 400 nm using the CVD method, an ion implantation mask (for example, tungsten) 12 is formed.

Using this ion implantation mask 12 as a mask, PSG
Film 2 on film 1 Si, N4 film 15. Thermal oxide film 11 is 0H2
A state removed by RIE using FQ gas is shown.

In FIG. 4(b), using the ion implantation mask 12 as a mask, B is set at 2-OMeV and As is set at 3-OMeV. OM
3 x 1013 cm-2 and 5 x respectively in eV
After implanting 1014 m −2 , a groove 14 with a depth of 4 μm was formed in the silicon substrate 10 again by RIE, and then,
Ion implantation mask 12. 1 Si on 2 PSG films
The figure shows a state in which the N4 film 15 and the oxide film 11 are removed and heated in an oxidizing atmosphere to form a thermal oxide film 16 on the inner wall of the trench 14 and the surface of the silicon substrate 10. At this time, groove 14
An n-type diffusion layer 19 and a p-type diffusion layer are formed around the sidewalls.

Figure 4(c) shows C! After depositing polycrystalline silicon to a thickness of 0.6 μm using the VD method to completely fill the groove 14, a resist pattern is formed and etching is performed to remove the polycrystalline silicon deposited on the substrate except for the necessary portions. A state in which a polycrystalline silicon layer 18 is formed is shown.

At this time, an n-type diffusion layer 19 and a p-type diffusion layer with an applied force λ are formed on the side surfaces of the groove. The reason for this is that boron B and arsenic As
due to differences in diffusion coefficients in thermal diffusion.

That is, As has a smaller diffusion coefficient than B, so a shallow junction is formed, whereas B has a larger diffusion coefficient, so a deep junction is formed. Therefore, in order to form a deep n-type layer and a shallow p-type layer, for example, phosphorus (P) and gallium (Ga) may be used as impurities. Note that the above thermal oxide film 16 is r S IO2/5IJIN4
It goes without saying that a laminated structure such as /5IO11 or the like can be used, and other insulating films 2 having a large dielectric constant such as 'ra, o, etc. can also be used.

Example 3 In this example, an impurity doped layer is left not only inside the substrate but also on the side surfaces of the groove near the surface of the substrate.

FIG. 5(a) shows a p-type (100) plane, resistivity 10Ω, silicon substrate 10 subjected to normal selective oxidation (LOcO8).
After growing a thermal oxide film 11 with a thickness of 30 nm in a state where an oxide film 22 for element isolation and a p-type channel stopper swamp were formed by the method, a 0.8 μm thick thermal oxide film 11 with a thickness of 0.8 μm was grown on two PSG films with a thickness of 0.5 μm. After depositing each tungsten suspension,
Tungsten suspension and PSG in the area where grooves are to be formed
A state in which the film 21 is processed using the resist pattern 5 as a mask is shown. At this time, an ion implantation mask is formed by taper etching the tungsten film.

FIG. 5(b) shows resist pattern 5. Using the taper-etched tungsten suspension and PSG film 21 as a mask, B+ was 5X1013cm2+ at 2 MeV and A
This figure shows a state in which a B ion implantation layer 20 and an As ion implantation layer 19 are formed by performing ion implantation of s+ at 3 MeV and I x 10"cm-"y respectively. The shape of these ion-implanted layers 19, 20 is determined primarily by the shape of the tungsten film. That is,
Ions are not implanted in the portions where the tungsten plate is present, shallow implantation layers are formed in the tapered portions, and deep ion implantation layers are formed in the portions where there is no ion implantation mask. Therefore, the shape of the ion-implanted layers 19 and I is not a "pear" shape with a downward bulge as shown in Example 1 (FIG. 3), but can be doped more uniformly.

In FIG. 5(C), using the resist film 5° PSG film 21 in FIG. 5(b) as a mask, the silicon substrate 10 is processed almost vertically to form a groove, and then the resist film 5° tungsten film 24. PSG film 21. After removing the thermal oxide film 11, a thermal oxide film 26 with a thickness of 6 nm is formed. 0 with a thickness of 15 nm
VA) A nitride film n and a 3 nm thick thermal oxide film grown by thermally oxidizing the nitride film τ are formed, and a gate 18 made of polycrystalline silicon doped with phosphorus is further formed.

FIG. 5(d) shows that from the state of FIG. 5(C), 9 interlayer oxide films A, gate oxide film A, tungsten gate 4, and 2 interlayer PSG films 31 between arsenic ion implantation layers are formed on the silicon substrate 10 from the state shown in FIG. 5C.
．． A state in which Al interconnections 32 are sequentially formed to form a memory cell of a typical dynamic random access memory is shown.

In this example, the reason why the B+ doped layer spreads wider than the As+ doped layer 19 is because (1) the lateral dopant of impurities during ion implantation is thicker in layer B, and (2) the heat treatment after implantation The diffusion of impurities is faster in B than in As,
This is due to two reasons.

As described above, according to this embodiment, it is possible to form a structure in which the side and bottom surfaces of the groove are surrounded by the impurity-doped layer in a self-aligned manner.

〔Effect of the invention〕

As explained above, according to the present invention, high-energy ion implantation forms a structure in which the side and bottom surfaces of a groove processed in a semiconductor substrate are surrounded by an impurity-doped layer in a self-aligned manner. The technical effects are great.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are sectional views for explaining the outline of the present invention. Figure 2 is a diagram explaining the problems of the prior art, and Figure 3 (aL
(bL (cL) Figure 4 (aL (b), (c)
,, Figures 5(a), (bL(C), and (d) are cross-sectional views explaining the present invention in detail, respectively. <Explanation of symbols> 1.10...Silicon substrate 2,14°° Groove 3
, 5.13.19.20... Impurity doped layer (ion implantation layer) 4.12... Ion implantation mask 11, 16.26.28... Thermal oxide film 15... Silicon nitride film 17, 18°°゛Polycrystalline silicon layer 21
．． 31...PSG film ρ...Oxide film for element isolation B...P-type channel stopper 4...Tungsten gate (to)...Arsenic ion implantation layer 32...AI wiring 33...Interlayer Oxide film praise...Gate oxide film agent's patent attorney Junnosuke Nakamura 1 Figure 3 - Ion implantation tube 1'2 Figure θ-・Isai> Dimension 2 or Kano Palm contract U--Ichimon Mouth 1 Hinobu Nobu d--Ichisakite? Figure 4, Figure 5 (Q) (b) Figure 5 (C) (d)

Claims (1)

[Claims] forming an ion implantation mask on a semiconductor substrate; performing ion implantation using the ion implantation mask as a mask to form an impurity doped layer in the semiconductor substrate; A method of manufacturing a semiconductor device, comprising the step of etching a substrate to form a groove whose side surfaces are surrounded by the impurity-doped layer.