JPH0384925A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a capacitor electrode part having an n<+> layer of a definite concentration by a method wherein p-type ions are implanted into a sidewall and a bottom part of a first recessed part and n-type ions are implanted into the bottom part of the first recessed part so as to offset a p<+> layer. CONSTITUTION:An SiO2 film 2 is formed on a p-type substrate 1 by a thermal oxidation method and a CVD method; a first recessed part 3 is formed in a separation part and a trench capacitor formation part by a dry etching operation by using a selective photoresist mask. Boron ions 4 are implanted into sidewalls in all directions four times obliquely by a 90-revolution step ion implantation operation to form a p<+> layer 5. Then, arsenic ions 17 are implanted four times obliquely by a 90-revolution step ion implantation operation. Thereby, a boron ion implantation layer at a bottom part of an implated groove is offset and transformed sufficiently into an n-type. Since a concentration of the p<+> layer in sidewalls of a second deep recessed part directly under the first recessed part is offset by an n-layer and suppressed, a p<+> high concentration part is not produced in a storage node to be formed later and an n<+> layer can be formed in a state having a uniform concentration.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, and specifically relates to a method of manufacturing a high-density LSI, especially a high-density memory. SCC structure (Surrounde
dCapacitor Ce1l) was reported by the present inventors at the 1987 Solid State Device Conference 77, but the method shown in Figure 4 was used in this report. This is done based on the process cross-sectional diagram in Figure 4. In the step (a) of the same figure, a 5-IFT film 2 is formed on a p-type Si substrate 1, and the formation portion of a trench capacitor that shares isolation is vertically etched using the 5-Ide film 2 as a mask to form a first recess 3. Then, in step (b), a p region 5 is formed by boron ion implantation 4, and a source (upper part) is formed after that.
An n+ region 18 is formed on the sidewall above the p+ region 5 by arsenic ion implantation 17 in the area where connection between the storage node (bottom) and the storage node (lower part) is required.Next, in step (C), a CVD 5iO* film with excellent coverage is formed. Then, the sidewall 5iO26 was left by etching with strong verticality and (
d) In the process, the second
Silicon etching is performed to form the recess 7.

Then, boron ions 8 are implanted into all the side walls to form a p layer 9, and then As ions 10 are successively implanted into all the side walls to form an n0 layer 11. If the second recess is formed, the following problem may occur, which will be explained using Fig. 5.
Boron was step-implanted four times at a dose of Xl0'''Cm-'', and the distribution of boron in the immediate vicinity of the sidewall S i O *6 is shown in FIG. 10”c
Even if the part with a slightly higher concentration of "m-" exists slightly below the sidewall, the figure (b) shows that the acceleration energy is 150 keV and the dose is 2 x 10 in the first recess.
The force that is the same dark green as the concentration of As atoms when step ion implantation of "cm-" is performed four times < The concentration of As at the part where the boron concentration shown in (a) is 10 cm (approximately equivalent) Even if it is, the force that causes part of the n0 layer of the capacitor electrode to be canceled by the 90 layer and cut \
Or (Yo) If a voltage of 100% is applied to the storage node formed after forming the capacitor, it becomes depleted and not only does it no longer function as a 1.% n layer, but also the connection with the source of the upper transfer gate transistor. It gets cut off.

With conventional methods like this, the operation of the memory cell becomes unstable or the memory cell becomes inoperable within a special narrow voltage range.One way to solve this problem is to improve the performance of semiconductor devices. Although one of the inventors has filed a patent application (Application No. 63-5155) for the manufacturing method, this is a method in which the high concentration portion of PO is removed by etching a slight additional recess after the first recess is formed. However, according to this method, the number of steps increases because dry etching is performed once, and the process cost increases because minute precision etching is required.
To provide a method for manufacturing a semiconductor device in which a capacitor electrode part having a constant concentration of n0 layer can be formed without the part of n4 layer on the side wall of the capacitor being canceled by the 93 layer when forming a memory cell of CC structure. With the goal.

Means for Solving the Problems The present invention solves the above-mentioned problems by:
a step of implanting p-type ions into the side walls and bottom of the first recess, and a step of implanting p-type ions into the bottom of the first recess so as to cancel out the p-layer formed by the p-type ion implantation.
a step of implanting type ions, a step of depositing an insulating film on the semiconductor substrate, and etching the insulating film using an etching method with excellent verticality to leave the insulating film on the side wall of the first recess. forming a second recess by performing trench etching using the insulating film left on the side wall of the first recess as a mask; and forming at least an n layer on the side wall of the second recess. According to the present invention, with the above-described structure, the concentration of the 99 layer on the side wall of the deep second recess immediately below the first recess is suppressed by being canceled by the n layer. A high p0 concentration area is formed in the storage node to be formed, and the i';n'' layer is formed with a uniform concentration.As a result, a dynamic RAM cell with stable characteristics can be formed. Although the explanation will be based on a specific example, FIGS. 1(a) to 1(f) are process cross-sectional views showing a method for manufacturing a semiconductor device. 5ide film 2 to about 1μ by thermal oxidation and CVD method.
Then, the first recess 3 is formed by dry etching using a selective photoresist mask for the isolation part and the trench capacitor forming part. The depth of t is 0.6 μm.
And acceleration energy 30 keys, dose amount 1
, 5 x 10 “cr” (7) boron ion implantation 4
The 99 layer 5 is formed by injecting the ion implantation diagonally four times into the sidewalls in all directions using 90 rotation step ion implantation.Next, in step (b), the acceleration energy is 150 keV and the dose is 2X.
10 "cm-" arsenic ion implantation 17 diagonally 4 times 90
As a result of the rotational step ion implantation, the boron ion implanted layer at the bottom of the groove implanted in step (a) is canceled out and the implantation becomes sufficiently n-type. This implantation profile is shown in Figure 2 (a). ) is the conventional one & (b
) is the method of the present invention a) is the method of the present invention? ! Even if the impurity concentration of As is completely higher than the impurity concentration of B,
In the process (C), the resistance is 5ins by low pressure CVD method.
A layer with a thickness of 0.15 μm was formed, and a layer of 5 inches was vertically etched using a reactive ion etching method to form the sidewall 5.
After forming iOe6, in step (d), a second recess 7 is formed by deep trench etching using these 5iOe6 as a mask, and boron 8 and As10 are implanted as in the conventional example. layer 9n°
After layer 11 is formed, the trench is further dug in step (e) and B0 ions are vertically implanted to increase the concentration of the bottom p layer 19. If this method is used, a nearly completed dynamic The cross-sectional view of a RAM cell is (
f), the source 12, gate 13.f) of the LMOS transistor. Drain 14 and 1. A polysilicon plate 15 with a thin oxide film sandwiched therebetween is formed in the second recess 7, and the upper part is filled with low pressure CVDSiO2. The word line 16 is formed at the same time as the gate 13 is formed, and here the source 12 and the capacitor storage electrode 11 are connected, and the drain 1
As described above, according to this embodiment, it is possible to sufficiently connect the source and storage electrodes even though they are separated from 4. Therefore, a very good capacitor portion is formed on the side wall. Figure 3 shows the dependence of the capacitance of the capacitor formed by these methods on storage node voltage changes based on the capacitance (C) at 07. In this case, the plate voltage is fixed at 1.5V. However, the conventional method and method a of the present invention are completely the same trench forming method.The conventional method results in partial depletion and the capacitance decreases rapidly. As a result, the C/C value was approximately 85% at 3V, and good characteristics were obtained without a large drop in capacity.Furthermore, in the depth direction of the side wall of the first recess (from Dynamic R is achieved by selecting the energy that allows p-type atoms to penetrate deeply.
In this example, As ions were used as the n-type layer.
5tP ions are also equivalent, but regarding the fact that As ions cancel the boron layer, it is necessary that the state of cancellation occurs after thermal diffusion occurs in all heat treatments performed during the process, and it must be completely canceled immediately after implantation. Effects of the Invention As described above, according to the present invention, the concentration of the 92 layer on the side wall of the deep second recess immediately below the first recess is suppressed by being canceled by the n layer. A high p0 concentration area is generated in the node, and the n layer is formed with a uniform concentration, resulting in the formation of a dynamic RAM cell with stable characteristics.

[Brief explanation of drawings]

Figure 1 is a process cross-section showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 is the depth distribution of atomic concentration in the present method and the conventional method. Figure 3 is the storage node voltage of the SCC capacitance. Figure 4 shows the process cross-section of the conventional semiconductor device manufacturing method, and Figure 5 shows the atomic concentration contour diagram of the conventional process.

Claims (2)

[Claims] (1) A step of forming a first recess in a semiconductor substrate, a step of implanting p-type ions into the side walls and bottom of the first recess, and a step of implanting p-type ions into the bottom of the first recess.
A step of implanting n-type ions to cancel out the ^+ layer,
Thereafter, a step of depositing an insulating film on the semiconductor substrate, a step of etching the insulating film using an etching method with excellent verticality to leave the insulating film on the side wall of the first recess, and A method for manufacturing a semiconductor device, comprising: forming a second recess by performing trench etching using an insulating film left on the side wall of the recess as a mask; and forming at least an n layer on the side wall of the second recess. (2) In the vertical direction of the side wall of the first recess, the p-type atoms are introduced deeper than the n-type atoms, and in the bottom of the first recess, the n-type atoms are introduced deeper than the peak position of the p-type atoms. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the ion implantation energy for forming the semiconductor device is selected.