JPH0235714A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To control leak current by a method wherein the part of a gate controlled diode is made an LDD structure by forming a high concentration PN junction on the side wall of a recessed part, and at the same time by setting a gradient in the concentration of a diffusion layer, only in the bottom of the recessed part. CONSTITUTION:After a first resist film 6 is flatly spread on a silicon substrate 1 on which a step-difference is formed, a first oxide film 2 is formed thereon; after a second resist film 8 is spread thereon, the film 8 is patterned; by using this resist film as a mask, the oxide film 2 is etched; by using this oxide film as a mask, the resist film 6 is etched so as to be left only in the bottom of a recessed part 3, and a mask for ion implantation is formed; then oblique ion implantation of As<+> and B<+> with respect to the normal of the substrate is performed, thereby forming an N<+> diffusion layer on the side wall of the recessed part, and forming a P<+> layer on the side wall and in the bottom. As the result of this process, as to the recessed part bottom side wall, its impurity concentration of the part masked by the resist film 6 decrease toward the depth direction of the recessed part, and an N<+> region and a P<-> region are formed. Thus, in the self alignment manner, an LLD structure is formed in the recessed part bottom side wall.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a DRAM memory cell using a trench capacitor.

2. Description of the Related Art A part of a conventional method for manufacturing a DRAM memory cell using a trench capacitor is shown in FIG. First, a first oxide film 2 serving as a mask for silicon etching and ion implantation is formed on a silicon substrate 1, and then the silicon substrate 1 is etched to form a recess 3. Furthermore, As+ ions are obliquely implanted into the sidewalls and bottom of the recess 3 to form an n+ diffusion layer 4 that will serve as a storage node. Furthermore, Hi-
B+ ions are implanted into the side walls and bottom of the recess 3 to obtain the structure. Thereafter, in order to perform cell isolation, the recess is further dug down and vertical B+ ions from which the n+ diffusion layer at the bottom of the recess 3 has been removed are injected vertically to form a p+ diffusion layer at the bottom of the recess. After that, as shown in FIG.
After forming a polysilicon buried electrode 10, a switching transistor is formed to complete a memory cell. However, in the conventional technique, the controllability of the step of re-digging the recessed portions of the substrate for performing cell separation becomes poor. Further, as shown in FIG. 5B, a gate control diode is formed at the bottom of the recess, and leakage current from the n+ diffusion layer 4, which is a storage node, to the substrate 1 becomes a problem.

Problems to be Solved by the Invention As described above, in the prior art, gate-controlled diodes are formed at the bottom of the four parts of the substrate. Furthermore, in order to prevent the electrical floating of the switching transistor due to the elongation of the depletion layer of the pn junction on the side wall of the recess as devices become highly integrated, the concentrations of the p+ layer 5 and the n+ layer 4 are also increased.
There is a constraint that the growth of the depletion layer must be suppressed. This highly doped pn junction tends to increase leakage current from the viewpoint of the gate-controlled diode.

In view of these points, the present invention achieves a high concentration pn junction on the side wall of the recess, and at the same time creates a gradient in the concentration of the diffusion layer only at the bottom of the recess, thereby converting the gate conductor diode into an LD.
The purpose of the D structure is to suppress leakage current.

Means for Solving the Problems The present invention provides a method in which a first layer is formed on the entire surface of the substrate including the recesses formed in the substrate.
a step of uniformly applying a resist film, a step of forming a silicon oxide film on the resist film, and a step of forming a second resist film on the silicon oxide film of E by photolithography, etching the silicon oxide film using the resist film as a mask; and etching a second resist film using the silicon oxide film remaining from the above process as a mask to form a resist film only on the bottom of the four parts of the substrate. This is a method of manufacturing a semiconductor device, which further includes a step of obliquely implanting impurity ions into the sidewall and bottom of the recess newly created in step E.

Function: According to the present invention, an LDD structure can be easily formed in a self-aligned manner at the bottom of a recess through the steps described above, and junction leakage current on the sidewalls of the bottom of the recess can be suppressed. Furthermore, by using a three-layer resist, a resist film can be formed at the bottom of the recess while masking the non-implanted region, making it possible to apply the present invention to actual devices, particularly DRAMs having trench capacitors.

Embodiment An embodiment of the present invention will be explained based on the process cross-sectional views of FIGS. 1 and 2. First, a first resist film 6 is evenly applied to a silicon substrate 1 having a step shown in FIG. 3, and then a first oxide film 2 is formed on the resist film 6, and then a second After coating the resist film 8, the resist film 8 is patterned (FIG. 2(a)). Next, as shown in Figure 2 (using the above resist film as a mask, the first
The oxide film 2 is etched. Further, as shown in FIG. 2(C), etching is performed using the oxide film as a mask so that the first resist film 6 remains only at the bottom of the recess 3. This forms a mask for ion implantation. ,
As shown in FIG. 1(a), As+ and B+ ions are implanted obliquely at 7 degrees to the substrate normal to the entire surface to form an n+ diffusion layer on the sidewalls of the recess and a p+ layer on the sidewalls and bottom. As a result of the process, the impurity concentration of the portion of the bottom sidewall of the recess that is masked by the resist film 6 decreases as it goes in the depth direction, as shown in FIG. 1(b), forming an n+ region and a p- region. In this way, an LDD structure is formed on the bottom side wall of the recess in a self-aligned manner.

As described above, in the present invention, when a resist film is formed only at the bottom of a substrate recess and impurity ions are implanted into the side walls of the recess, the impurity concentration in the g4 wall portion masked by the resist film at the bottom of the four parts is lowered than in the other side wall parts. By doing so, the leakage current of the gate-controlled diode is suppressed. When implanting impurities into the sidewalls of the recess, due to the effect of the resist film at the bottom of the recess, the amount of directly incident ions reaching the sidewall portion masked by the resist film decreases toward the bottom of the recess. Furthermore, experiments have revealed that when oblique ion implantation is performed on the sidewall of a narrow recess, the opposite sidewall where ions are directly incident is also doped at a considerable concentration. Figure 3 shows As+ ions being accelerated at an angle of 7.5° to the side wall of a recess with an aspect ratio of 15 at an energy of 150 kevl and a dose of 1.07 x 10 /cJ.
The depth direction profile of the As+ ion concentration is shown as a result of SIMS analysis at three points 1 to 3 on the direct incidence region of the ions and the opposite side wall when the ions are implanted. It can be seen that the opposite side wall, on which ions should not be incident, is also doped at a certain concentration. Therefore, if this effect is also taken into account, a considerable concentration difference will occur between the side wall of the recess and the side wall masked by the resist film, and an LDD structure will be formed in a self-aligned manner.

Further, by using a three-layer resist in which a resist film, a silicon oxide film, and a resist film are stacked for patterning, it is possible to effectively mask the non-implanted region and form a resist film at the bottom of the recess.

As described in detail, according to the present invention, a DD structure can be formed on the bottom side wall of a recess through an extremely easy process, and leakage current caused by a gate conductor diode that occurs when a capacitor is subsequently formed can be suppressed. It becomes possible to do so. Furthermore, the non-implanted region can be masked using the three-layer resist, which has a great practical effect.

[Brief explanation of the drawing]

Figures 1 and 2 are cross-sectional views of a part of the manufacturing process showing an embodiment of the present invention, and Figure 3 is a side wall of the recess, a region where incident ions are directly incident when performing oblique ion implantation, and the opposite side wall. Characteristic diagrams showing the impurity concentration profile of
The figure is a sectional view of a part of the manufacturing process of a conventional method. 4...n+diffusion layer, 4゛...n-+
n− diffusion layer, 5...p+ diffusion layer, 5'...
...p+-"p- diffusion layer, 6...first resist film, 7...second oxide film, 8...second resist film. Substitute Person's name: Patent attorney Shigetaka Awano 1 person 1 Figure/-1 PC board Figure 7- 2nd [Oxide film 8-11 2nd resist film

Claims (1)

[Claims] A step of uniformly applying a first resist film over the entire surface of the substrate including the recesses formed in the substrate, a step of forming a silicon oxide film on the resist film, and a step of forming a second resist film on the silicon oxide film. a step of forming a resist film by photolithography, a step of etching the silicon oxide film using the resist film as a mask, and etching the second resist film using the silicon oxide film remaining from the above step as a mask. A method for manufacturing a semiconductor device, comprising the steps of leaving a resist film only on the bottom of the substrate recess, and further obliquely implanting impurity ions into the side walls and bottom of the recess newly created by the above step.