JP2581302B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2581302B2 JP2581302B2 JP2307688A JP30768890A JP2581302B2 JP 2581302 B2 JP2581302 B2 JP 2581302B2 JP 2307688 A JP2307688 A JP 2307688A JP 30768890 A JP30768890 A JP 30768890A JP 2581302 B2 JP2581302 B2 JP 2581302B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- forming
- layer
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 238000000034 method Methods 0.000 title claims description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000005468 ion implantation Methods 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 57
- 150000002500 ions Chemical class 0.000 description 17
- 239000003990 capacitor Substances 0.000 description 10
- 238000001459 lithography Methods 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に半導体記
憶装置において記憶容量が基板に溝を設けて、その部分
に形成されている溝型セル容量部を有するMOS型DRAMに
おける溝容量側壁へのイオン注入法に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor memory device in which a storage capacitor has a groove in a substrate, and a groove-type cell capacitor formed in that portion. The present invention relates to a method of implanting ions into a trench capacitor sidewall in a MOS DRAM having a portion.
半導体記憶装置としては、１個のMOSトランジスタと
これの直列に接続された容量をもつ１トランジスタ１キ
ャパシタメモリセルから構成してあることが多い。従来
のこの種の半導体記憶装置の製造方法の代表例について
図面を参照して説明する。ここで半導体基板１はＰ型シ
リコン基板とする。In many cases, a semiconductor memory device is composed of one MOS transistor and one transistor and one capacitor memory cell having a capacity connected in series. A typical example of a conventional method of manufacturing this type of semiconductor memory device will be described with reference to the drawings. Here, the semiconductor substrate 1 is a P-type silicon substrate.
まず、第８図に示す如く、半導体基板１へ窒化膜２を
形成後リソグラフィー工程を経て、素子分離領域とする
所望の箇所へバンチスルー防止のためのB+イオンを注入
し、p+層３を形成する。次に第９図の様に、半導体基板
１をLOCOS法により酸化し、素子分離領域となるフィー
ルド酸化膜４を形成し、窒化膜２を除去する。次にリソ
グラフィー工程を経て、所望の箇所にAs+イオンを注入
し、濃度1018cm-3、深さ0.3μｍのn+層５を形成する。
次に第10図に示す様にフォトレジスト６を塗布し、リソ
グラフィー工程を経て所望の箇所にn+層５を達する開口
を開け、開口部の半導体基板１をエッチングして容量を
形成する為の溝７を形成する。次いで溝７の側壁へ容量
増加及びソフトエラー低減の為にB+イオンを、ななめ回
転イオン注入し、p+層８を形成する。この時、図の場合
では斜めイオン注入角θをθ＝０゜（垂直）〜55゜の範
囲で変化させて、溝７内のボロン濃度が一様になるよう
にイオン注入していた。しかし、この方法では隣接する
フィールド酸化膜４の下のp+層３と溝開口側壁部のp+層
８が重なるp+層の重なり部21が出来てしまい、この部分
だけボロン濃度が高くなる。この為、のちに形成される
ｐ−ｎ接合の空乏層幅がp+層の重なり部21で局所的に薄
くなる可能性がある。その結果、この部分だけ電界が集
中し、リーク電流が多くなり、絶縁耐圧も低くなる可能
性をもっている。また、イオン注入の際にシリコン基板
に発生する結晶欠陥が残留しやすくなり、リーク電流が
多くなる可能性がある。つまり、溝容量の電荷蓄積時間
が著しく低下し、DRAMとしての機能を果たす事がむずか
しくなる。以上のように、従来の技術では溝側壁上部だ
けの注入、または溝内全域への注入しか実現出来ず、溝
開口側壁上部以外へイオン注入することは出来ない。First, as shown in FIG. 8, after a nitride film 2 is formed on a semiconductor substrate 1, through a lithography process, B + ions for preventing bunch-through are implanted into a desired portion to be an element isolation region, and a p + layer 3 is formed. To form Next, as shown in FIG. 9, the semiconductor substrate 1 is oxidized by the LOCOS method, a field oxide film 4 serving as an element isolation region is formed, and the nitride film 2 is removed. Next, through a lithography step, As + ions are implanted into desired portions to form an n + layer 5 having a concentration of 10 18 cm −3 and a depth of 0.3 μm.
Next, as shown in FIG. 10, a photoresist 6 is applied, an opening for reaching the n + layer 5 is formed at a desired place through a lithography process, and the semiconductor substrate 1 in the opening is etched to form a capacitor. A groove 7 is formed. Next, B + ions are slantedly and rotationally implanted into the side walls of the groove 7 to increase the capacity and reduce the soft error, thereby forming the p + layer 8. At this time, in the case of the drawing, the ion implantation is performed so that the boron concentration in the groove 7 becomes uniform by changing the oblique ion implantation angle θ in the range of θ = 0 ° (vertical) to 55 °. However, would be able to overlap portions 21 of the p + layer p + layer 8 of p + layer 3 and the groove opening side wall portions below the field oxide film 4 adjacent overlap in this way, the boron concentration is higher by this part . For this reason, the width of the depletion layer of the pn junction formed later may be locally reduced at the overlapping portion 21 of the p + layer. As a result, the electric field concentrates only in this portion, the leak current increases, and the dielectric strength voltage may decrease. In addition, crystal defects generated in the silicon substrate during ion implantation tend to remain, which may increase the leak current. That is, the charge storage time of the trench capacitance is significantly reduced, and it becomes difficult to perform the function as the DRAM. As described above, according to the conventional technique, only implantation at the upper portion of the groove side wall or implantation into the entire groove can be realized, and ion implantation cannot be performed at portions other than the upper portion of the groove opening side wall.
次に、第11図に示すようにAs+イオンを斜め回転イオ
ン注入してn+層９を形成し、フォトレジスト６を除去し
た後、容量部の絶縁膜となる高誘電体層10を形成し、そ
の上にポリシリコン等による電極11を形成する。次いで
絶縁膜12,ゲート絶縁膜13を形成した後、ワード線14を
パターニングする。n+拡散層15はフォトレジストをマス
クとしてAs+イオンを注入して形成する。次に層間膜16
を成長した後、拡散層15へのコンタクトをパターニング
してアルミ等によりディジット線17を形成し、半導体記
憶装置が形成される。Next, as shown in FIG. 11, an n + layer 9 is formed by oblique rotation ion implantation of As + ions, and the photoresist 6 is removed. Then, a high dielectric layer 10 serving as an insulating film of a capacitor portion is formed. Then, an electrode 11 made of polysilicon or the like is formed thereon. Next, after forming the insulating film 12 and the gate insulating film 13, the word lines 14 are patterned. The n + diffusion layer 15 is formed by implanting As + ions using a photoresist as a mask. Next, interlayer film 16
Is grown, and the contact to the diffusion layer 15 is patterned to form a digit line 17 of aluminum or the like, thereby forming a semiconductor memory device.
上述した従来の溝型容量部側壁へのB+イオンの斜め回
転注入では、第10図において、斜めイオン注入角θをθ
＝０゜（垂直）〜55゜と変化させ、溝７内のボロン濃度
が一様になる様にしてp+層８を形成していた。しかし、
この方法では、溝７に隣接するフィールド酸化膜４の下
のp+層３と溝開口部側壁上部のp+層８が重なるp+層の重
なり部21が生じる。すなわち、p+層３を形成する為にボ
ロンを２×1013cm-2,p+層８を形成する為に２×1013cm
-2注入した場合、p+層の重なり部21では４×1013cm-2注
入され、局所的にボロン濃度が高くなるので、この部分
でｐ−ｎ接合の空乏層巾が薄くなってしまう。その結
果、溝容量部に電圧が印加されると、４×1013cm-2注入
されたp+層の重なり部21の空乏層では、他の部分よりも
局所的に電界が集中し、絶縁耐圧が著しく低くなり、か
つリーク電流も多くなる。また、イオン注入の際にシリ
コン基板に発生する結晶欠陥が残留しやすくなり、リー
ク電流が多くなることも併発するので、この装置の信頼
性を悪くするという欠点がある。In the above-described conventional oblique rotation implantation of B + ions into the side wall of the groove-type capacitor, the oblique ion implantation angle θ is set to θ in FIG.
= 0 ° (vertical) to 55 °, and the p + layer 8 was formed such that the boron concentration in the groove 7 became uniform. But,
In this way, the overlap portion 21 of the p + layer p + layer 3 and the groove opening side wall upper portion of the p + layer 8 below the field oxide film 4 adjacent to the groove 7 overlap occurs. That, 2 × 10 13 boron to form a p + layer 3 cm -2, 2 × 10 13 to form a p + layer 8 cm
When −2 is implanted, 4 × 10 13 cm −2 is implanted in the overlapping portion 21 of the p + layer, and the boron concentration locally increases, so that the depletion layer width of the pn junction becomes thin in this portion. . As a result, when a voltage is applied to the trench capacitance portion, the electric field is more locally concentrated in the depletion layer of the overlapping portion 21 of the p + layer implanted with 4 × 10 13 cm −2 than in other portions, and the insulation is increased. The withstand voltage becomes extremely low and the leak current also increases. In addition, crystal defects generated in the silicon substrate during ion implantation are likely to remain, and the leakage current is increased. This also has the disadvantage that the reliability of this device is deteriorated.
本発明の目的は、上記欠点を除去し、溝側壁へのB+イ
オン注入の際、側壁上部のみイオン注入せず、局所的に
空乏層幅が薄くなるのに除去し、信頼性の高い溝型容量
部を備えた半導体装置の製造方法を提供することにあ
る。An object of the present invention is to eliminate the above-mentioned drawbacks, and to implant a B + ion into a trench sidewall without performing ion implantation only on the upper portion of the sidewall, but to remove the depletion layer locally even when the width of the depletion layer becomes thinner. An object of the present invention is to provide a method of manufacturing a semiconductor device having a mold capacitor.
本発明の半導体装置の製造方法は、半導体基板の主表
面に耐酸化性の第１の絶縁膜をマスクに所望の箇所へ半
導体基板と同一導電型の第１高濃度層を形成し、熱酸化
を行ないフィールド酸化膜を形成する工程と、第１の絶
縁体を除去する工程と、第２の絶縁膜を形成する工程
と、該第２の絶縁膜のフィールド酸化膜の近傍を開口す
る工程と、前記半導体基板１をエッチングして、溝を形
成する工程と第２の絶縁膜をひさし状のマスクにして溝
側壁上部以外の箇所に、斜め回転イオン注入し、所望の
領域のみ前記半導体基板と同一伝導型の第２高濃度層を
形成する工程と、前記第２の絶縁膜を除去する工程と、
溝の側壁全面に半導体基板と逆導電型の第３高濃度層を
形成する工程と、溝部に高誘電体膜及び導電電極を形成
する工程を含んで構成される。According to the method of manufacturing a semiconductor device of the present invention, a first high-concentration layer of the same conductivity type as that of a semiconductor substrate is formed at a desired position on a main surface of a semiconductor substrate using an oxidation-resistant first insulating film as a mask. Forming a field oxide film, removing the first insulator, forming a second insulating film, and opening an area of the second insulating film near the field oxide film. A step of forming a groove by etching the semiconductor substrate 1 and obliquely rotating ion implantation into portions other than the upper portion of the groove side wall using a second insulating film as an eaves-shaped mask, Forming a second high concentration layer of the same conductivity type, removing the second insulating film,
The method includes a step of forming a third high concentration layer of a conductivity type opposite to that of the semiconductor substrate on the entire side wall of the groove, and a step of forming a high dielectric film and a conductive electrode in the groove.
〔実施例〕 次に、本発明について図面を参照して説明する。第１
図〜第６図は本発明の一実施例の縦断面図である。この
実施例において、半導体基板１はｐ型シリコン基板とす
る。先ず第１図に示す如く、半導体基板１へ窒化膜２を
1500Å形成後、リソグラフィー工程を経て半導体基板１
へ達する開口を開け、素子分離領域にする所望の箇所
へ、素子間パンチスルー防止の為のB+イオンを２×1013
cm-2注入し、p+層３を形成する。次に第２図の様に半導
体基板１をLOCOS法により酸化し、素子分離領域となる
フィールド酸化膜４を7000Å形成し、窒化膜２を除去す
る。次にリソグラフィー工程を経て、所望の箇所にAs+
イオンを注入し、濃度1018cm-3,深さ0.3μｍのn+層５を
形成する。次に第３図に示すようにフォトレジスト６を
塗布し、リソグラフィ工程を経て所望の箇所にn+層５に
達する開口を開ける。この時の開口は、溝開口径の設計
値（1.4μｍ）より0.4μｍ小さくし、1.0μｍとした。
次に第４図に示すようにn+層５の開口部にフォトレジス
トをマスクとし反応性イオンエッチング（RIE法）によ
り、深さ５〜７μｍの溝を形成する。この時、エッチン
グに使う反応ガスは等方性のやや強いものから連続的に
異方性の強いものに変えた。こうすることによって、溝
開口部にレジストによるひさし作り、溝幅は1.4μｍと
した。次いで溝７の側壁へ、容量化及びソフトエラーレ
ート低減の為にB+イオンを斜め回転イオン注入し、濃度
1016cm-3,側壁から深さ0.6μｍのp+層８を形成した。こ
の時の注入角度θはθ＝０゜（垂直）〜15゜とした。こ
うすることによって基板表面から約0.8μｍはボロンが
注入されずp+層３とp+層８が重ならない。次いで第５図
に示すようにフォトレジスト６を除去し、再びリソグラ
フィー工程を経てAs+イオンを注入し、濃度1018cm-3側
壁から深さ0.2μｍのn+層９を形成する。次に容量部の
絶縁膜となる高誘電体層10を形成し、ポリシリコンの成
長のリンのドープを繰り返した後、エッチバックして、
溝７の中のポリシリコンで埋め、さらにパターニングし
てポリシリコン電極11を形成する。次に第６図に示すよ
うに絶縁膜12を約2000Å形成し、その後ゲート絶縁膜13
を300Å形成した後ポリシリコンによるワード線14をパ
ターニングする。n+拡散層15はフォトレジストをパター
ニングし、マスクとしてAs+イオンを注入し、濃度1019c
m-3、深さ0.3μｍの程度にする。次に層間膜16を500Å
成長した後、リソグラフィー工程を経て、拡散層15への
コンタクトをパターニングしてアルミ等によいディジッ
ト線17を形成すると、溝型容量部を有するMOS型DRAMの
セルが形成される。Next, the present invention will be described with reference to the drawings. First
FIG. 6 to FIG. 6 are longitudinal sectional views of one embodiment of the present invention. In this embodiment, the semiconductor substrate 1 is a p-type silicon substrate. First, as shown in FIG. 1, a nitride film 2 is
After forming 1500mm, the semiconductor substrate 1
B + ions for preventing punch-through between elements are formed in a desired portion of an element isolation region at 2 × 10 13
Implant cm −2 to form ap + layer 3. Next, as shown in FIG. 2, the semiconductor substrate 1 is oxidized by the LOCOS method, a field oxide film 4 serving as an element isolation region is formed at 7000 °, and the nitride film 2 is removed. Next, through a lithography process, As +
Ions are implanted to form an n + layer 5 having a concentration of 10 18 cm −3 and a depth of 0.3 μm. Next, as shown in FIG. 3, a photoresist 6 is applied, and an opening reaching the n + layer 5 is formed at a desired position through a lithography process. The opening at this time was set to 1.0 μm, which was 0.4 μm smaller than the design value (1.4 μm) of the groove opening diameter.
Next, as shown in FIG. 4, a groove having a depth of 5 to 7 μm is formed in the opening of the n + layer 5 by reactive ion etching (RIE) using a photoresist as a mask. At this time, the reaction gas used for etching was changed from a slightly strong isotropic one to a continuously strong anisotropic one. By doing so, the eaves were formed by the resist at the groove opening, and the groove width was 1.4 μm. Then, B + ions are obliquely rotated and implanted into the side walls of the groove 7 to increase the capacity and reduce the soft error rate.
A p + layer 8 having a thickness of 10 16 cm -3 and a depth of 0.6 μm from the side wall was formed. At this time, the injection angle θ was θ = 0 ° (vertical) to 15 °. By doing so, boron is not implanted about 0.8 μm from the substrate surface, so that the p + layer 3 and the p + layer 8 do not overlap. Next, as shown in FIG. 5, the photoresist 6 is removed, and as + ions are implanted again through a lithography process, thereby forming an n + layer 9 having a depth of 0.2 μm from the side wall having a concentration of 10 18 cm −3 . Next, a high dielectric layer 10 serving as an insulating film of a capacitor portion is formed, and after phosphorus doping of polysilicon growth is repeated, etch back is performed.
The trench 7 is filled with polysilicon and further patterned to form a polysilicon electrode 11. Next, as shown in FIG. 6, an insulating film 12 is formed for about 2000.
Is formed, and the word line 14 is patterned by polysilicon. The n + diffusion layer 15 is formed by patterning a photoresist, implanting As + ions as a mask, and having a concentration of 10 19 c.
m −3 and a depth of about 0.3 μm. Next, the interlayer film 16 is 500Å
After the growth, a lithography process is performed to pattern a contact to the diffusion layer 15 to form a digit line 17 that is good for aluminum or the like, thereby forming a MOS DRAM cell having a groove-type capacitor.
また、本実施例では溝７の開口及びB+イオン注入のマ
スクとしてフォトレジスト膜を用いたが、これに限られ
ることはなく、例えばシリコン酸化膜やシリコン窒化膜
等の絶縁膜を用いてもよい。さらに、第12図に示す様に
多層構造の膜を用いてもよい。第12図にシリコン酸化膜
22とフォトレジスト６による２層構造を用いた実施例を
示す。この場合は、シリコン酸化膜22から溝開口時のマ
スク及び半導体基板１の表面保護を兼ねる膜として用
い、この上にフォトレジスト６を塗布した構造とした。
これに、リソグラフィー工程を経て所望の箇所にシリコ
ン酸化膜に達する開口を開けた。次にシリコン酸化膜を
等方的にエッチングしレジストより後退させ開口部にレ
ジストによるひさしを形成し、その後上記実施例の如く
反応性イオンエッチングにより深さ５〜７μｍの溝７を
形成した。この場合、シリコン酸化膜22のサイドエッチ
量を調節することにより、基板表面からp+層８までの距
離を決定する事ができる。以下の工程は上記実施例と同
様に行った。In this embodiment, the photoresist film is used as the opening of the groove 7 and the mask for B + ion implantation. However, the present invention is not limited to this. For example, an insulating film such as a silicon oxide film or a silicon nitride film may be used. Good. Further, as shown in FIG. 12, a film having a multilayer structure may be used. Figure 12 shows the silicon oxide film
An embodiment using a two-layer structure of 22 and photoresist 6 will be described. In this case, the silicon oxide film 22 is used as a mask when the groove is opened and also as a film for protecting the surface of the semiconductor substrate 1, and a photoresist 6 is applied thereon.
In addition, an opening reaching the silicon oxide film was formed at a desired location through a lithography process. Next, the silicon oxide film was isotropically etched and receded from the resist to form an eave with the resist in the opening, and thereafter, a groove 7 having a depth of 5 to 7 μm was formed by reactive ion etching as in the above-described embodiment. In this case, the distance from the substrate surface to the p + layer 8 can be determined by adjusting the amount of side etching of the silicon oxide film 22. The following steps were performed in the same manner as in the above example.
以上のように、溝側壁上部へイオン注入せず局所的に
ボロン濃度が高くなる部分のない概略等しい濃度の溝側
壁p+層７を形成することにより、信頼性の高い溝型容量
部を形成した。As described above, by forming the groove side wall p + layer 7 having substantially the same concentration without a portion where the boron concentration is locally increased without ion implantation into the upper portion of the groove side wall, a highly reliable groove type capacitance portion is formed. did.
第７図では本発明の実施例２の縦断面図である。この
第２の実施例では、第３図におけるフォトレジスト６の
代りに窒化膜18をCVD方によい堆積し、リソグラフィー
工程を経て所望の箇所にn+層５に達する開口を1.4μｍ
開けた。その後、酸化膜をCVD法により堆積した後、エ
ッチバックを行ない開口部の窒化膜側壁へサイドウォー
ル19を形成する。その後、n+層５の開口部に窒化膜18と
サイドウォール19をマスクにウェットエッチングを行な
い溝幅が1.4μｍとなる所で止め、サイドウォールによ
るひさしを形成した。その後、異方性のやや強いガスを
用い、RIE法による深さ５〜７μｍの溝を形成した。そ
の後、実施例１と同様に溝７の側壁へB+イオンを斜め回
転イオン注入し、p+層８を形成した。その他の工程は、
第１の実施例の同一である。このように、第２の実施例
では、溝７のエッジにテーパーが設けられるので、溝開
口部のエッジの劣りを緩和し、高誘電体層の膜厚が局所
的に薄くなる部分を除去し、概略等しい膜厚にできるの
で、さらに信頼性の高い溝容量部を形成することができ
るという利点ももっている。FIG. 7 is a longitudinal sectional view of Embodiment 2 of the present invention. In the second embodiment, a nitride film 18 is deposited by CVD in place of the photoresist 6 shown in FIG. 3, and an opening reaching the n + layer 5 at a desired position through a lithography process is set to 1.4 μm.
Opened. Then, after depositing an oxide film by the CVD method, etch back is performed to form a sidewall 19 on the side wall of the nitride film in the opening. Then, wet etching was performed on the opening of the n + layer 5 using the nitride film 18 and the side wall 19 as a mask, and the opening was stopped at a point where the groove width became 1.4 μm, and an eave by the side wall was formed. Thereafter, a groove having a depth of 5 to 7 μm was formed by RIE using a slightly anisotropic gas. Thereafter, as in Example 1, B + ions were obliquely rotated and implanted into the side walls of the groove 7 to form a p + layer 8. Other steps are
This is the same as the first embodiment. As described above, in the second embodiment, the edge of the groove 7 is tapered, so that the edge of the groove opening is alleviated, and the portion where the thickness of the high dielectric layer is locally reduced is removed. Since the thickness can be made substantially equal, there is also an advantage that a more reliable groove capacitance portion can be formed.
以上説明したように本発明は、溝開口時に形成した絶
縁膜のひさし状マスクを利用して、溝内へのB+イオンの
斜め回転イオン注入の際、溝側壁上部へイオン注入せず
局所的にボロン濃度が高くなる部分を除去することによ
り、ｐ−ｎ接合の空乏層幅が薄くなるのを防ぎ、局所的
に電界が集中するのを緩和でき、かつイオン注入の際に
シリコン基板に発生する結晶欠陥が局所的に残留するの
を防げるので、信頼性の高い溝型容量部を備えた半導体
装置を得ることができる効果がある。As described above, the present invention makes use of the eaves-shaped mask of the insulating film formed at the time of opening the groove, and performs local ion implantation without obliquely ion-implanting B + ions into the upper portion of the groove side wall when the B + ions are injected into the groove. By removing the portion where the boron concentration becomes high, the depletion layer width of the pn junction can be prevented from becoming thin, the localization of the electric field can be reduced, and the silicon substrate is generated at the time of ion implantation. Therefore, it is possible to obtain a highly reliable semiconductor device having a groove-type capacitance portion.
第１図〜第６図及び第12図は本発明の実施例を説明する
ための縦断面図、第７図は本発明の第２の実施例を説明
するための縦断面図、第８図〜第11図は従来の半導体装
置の一例の縦断面図である。 １……半導体基板（Ｐ型）、２……窒化膜（Si3N4膜：
第１の絶縁膜）、３……p+層（第１高濃度層）、４……
フィールド酸化膜、５……n+層、６……フォトレジスト
（第２の絶縁膜）、７……溝、８……p+層（第２高濃度
層）、９……n+層（第３高濃度層）、10……誘電体層、
11……電極、12……絶縁膜、13……ゲート絶縁膜、14…
…ワード線、15……n+拡散層、16……層間膜、17……デ
ィジット線、18……窒化膜（Si3N4膜）、19……サイド
ウォール、20……B+イオン、21……p+層の重なり部、22
……シリコン酸化膜。1 to 6 and 12 are longitudinal sectional views for explaining an embodiment of the present invention, FIG. 7 is a longitudinal sectional view for explaining a second embodiment of the present invention, and FIG. 11 to 11 are longitudinal sectional views of an example of a conventional semiconductor device. 1 ...... semiconductor substrate (P-type), 2 ...... nitride film (Si 3 N 4 film:
1st insulating film), 3... P + layer (first high concentration layer), 4.
Field oxide film, 5 ... n + layer, 6 ... photoresist (second insulating film), 7 ... groove, 8 ... p + layer (second high concentration layer), 9 ... n + layer ( 3rd high concentration layer), 10 ... dielectric layer,
11 ... electrode, 12 ... insulating film, 13 ... gate insulating film, 14 ...
… Word line, 15… n + diffusion layer, 16… interlayer film, 17… digit line, 18… nitride film (Si 3 N 4 film), 19… sidewall, 20… B + ion, 21 ...... p + layer overlap, 22
.... Silicon oxide film.
Claims (7)
容量部を有するMOS型DRAMに関して、耐酸化性の第１の
絶縁膜をマスクに所望の箇所へ半導体基板と同一導電型
の第１高濃度層を形成し、熱酸化を行ないフィールド酸
化膜を形成する工程と、第１の絶縁膜を除去する工程
と、第２の絶縁膜を形成する工程と、該第２の絶縁膜の
フィールド酸化膜の近傍を開口する工程と、前記半導体
基板１をエッチングして、溝を形成する工程と第２の絶
縁膜をひさし状のマスクにして溝側壁上部以外の箇所
に、斜め回転イオン注入し、所望の領域のみ前記半導体
基板と同一伝導型の第２高濃度層を形成する工程と、前
記第２の絶縁膜を除去する工程と、少くとも溝の側壁全
面に半導体基板と逆導電型の第３高濃度層を形成する工
程と、溝部に高誘電体膜及び導電電極を形成する工程を
含むことを特徴とする半導体装置の製造方法。An MOS type DRAM having a groove-type cell capacitance portion formed on a main surface of a semiconductor substrate. The first type of oxidation-resistant insulating film is used as a mask to a desired portion of the same conductivity type as the semiconductor substrate. (1) forming a high-concentration layer, performing thermal oxidation to form a field oxide film, removing the first insulating film, forming a second insulating film, and forming a second insulating film. A step of opening the vicinity of the field oxide film, a step of forming a groove by etching the semiconductor substrate 1, and a step of obliquely rotating ion implantation into portions other than the upper portion of the groove side wall using the second insulating film as an eaves-shaped mask. Forming a second high-concentration layer of the same conductivity type as the semiconductor substrate only in a desired region; removing the second insulating film; Forming a third high concentration layer, and forming a high dielectric film and And a step of forming a conductive electrode.
膜を用いることを特徴とする特許請求の範囲第１項記載
の半導体装置の製造方法。2. The method according to claim 1, wherein a photoresist film is used as said second insulating film.
を用いることを特徴とする特許請求の範囲第１項記載の
半導体装置の製造方法。3. The method for manufacturing a semiconductor device according to claim 1, wherein a silicon oxide film is used as said second insulating film.
を用いることを特徴とする特許請求の範囲第１項記載の
半導体装置の製造方法。4. The method for manufacturing a semiconductor device according to claim 1, wherein a silicon nitride film is used as said second insulating film.
とフォトレジスト膜を組合せた多層構造を用いることを
特徴とする特許請求の範囲第１項記載の半導体装置の製
造方法。5. The method according to claim 1, wherein the second insulating film has a multilayer structure in which a silicon oxide film and a photoresist film are combined.
フォトレジスト膜を組合せた多層構造の膜を用いること
を特徴とする特許請求の範囲第１項記載の半導体装置の
製造方法。6. The method according to claim 1, wherein a film having a multilayer structure in which a silicon nitride film and a photoresist film are combined is used as said second insulating film.
とシリコン窒化膜とフォトレジスト膜を組合せた多層構
造の膜を用いることを特徴とする特許請求の範囲第１項
記載の半導体装置の製造方法。7. The semiconductor device according to claim 1, wherein a film having a multilayer structure in which a silicon oxide film, a silicon nitride film, and a photoresist film are combined is used as said second insulating film. Production method.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2307688A JP2581302B2 (en) | 1989-12-29 | 1990-11-14 | Method for manufacturing semiconductor device |
| US07/791,345 US5330926A (en) | 1990-11-14 | 1991-11-14 | Method of fabricating semiconductor device having a trenched cell capacitor |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1-342836 | 1989-12-29 | ||
| JP34283689 | 1989-12-29 | ||
| JP2307688A JP2581302B2 (en) | 1989-12-29 | 1990-11-14 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03224260A JPH03224260A (en) | 1991-10-03 |
| JP2581302B2 true JP2581302B2 (en) | 1997-02-12 |
Family
ID=26565228
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2307688A Expired - Lifetime JP2581302B2 (en) | 1989-12-29 | 1990-11-14 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2581302B2 (en) |
-
1990
- 1990-11-14 JP JP2307688A patent/JP2581302B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03224260A (en) | 1991-10-03 |
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