JP3224916B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a memory cell having a bit line contact and a strap contact.

[0002]

2. Description of the Related Art As DRAM (dynamic random access memory) has been highly integrated, it has become essential to make the element structure three-dimensional. DR after 4Mbit DRAM
The structure of a memory cell (DRAM cell) used in AM is roughly classified into a method using a so-called stack capacitor in which a charge storage node is formed above a silicon substrate, and a method in which a groove is formed in a silicon substrate to store charge therein. A method of forming a node is divided into a method using a so-called trench capacitor.

In a DRAM cell using a trench capacitor, it becomes difficult to maintain a dielectric strength between adjacent trenches as the element becomes finer. As a countermeasure,
A trench capacitor cell having a structure in which an inner wall of a trench is covered with an insulating film and a charge storage node is formed of polysilicon therein is becoming mainstream.

In this trench capacitor cell, a capacitor charge storage node and a charge transfer gate MO are provided.
There is a structure in which a wiring is formed so as to be in contact with the source region of the S transistor, and this contact portion is called a strap contact. Further, a portion where the bit line contacts the drain region of the charge transfer gate MOS transistor is called a bit line contact.

Hereinafter, a conventional method for forming a trench capacitor will be described in detail with reference to FIGS. 5 (a) to 5 (c), 6 (a) and 6 (b). First, FIG.
As shown in (a), the p-type in which the n-type diffusion layer 50 is embedded is shown.
A groove reaching the above-mentioned n-type diffusion layer 50 is dug in the silicon substrate 51, an insulating film (for example, a silicon oxide film) 53 is formed on the inner peripheral surface of the groove, and the capacitor electrode (up to an intermediate height in the groove) is formed. polysilicon film doped with n-type impurity) 5
4 is buried, a capacitor insulating film 55 is formed thereon, and a capacitor charge storage node (n
(A polysilicon film doped with a type impurity) 56 is buried.

Thereafter, a gate insulating film 57 is formed on the substrate, and a polysilicon film 58 and a silicon nitride film (SiN film) 5 for an etching mask are formed on the gate insulating film 57.
9 are sequentially deposited and word lines 58 are formed by patterning.

Next, a SiN film 60 is deposited on the entire upper surface of the substrate 51 by a low pressure CVD (chemical vapor deposition) method. Next, as shown in FIG. 5B, a photoresist 61 is applied to the entire surface, and the lithography technique is used to coat the SiN film 60 on the region where the strap contact is to be formed (62 in FIG. 5A) and the underlying layer. Anisotropic etching (for example, reactive ion etching; RI)
E), and a contact hole for a strap contact is opened. In this case, the SiN film 60 on the side wall of the word line 58 adjacent to the strap contact formation planned region 62 is left.

Next, after the photoresist 61 is removed, a phosphorus-doped polysilicon film 63 is deposited on the entire surface as shown in FIG.
Patterning is performed so that a part of the semiconductor layer remains in the strap contact region. Then, by solid-phase diffusion from the polysilicon film 63, an n-channel MO for a charge transfer gate is formed.
The source region 63a of the S transistor is formed.

Next, as shown in FIG. 6A, the SiN in the region where the bit line contact is to be formed (64 in FIG. 5A) is formed.
The film 60 and the underlying gate insulating film 57 are removed by RIE. In this case, the SiN film 60 on the side wall of the word line 58 adjacent to the bit line contact formation region 64 is left.

Next, S is applied to the entire surface of the substrate by a low pressure CVD method.
BPSG to deposit iN film 65 and then to deposit
(Phosphorus-boron-silicate glass) A polysilicon film 66 is deposited as a stopper when the film 67 is removed.

Subsequently, a BPSG film 67 is deposited on the entire surface, a photoresist 68 is applied on the entire surface, and the lithography technique is used to form a BPSG film 67 on the bit line contact formation region.
The PSG film 67 is removed by RIE.

Next, the polysilicon film 66 is removed by isotropic etching only on a region where a bit line contact is to be formed, and the BPSG film is formed at 900 ° C. in a wet atmosphere.
The reflow of the film 67 and the oxidation of the polysilicon film 66 remaining except on the region where the bit line contact is to be formed are performed. Then, the Si on the region where the bit line contact is to be formed is formed.
The N film 65 is removed by RIE, and a contact hole for bit line contact is opened.

Next, after removing the photoresist 68, as shown in FIG. 6B, a polysilicon film 69 is deposited on the entire surface by a low pressure CVD method, and phosphorus ions are deposited on the polysilicon film 69 by an ion implantation method. Inject. Then, a drain region 69a of an n-channel MOS transistor for a charge transfer gate is formed by solid-phase diffusion from the polysilicon film 69. Further, a tungsten silicide (WSi) film 70 is deposited on the entire surface by DC magnetron sputtering. Thereafter, the WSi film 70 and the polysilicon film 69 are patterned by RIE, thereby forming a bit line in contact with the drain region 69a of the charge transfer gate MOS transistor.

However, the conventional method of forming a strap contact / bit line contact as described above has the following problems. (1) Since the strap contact and the bit line contact are formed separately (sequentially), the process becomes longer,
It is not preferable in terms of productivity.

(2) Since a lithography step for opening a contact hole for a strap contact and a contact hole for a bit line contact is performed separately,
A short circuit of the strap contact / bit line contact may occur due to misalignment of the pattern mask or the like.

(3) When an insulating film is formed on the entire surface of the substrate after forming the strap contact and the bit line contact, a concave portion is formed corresponding to the portion on the strap contact and the bit line contact. The lithography process will be affected. On the other hand, Japanese Patent Application Laid-Open No. 2-128466 discloses a technique of simultaneously forming a strap contact and a bit line contact in a "DRAM cell having an SDHT structure and a method of manufacturing the same". A recess is generated corresponding to the portion on the contact.

[0017]

As described above, conventionally, when a DRAM cell having a strap contact / bit line contact is formed, an insulating film is formed on the entire surface of the substrate after the formation of the strap contact / bit line contact. In such a case, there is a problem that a concave portion is formed corresponding to the portion on the strap contact and the portion on the bit line contact, which hinders a subsequent lithography process.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and simplifies the process when forming a DRAM cell having a strap contact / bit line contact, and short-circuits the strap contact / bit line contact. To provide a method of manufacturing a semiconductor device, which can prevent the occurrence of a lithography process, and can secure flatness when an insulating film is formed on the entire surface of a substrate after forming a strap contact / bit line contact. Aim.

[0019]

According to the method of manufacturing a semiconductor device of the present invention, when forming a DRAM cell having a strap contact / bit line contact, a first insulating film is deposited on the entire surface of a substrate, A step of removing the first insulating film on the region where the contact is to be formed and the region where the bit line contact is to be formed, and after chemically depositing the first conductive layer over the entire surface of the substrate up to at least the height of the word line. Removing the first conductive layer using a mechanical polishing method so that the first conductive layer is buried to the height of the word line; and depositing a second insulating film over the entire surface of the substrate to form a bit line contact formation region Forming a connection hole for bit line contact by removing at least a part of the second insulating film on the first conductive layer; and forming a bit line. And wherein the Rukoto.

[0020]

According to the present invention, after a word line is formed, a first conductive layer is deposited on the entire surface of a substrate, and the first conductive layer is left buried at least to the height of the word line by using a polishing method. Then, a second insulating film is deposited on the entire surface of the substrate, reflow is performed, and the second insulating film on the region where the bit line contact is to be formed is removed to form a connection hole for the bit line contact. , And bit lines.

Therefore, the strap contact and the bit line contact can be formed at the same time, and the process is largely omitted.
Improvements in construction period / productivity can be achieved. In addition, since the lithography process for simultaneously opening the contact hole for the strap contact and the contact hole for the bit line contact is performed, short-circuiting of the strap contact / bit line contact due to misalignment of the pattern mask or the like may occur. There is no risk of getting up.

Further, since the first conductive layer is buried at least up to the height of the word line, it is possible to flatten a plane including the strap contact region and the bit line contact region. Thereby, in the step of depositing the second insulating film later to form the connection hole for the bit line contact, the underlying structure is flat, so that the lithography technique is facilitated.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIGS. 1A to 1C, 2A and 2B show a cross-sectional structure of a wafer in a process of forming a DRAM cell according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a p-type silicon substrate 11 in which an n-type diffusion layer 10 is embedded is
A groove reaching the n-type diffusion layer 10 is dug, an insulating film (for example, a silicon oxide film) 13 is formed on the inner peripheral surface of the groove, and a capacitor electrode (polysilicon doped with an n-type impurity) is formed to an intermediate height in the groove. A film 14 is buried, a capacitor insulating film 15 is formed thereon, and a capacitor charge storage node (a polysilicon film doped with an n-type impurity) 16 is buried above the trench.

Thereafter, a gate insulating film 17 is formed on the substrate, and a polysilicon film 18 and a silicon nitride film (SiN film) 1 for an etching mask are formed on the gate insulating film 17.
9 are sequentially deposited and word lines 18 are formed by patterning.

Next, a SiN film 20 is deposited on the entire upper surface of the substrate 11 by a low pressure CVD (chemical vapor deposition) method. Next, as shown in FIG. 1B, a photoresist 21 is applied to the entire surface, and the lithography technique is used to form the SiN film 20 on the region where the strap contact is to be formed (22 in FIG. 1A) and the underlying layer. Region where gate insulating film 17 and bit line contact are to be formed (23 in FIG. 1A)
The upper SiN film 20 and the underlying gate insulating film 17 are removed by anisotropic etching (for example, RIE) to open a contact hole for a strap contact and a contact hole for a bit line contact. In this case, the SiN film 20 on the side wall of the word line adjacent to the region where the strap contact is to be formed and the SiN film 20 on the side wall of the word line adjacent to the region where the bit line contact is to be formed
Leave.

In this step, the strap contact /
Since the openings for the bit line contacts are made at the same time, the lithography rules can be greatly relaxed as compared with the design rules.

Next, after the photoresist 21 is removed, as shown in FIG. 1C, a phosphorus-doped polysilicon film is deposited on the entire surface by a low pressure CVD method. In this case, at least the height of the word line 18 (at least the etching mask SiN film 1 from the substrate surface).
9 or more), the polysilicon film (24a, 2
4b) is deposited.

Then, the polysilicon films (24a, 2a,
4b), the source region 25a and the drain region 25b of the n-channel MOS transistor for the charge transfer gate are formed by solid phase diffusion.

Next, the polysilicon film is removed using a chemical or mechanical polishing method so as to leave the polysilicon film buried at least up to the height of the word line 18. As a result, a conductive layer 24a for electrically connecting the capacitor charge storage node 16 and the source diffusion layer 24a of the charge transfer gate transistor and a conductive layer 24b for bit line contact are formed.

Next, the polysilicon film other than on the strap contact region / bit line contact region is removed by using lithography and RIE. next,
As shown in FIG. 2A, a BPSG film 26 is deposited on the entire surface of the substrate by a low pressure CVD method, and the BPSG film 26 is reflowed at 900 ° C. in an N ₂ atmosphere.

Subsequently, a photoresist 27 is applied to the entire surface, and the BPSG film 26 on the bit line contact formation expected area is removed by RIE using lithography technology.
A connection hole for a bit line contact is formed.

Next, as shown in FIG.
A polysilicon film 28 is deposited on the entire surface by a method D, and phosphorus ions are implanted into the polysilicon film 28 by an ion implantation method. Further, after a WSi film 29 is deposited on the entire surface by DC magnetron sputtering, the WSi film 2 is formed.
9 and the polysilicon film 28 are patterned by RIE, thereby forming the conductive layer 24 for bit line contact.
Bit lines (28, 29) in contact with b are formed.

According to the formation method of the first embodiment, after forming the word line 18, the SiN film 20 is deposited on the entire surface of the substrate, and the strap contact formation region 22 and the bit line contact formation region 23 are formed. The upper SiN film 20 is simultaneously removed, and a polysilicon film is further deposited on the entire surface of the substrate up to the height of the word line. Thereafter, the polysilicon film is removed by a chemical or mechanical polishing method so that the polysilicon film is buried at least up to the height of the word line, thereby removing the conductive film 24a for the strap contact and the conductive film for the bit line contact. The layer 24b is formed. Further, a BPSG film 26 is deposited on the entire surface of the substrate, reflow is performed, and the BPSG film 26 on the region where the bit line contact is to be formed is removed to form a connection hole for a bit line contact. ).

Accordingly, the strap contact 24a and the bit line contact 24b can be formed at the same time, so that the steps can be largely omitted, and the work period / productivity can be improved.

Since the lithography process for opening the contact hole for the strap contact and the contact hole for the bit line contact is performed simultaneously,
The possibility of short-circuiting of the strap contact / bit line contact due to misalignment of the pattern mask or the like is eliminated.

In addition, the polysilicon films (24a, 24a)
Since b) is buried at least to the height of the word line 18, it is possible to flatten a plane including the strap contact region and the bit line contact region. Thereby, in the step of depositing the BPSG film 26 later to form the connection hole for the bit line contact, the underlying structure is flat, so that the lithography technique is facilitated.

FIGS. 3A, 3B and 4A,
(B) shows the sectional structure of the wafer in the main step of the method for forming the DRAM cell according to the second embodiment of the present invention. First, in the step shown in FIG. 3A, as in the step shown in FIG. 1A of the first embodiment, a silicon oxide film 13, a capacitor electrode 14, and a capacitor insulating film 15 are formed on a silicon substrate 11. , Capacitor charge storage node 16, gate insulating film 17, polysilicon film (word line) 18, S
An iN film 19 and a SiN film 20 are formed.

Thereafter, a BPSG film 30 is deposited on the entire surface of the substrate by a low pressure CVD method, and the BPSG film 30 is reflowed in an N ₂ atmosphere at 900 ° C. Next, FIG.
As shown in (b), a photoresist 31 is applied to the entire surface, and the BPSG film 30 and the SiN film 20 on the strap contact formation region 22 are applied using lithography technology.
And the BPSG film 30 and the SiN film on the gate insulating film 17 thereunder and the bit line contact formation region 23
The film 20 and the underlying gate insulating film 17 are removed by anisotropic etching (for example, RIE) to open a contact hole for a strap contact and a contact hole for a bit line contact. In this case, the word line 18 adjacent to the region where the strap contact is to be formed is formed.
And the SiN film 20 on the side wall of the word line 18 adjacent to the region where the bit line contact is to be formed is left.

Next, the photoresist 31 is removed,
As shown in FIG. 4A, a phosphorus-doped polysilicon film (32a, 32b) is deposited on the entire surface by low-pressure CVD. In this case, the polysilicon film (32a, 32
b) is deposited above the height of the BPSG film 30.

Then, the polysilicon films (32a, 3a,
The source region 25a and the drain region 25b of the n-channel MOS transistor for the charge transfer gate are formed by the solid phase diffusion from 2b).

Next, the polysilicon films (32a, 32b) are formed by a chemical or mechanical polishing method.
Is removed so as to remain embedded in the BPSG film 30. As a result, a conductive layer 32a for electrically connecting the capacitor charge storage node 16 to the source diffusion layer 25a of the charge transfer gate transistor and a conductive layer 32b for bit line contact are formed.

Next, as shown in FIG.
An oxide film 33 is deposited on the entire surface by the method D, and the oxide film 33 is removed only on the bit line contact conductive layer 32b by using a lithography technique and RIE.

Thereafter, a polysilicon film 28 is deposited on the entire surface, and phosphorus ions are implanted into the polysilicon film 28 by an ion implantation method. Further, a WSi film 29 is deposited on the entire surface by DC magnetron sputtering. Thereafter, the WSi film 29 and the polysilicon film 28 are
By patterning with E, a bit line is formed.

According to the formation method of the second embodiment, after forming the word line, the SiN film 20 and the B
A PSG film 30 is sequentially deposited, and the BPSG film 30, the SiN film 20 and the gate insulating film 17 thereunder on the strap contact formation region 22 and the BPSG film 30, the SiN film 20 and the bit line contact formation region 23 on the bit line contact formation region 23 are formed. The lower gate insulating film 17 is removed by RIE to form a hole. Then, a polysilicon film 32 is buried in the opening, and an oxide film 33 is further deposited on the entire surface. The oxide film 3 is formed only on the bit line contact conductive layer 32b.
After removing 3, a bit line is formed.

Therefore, as in the first embodiment, by forming the conductive layer for strap contact 32a and the conductive layer for bit line contact 32b at the same time, the steps can be largely omitted.

Further, since the BPSG film 30, the SiN film 20, and the gate insulating film 17 thereunder are removed by RIE to form holes, the lithography process can be further reduced.

In addition, the polysilicon films (32a, 32
Since b) is buried to the height of the BPSG film 30, the underlying structure is flat in the later step of depositing the oxide film 33 and forming the connection hole for the bit line contact, thereby facilitating the lithography technique.

[0049]

As described above, according to the present invention, when forming a trench capacitor type DRAM cell, a strap contact and a bit line contact can be formed at the same time, and the process can be largely omitted.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a wafer in a process of forming a DRAM cell according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing the wafer in a step that follows the step of FIG. 1;

FIG. 3 is a sectional view showing a wafer in a process of forming a DRAM cell according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing the wafer in a step that follows the step of FIG. 3;

FIG. 5 is a sectional view showing a wafer in a conventional trench capacitor forming process.

FIG. 6 is a sectional view showing the wafer in a step that follows the step of FIG. 5;

[Explanation of symbols]

11 silicon substrate, 13 silicon oxide film, 14 capacitor electrode, 15 capacitor insulating film, 16 capacitor charge storage node, 17 gate insulating film, 18 polysilicon film (word line), 19 SiN film, 20 ... Si
N film, 21 photoresist, 22 planned strap contact formation region, 23 planned bit line contact formation region, 24 polysilicon film, 24a, 32a conductive layer for strap contact, 24b, 32b bit line contact Conductive layer, 25a ... source region, 25b ...
Drain region, 26 ... BPSG film, 27 ... Photoresist, 28 ... Polysilicon film, 29 ... WSi film, 30 ... B
PSG film, 31: photoresist, 33: oxide film.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242

Claims (1)

(57) [Claims] A step of digging a groove in a part of the surface of the semiconductor substrate and forming an insulating film on an inner peripheral surface of the groove; Forming a capacitor insulating film thereon, further forming a second conductive material serving as a capacitor charge storage node above the trench, and forming a gate insulating film on the semiconductor substrate. Forming a word line on the gate insulating film; forming an impurity diffusion layer on a part of the surface of the semiconductor substrate;
Forming a MOS transistor for a charge transfer gate using a part of the word line as a gate electrode; depositing a first insulating film on the entire surface of the semiconductor substrate; Depositing a film; and connecting a source diffusion layer of the charge transfer gate MOS transistor to a charge storage node in the trench.
A bit line contact formation region for connecting the second insulation film, the first insulation film on the contact formation region and the gate insulation film thereunder and a drain diffusion layer of the charge transfer gate MOS transistor to a bit line. Removing the second insulating film, the first insulating film, and the gate insulating film therebelow by anisotropic etching; and removing the first insulating film over the entire surface of the semiconductor substrate up to at least the height of the second insulating film. Depositing the first conductive layer, and removing the first conductive layer using a planarization technique so as to leave the first conductive layer buried at least up to the height of the second insulating film. Forming a conductive layer for electrically connecting the source diffusion layer of the transistor for the charge transfer gate and a conductive layer for the bit line contact Depositing a third insulating film on the entire surface of the semiconductor substrate, removing at least a portion of the third insulating film on the first conductive layer on the region where the bit line contact is to be formed, Forming a connection hole; depositing a second conductive layer over the entire surface of the semiconductor substrate; and patterning the second conductive layer to form a bit line. A method for manufacturing a semiconductor device.