JP3114803B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an increased capacitance of a capacitor and a method of manufacturing the same.

[0003]

[Prior art]

Conventionally, in a method of manufacturing a semiconductor device such as a semiconductor memory device, in order to increase the capacity of a MOS capacitor, a method of forming irregularities on the surface of a storage electrode of the MOS capacitor to increase the surface area of the electrode is used. Is used. For example, Japanese Patent Application Laid-Open No. Hei 4-96366 discloses a technique for increasing the capacitance of a capacitor by substantially increasing the surface area of an electrode without increasing the area of a MOS capacitor on a plane.

FIGS. 5 and 6 show a conventional semiconductor device having a stacked capacitor type cell disclosed in Japanese Patent Application Laid-Open No. 4-96366 and a method of manufacturing the same. As shown in FIG. 5A, the thickness of the polysilicon is about 300 nm.
As shown in FIG. 5B, a thickness of about 1.
A 2 μm photoresist 28 is patterned. Using HBr as a reaction gas, a flow rate of 60 sccm, 150 mTo
Anisotropic RIE is performed at a pressure of rr and an RF power of 400 W. As a result, as shown in FIG. 6A, the surface of the storage electrode 26 is etched to a depth of about 150 nm to form irregularities. .

Next, as shown in FIG. 6B, a capacitive insulating film 29 is formed, and a counter electrode 30 of the stacked capacitor is formed.
As a (cell plate), a second polysilicon film having a thickness of about 150 nm is patterned.

[0007] By using the above method, the stacked capacitor can realize a larger area, that is, a larger capacity, which is substantially twice or more, without increasing the area in plan view.

In this conventional example, the case where the storage electrode 16 having a thickness of about 300 nm is subjected to the etching of about 150 nm unevenness, that is, 50% of the film thickness, is practically 1% to 90% of the film thickness. Etching can be performed in the range. That is, the capacitance of the cell can be controlled by changing the etching depth of the polysilicon film serving as the storage electrode 26.

[0009]

[Problems to be solved by the invention]

However, this conventional technique has the following problems. For recent semiconductor devices, the effect obtained by the above-described conventional technology is small. In recent years, with the increase in density and integration of semiconductor devices, M
It has become difficult to design the area of the OS capacitor as viewed in a plane as shown in FIG. Since the planar area has been reduced, there is a limit in forming a concavo-convex pattern by photolithography. Therefore,
It has become difficult to increase the surface area only by forming irregularities on the surface of the storage electrode.

When the thickness of the storage electrode 26 is increased, there is an effect of increasing the surface area according to the prior art, but the flatness of the upper interlayer silicon oxide film is deteriorated, and it becomes difficult to form the upper wiring. It is not practical because it creates new problems.

In the second conventional example shown in FIG.
There are the following problems. First, the poor coverage of the first storage electrode makes it difficult to subsequently form a second storage electrode serving as a capacitive insulating film and a counter electrode. As can be seen from FIG. 7, the coverage of the formed capacitive insulating film deteriorates because the first storage electrode serving as a base when the capacitive insulating film is formed has an inverse taper,
It is fully conceivable that the storage electrode will no longer be used. Further, the reproducibility of the production method is poor. The growth of polysilicon as the first storage electrode is
Although it is performed separately, it is sufficiently conceivable that in the second deposition, there is no gap for embedding the capacitive insulating film and the second storage electrode depending on the diameter of the connection hole. .

The present invention has been made to solve the above problems. Therefore, an object of the present invention is to form a void in a polysilicon film as a storage electrode and use the void to increase a substantial surface area of a MOS capacitor and increase the capacity of the capacitor. An object of the present invention is to provide an apparatus and a method of manufacturing the same.

[0014]

[Means for Solving the Problems]

In the semiconductor device of the present invention, a hole reaching the source region or the drain region of the MOS transistor is formed, and an insulating film formed so as to cover a gate electrode of the MOS transistor, and a void is left in the hole. A conductive storage electrode formed along the inner surface of the hole and formed around the hole in the insulating film and connected to a source region or a drain region of the MOS transistor, while leaving a void in the hole; A capacitive insulating film formed to cover the storage electrode, and a conductive counter electrode formed to cover the capacitive insulating film while filling voids in the holes.

The storage electrode is divided into a first storage electrode portion formed along the inner surface of the hole and a second storage electrode portion formed around the hole in the insulating film. 2
Is thicker than the thickness of the first storage electrode section.

Further, a method of manufacturing a semiconductor device according to the present invention
MOS having source region, drain region and gate electrode
Forming an insulating film so as to cover a gate electrode of the transistor; forming a hole in the insulating film so as to reach the source region or the drain region of the MOS transistor; and leaving a void in the hole. Forming a storage electrode along the inner surface of the hole and around the hole in the insulating film; and forming a capacitive insulating film to cover the storage electrode while leaving a void in the hole. And forming an opposing electrode so as to cover the capacitive insulating film while filling voids in the holes.

The step of forming the storage electrode includes the step of forming a first storage electrode portion along an inner surface of the hole, and the step of forming a second storage electrode portion around the hole in the insulating film. It is preferable that the thickness of the second storage electrode portion is larger than the thickness of the first storage electrode portion.

At least one of the step of forming the first storage electrode section and the step of forming the second storage electrode section includes a step of forming a polysilicon film and a step of forming an impurity in the polysilicon film. Doping may be provided, or at least one of the step of forming the first storage electrode portion and the step of forming the second storage electrode portion may include a step of forming a polysilicon film doped with an impurity. The method may include forming.

In the step of forming the storage electrode, the amount of the growth gas supplied is controlled and the film formation rate is controlled so that the hole is not completely filled. Forming a first storage electrode portion along an inner surface; and controlling a deposition rate so as not to completely fill the void by limiting a supply amount of the growth gas. Forming a second storage electrode portion around the hole in the insulating film by a growth method.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, a silicon oxide film 2 for element isolation is formed on a silicon semiconductor substrate 1. A gate oxide film 3 and a gate electrode 4 are formed on a semiconductor substrate 1 and a silicon oxide film 2 for element isolation.
Is formed. A drain region and a source region 11 are provided on both sides of the gate structure on the semiconductor substrate 1.
Are formed. The two gate structures are covered with an interlayer insulating film 5 of a silicon oxide film.

A semiconductor substrate 1 is provided between two gate structures.
Is formed. The inner surface of the connection hole is the first
Is covered with the storage electrode 6. A second storage electrode 7 connected to the first storage electrode 6 is formed around the connection hole of the silicon oxide film 5. On the silicon oxide film 5,
The portion where the second storage electrode 7 is not formed, the periphery of the second storage electrode 7, and the surface of the first storage electrode 6 are covered with the capacitive insulating film 9. An unfilled portion remains in the connection hole. A counter electrode (counter electrode) 10 is provided so as to cover the capacitive insulating film 9 and fill an unfilled portion in the connection hole.

Next, the method for fabricating the semiconductor device according to the first embodiment of the present invention will be described in detail. 2 and 3 show cross sections of the semiconductor device according to the first embodiment of the present invention in the order of steps.

In FIG. 2A, an element isolation silicon oxide film 2 is formed on a semiconductor substrate 1. Thereafter, a silicon oxide film and a polysilicon film are formed, and a gate structure including the gate oxide film 3 and the gate electrode 4 is formed by using photolithography technology. After that, impurity ions are implanted in a self-aligned manner with the gate structure to form a source region,
A drain region 11 is formed, and the gate electrode 4 also becomes conductive. Thereafter, a silicon oxide film 5 is formed on the entire surface of semiconductor substrate 1.

Next, a connection hole reaching the source / drain region is formed in the silicon oxide film 5 by etching.
After forming the connection holes, a first storage electrode 6 of polysilicon is formed by a chemical vapor deposition (CVD) method. At this time, a void is formed in the connection hole by restricting the supply of the growth gas. As described above, in the present invention, voids are intentionally formed during the formation of the polysilicon film by controlling the supply of the growth gas.

The conditions for forming the polysilicon film by the supply rate control are, specifically, a film forming temperature of 650 ° C. and 360 scc.
At a flow rate of m, SiH4 is supplied at a pressure of 80 mTorr. Of course, the film forming conditions are not limited to these.

Here, as the width of the void, it is necessary to ensure a width in which the capacitive insulating film 9 and the counter electrode 10 to be formed later can be formed.

Conventionally, voids should not be present because they cause deterioration of the reliability of the semiconductor device. However, with the recent increase in density and integration of semiconductor elements, it has become more difficult to fill the connection holes with a polysilicon film so that voids are not generated as the connection holes become finer. At present, a film is required to be formed by a reaction rate control in order to fill a connection hole so as not to generate a void. As a result, a film forming speed is reduced, and productivity is sacrificed.

In the present invention, voids are positively utilized,
Not only can the polysilicon film be formed as the storage electrode without sacrificing productivity, but the surface area of the polysilicon film that becomes the storage electrode can be increased, so that the substantial surface area of the MOS capacitor can be increased and the size of the capacitor can be increased. The capacity is being increased.

After that, the first storage electrode 6 is etched back by isotropic etching and is looked up from above the silicon oxide film 5. As the amount of etch back at this time,
It is preferable to perform over-etching of about 10% after the silicon oxide film 5 comes to the surface, but it is not particularly limited. Further, SF ₆ is specifically used as an etching gas for isotropic etching.

While being etched back, phosphorus ions are doped as impurity ions by ion implantation or diffusion.

Next, as shown in FIG. 2B, a polysilicon film for the second storage electrode 7 is formed on the first storage electrode 6.
Similarly, it is formed by supply control. Specifically, the conditions for forming the second storage electrode 7 are such that SiH ₄ is supplied at a deposition temperature of 650 ° C. at a flow rate of 360 sccm and a pressure of 80 mTorr. Of course, the film forming conditions are not limited to these.

At this time, if the voids left when the first storage electrode 6 is formed are newly buried by the second storage electrode 7, the effect of the present invention is lost. Therefore, it is necessary to form the second storage electrode 7 so that the entire void is not filled with the polysilicon of the second storage electrode 7.

Thereafter, a desired pattern of the photoresist film 8 is formed on the second storage electrode 7 by photolithography. Subsequently, FIG.
As shown in (2), the etching is performed until the second storage electrode 7 is no longer above the void of the first storage electrode 6. afterwards,
Ashing is performed to remove the photoresist film 8.

After the film formation of the second storage electrode 7 by the supply control, phosphorus ions are doped as impurities into the second storage electrode 7 by an ion implantation method or a diffusion method.

Next, as shown in FIG.
Is formed on the entire surface of the semiconductor substrate 1. At this time, the capacitive insulating film 9 is formed not only on the upper surface of the second storage electrode 7 but also on the exposed side surfaces. Further, a capacitive insulating film 9 is formed to cover the surface of the first storage electrode 6 in the connection hole. At this time, small voids still remain in the connection holes.

Next, a counter electrode 10 of a stacked capacitor made of polysilicon is formed. Counter electrode 10
Are formed so as to completely fill voids remaining when the capacitive insulating film 9 is formed. Thus, the semiconductor device is completed as shown in FIG.

Next, the method for fabricating the semiconductor device according to the second embodiment of the present invention will be described. 4A and 4B show a cross section of a semiconductor device according to a second embodiment of the present invention in the order of steps.

First, as shown in FIG. 4A, an element isolation silicon oxide film 2 is formed on a semiconductor substrate 1 as in the first embodiment. Thereafter, a silicon oxide film and a polysilicon film are formed, and a gate structure including a gate oxide film 3 and a gate electrode 4 is formed by using photolithography technology. Thereafter, impurity ions are implanted in a self-aligned manner with the gate structure to form a source region and a drain region, and the gate electrode 4 also becomes conductive. Thereafter, a silicon oxide film 5 is formed on the entire surface of semiconductor substrate 1.

Next, a connection hole reaching the source / drain region is formed in the silicon oxide film 5 by etching.
After the formation of the connection holes, the first storage electrode 6A of polysilicon doped with phosphorus by the supply rate control is formed as in the first embodiment. A void is formed in the connection hole by the formation of the polysilicon film by the supply control.

Next, as in the first embodiment, FIG.
As shown in FIG. 2B, a stacked capacitor is formed as the first storage electrode 6A, in which the void of the polysilicon film doped with phosphorus ions is used as the surface area of the storage electrode. Subsequent steps are the same as those in the first embodiment, and a description thereof will not be repeated.

In this case, it will be apparent that the second storage electrode 7A and the counter electrode 10 may also be polysilicon films doped with phosphorus ions.

[0045]

【The invention's effect】

As described above, according to the semiconductor device of the present invention, the voids are used as the surface area of the storage electrodes by forming polysilicon voids to be storage electrodes and etching back the voids. Can be. Therefore, the capacity of the capacitor can be increased.

Further, in the present invention, the polysilicon film is formed by controlling the supply for forming voids, so that the polysilicon film serving as the storage electrode can be formed without lowering the film forming speed.

Further, in the present invention, since voids at the time of forming the polysilicon film serving as the storage electrode are used, the MO
Without increasing the planar electrode area of the S capacitor
The surface area can be increased. Therefore, the present invention can cope with higher density and higher integration of the semiconductor element.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the semiconductor device in the manufacturing method according to the first embodiment of the present invention;

FIG. 3 is a sectional view of the semiconductor device in the manufacturing method according to the first embodiment of the present invention;

FIG. 4 is a sectional view of a semiconductor device in a manufacturing method according to a second embodiment of the present invention;

FIG. 5 is a cross-sectional view of a semiconductor device in a manufacturing method according to a first conventional example.

FIG. 6 is a cross-sectional view of a semiconductor device in a manufacturing method according to a first conventional example.

FIG. 7 is a sectional view of a semiconductor device in a second conventional example.

[Explanation of symbols]

 1, 21: semiconductor substrate 2, 22: silicon oxide insulating film for element isolation 3, 23: gate oxide film 4, 24: gate electrode 5, 25: silicon oxide film 6: first storage electrode 7: second storage Electrodes 8, 28: photoresist 9, 29: capacitive insulating film 10, 30: counter electrode 11: source / drain region 6A: first phosphorus-doped storage electrode 7A: second phosphorus-doped storage electrode 26 storage electrode

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/822 H01L 21/8242 H01L 27/04

Claims (9)

(57) [Claims] 1. A source region of a MOS transistor or
A hole reaching the drain region is formed, and the MOS transistor is formed.
An insulating film formed to cover the gate electrode of the transistor;BeforeFormed along the inner surface of the hole,PreviousMOS
TransistorSaidSource area orSaidDrain area
A conductive storage electrode connected to the region,The storage electrode is
Connected to the source region or the drain region
A first storage electrode unit, the first storage electrode unit, and the insulating film
And a second storage electrode portion formed on the
The width of the first cavity formed on the inner surface of the first storage electrode is
The width of the second cavity formed on the inner surface of the second storage electrode unit
Narrower,  In the holeCavityWhile covering the storage electrode.
A capacitive insulating film formed in the hole;BeforeRecord
Conductive counter electrode formed to cover the capacitive insulating film
A semiconductor device comprising: 2. The method according to claim 1, wherein the counter electrode is provided in the first cavity in the hole.
2. The device according to claim 1 , wherein the second cavity is formed so as to fill the cavity.
3. The semiconductor device according to claim 1. 3. The method according to claim 1, wherein said second storage electrode portion has a thickness equal to said first storage electrode portion.
The semiconductor device according to a thick claim 1 or 2 than the thickness of the storage electrode of the. 4. A semiconductor device comprising: a source region, a drain region, and a gate electrode;
To cover the gate electrode of the MOS transistor
Forming an edge film, the source region of the MOS transistor or the
Forming a hole in the insulating film to reach the drain region
Steps and a void in the holeSo that is formedThe insulating filmFirst on
One membraneForming;The first film is etched back and a first film is formed in the hole.
While leaving the cavity Along the inner surface of the hole,
Forming a pole, and the storage electrode comprises the first storage electrode.
An electrode film and a second storage electrode film, Forming a second cavity over the first cavity;
And forming the first storage electrode film on the insulating film and the first storage electrode film.
Forming two storage electrode films; Inside the holeCavityWhile covering the storage electrode.
Forming a capacitive insulating film, andPreviousMemoir
Forming a counter electrode so as to cover the quantitative insulating film;
A method for manufacturing a semiconductor device comprising: 5. The width of the first cavity is equal to the width of the second cavity.
The method for manufacturing a semiconductor device according to claim 4, wherein the width is smaller . 6. The method according to claim 1, wherein said second storage electrode film has a thickness equal to said first storage electrode film .
Rather thickness than the thickness of the storage electrode film, the counter electrode, the first
6. The method of manufacturing a semiconductor device according to claim 4 , wherein the first and second cavities are filled . 7. The first storage electrodefilmAnd the second storage power
veryMembranePolysilicon filmAnd  ImpuritiesThe first storage electrode filmDoping the
Doping an impurity into the second storage electrode film.
At least oneToFurtherClaims to be providedAny of 4 to 6
Or13. The method for manufacturing a semiconductor device according to item 5. Wherein said at least one of the first storage electrode film is formed forming a second storage electrode film and the step, the claims comprising the step of forming a polysilicon film doped with an impurity 7. The method for manufacturing a semiconductor device according to any one of 4 to 6 . 9. The method according to claim 9,First membraneForming a hole in the hole so that the supply of the growth gas is limited so that the hole is completely filled.
Chemical vapor deposition while controlling the deposition rate
The first along the inner surface of the holefilmSteps to form
StepIncluding The step of forming the second storage electrode film includes:  By limiting the supply of the growth gas, the voids are completely
Control the deposition rate so that
The insulating film by the phase growth methodWith the first storage electrode film
aboveForming a second storage electrode unit.
A method for manufacturing the semiconductor device according to claim 4.
Law.