JPH01108762A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To facilitate the setting of impurity concentration and the prediction of characteristics by uniformly introducing impurity to determine transistor characteristics into a part of side wall surface of a trench formed in a semiconductor, which part turns to a channel, by a means such as oblique ion implantation from the side wall surface. CONSTITUTION:A deep trench is formed on a substrate composed of P-type silicon 1 of high concentration and a P-type epitaxial layer 2. A storage capacitor part is formed in the inside of the trench, by using polycrystalline silicon electrode 4 to store electric charge and an SiO2 film 3. Further, an N-type layer 5 and a buried contact layer 6 turning to the source.drain of a vertical type transistor are formed. The inside of the trench is oxidized, and an SiO2 film 11 is grown on the side wall surface at which a channel 9 of the transistor is positioned. Boron ion 12 to determine transistor characteristics is ion- implanted obliquely to a channel regin 9, through the SiO2 film 11 from a trench aperture part. By this implantation, an impurity layer of uniform concentration is introduced in the region 9. Thereby a structure which is not different from usual transistors is realized in spite of a vertical type transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and particularly to a structure of an MO8 type transistor in which the sidewall of a trench formed in a semiconductor substrate is used as a channel region, and a method for manufacturing the same.

BACKGROUND OF THE INVENTION One of the memory cell structures of a dynamic RAM that enables large capacity and high degree of integration is shown in FIG.

The configuration of each part of this memory cell is as follows. That is, a deep groove is formed through the substrate on which the P-type epitaxial layer 2 is grown on the highly doped P-type silicon 1. 4 is a storage charge storage electrode made of N-type polycrystalline silicon containing phosphorus, 3 is an extremely thin S be making. On the other hand, in the switching transistor, polycrystalline silicon 4 is brought into contact with the N-type layer 6 formed on the surface of the epitaxial layer and the trench sidewall, and the N-type buried contact layer 6 obtained by diffusing phosphorus from 4 is used as the source, drain, The thin 5LO2 film 8 is used as a gate oxide film, and the polycrystalline silicon wiring 7 is used as a gate electrode, and the transistor is configured in a vertical direction, which is different from a normal transistor. Therefore, 6 and 6 on the groove side wall surface
The portion 9 sandwiched between the two serves as the channel region of this transistor. Further, the transistor and the storage capacitor are connected through 6, and the storage charge of the polycrystalline silicon electrode 4 is controlled to enter and exit the vertical transistor through the buried contact layer 6. As will be seen from now on, the polycrystalline silicon wiring 7 serves as a word line, and the N-type layer 6 serves as a bit line.

In the above memory cell, since the transistor as well as the storage capacitor can be vertically formed and placed in one trench, the area occupied by the cell is reduced, which is advantageous for high integration. Conventionally, electrical characteristics such as the threshold voltage vT of a vertical transistor have been determined by controlling the impurity concentration distribution of the epitaxial layer 2 including the channel region 9 in the depth direction.

Therefore, the concentration at a certain depth is constant in the horizontal direction. FIG. 3 is an example of the depth direction impurity concentration distribution in the AA cross section in FIG. 4.

The high concentration layer of arsenic (88) near the substrate surface is formed by arsenic 6, and its junction depth is about 0.8 μm. Below this, up to around 2.0 μm, is the position where the channel region of the vertical transistor exists, and its boron (B)
The concentration distribution determines the electrical characteristics. The boron concentration is ~5 X 10 /cd at a depth of ~0.8 μm
, depth 2.0μm! In l ~5 X 10'”/c
It is yf.

Problems to be Solved by the Invention As described above, in the conventional technology, the boron concentration has a depth distribution in the channel region of a vertical transistor, that is, the boron concentration changes continuously in the channel direction. , compared to a transistor with a normal horizontal structure in which the impurity concentration in the channel part is constant, it is more complicated to set the impurity concentration to obtain the desired characteristics;
Another drawback was that it became difficult to predict the electrical characteristics of such transistors.

SUMMARY OF THE INVENTION The present invention provides a vertical transistor structure and a method of manufacturing a sheep that overcomes the drawbacks of the prior art described above. In the present invention, an impurity that determines transistor characteristics is uniformly introduced from the sidewall surface of a groove formed in a semiconductor substrate into a portion of the sidewall surface that will become the channel by means such as oblique ion implantation, and then -The structure is made to have a similar impurity concentration.

Effect When impurities are introduced from the groove sidewall surface by oblique ion implantation, the same amount of impurity is introduced into every part of the sidewall surface, so the impurity concentration in the channel direction is not uniform, and the normal horizontal It has the same structure as a transistor.

Therefore, it is possible to set the impurity concentration and predict the characteristics of the transistor using conventionally established methods.

Embodiment FIGS. 1a and 1b are cross-sectional views showing the process of forming a vertical transistor in a memory cell of a dynamic RAM according to the manufacturing process according to the present invention. In FIG. 1a, first, a deep groove is formed in a substrate consisting of a highly doped P-type silicon 1 and a P-type epitaxial layer 2 by a conventional method, and a polycrystalline silicon electrode 4 for charge storage and an SiO2 layer are formed inside the groove. □ A memory capacitor portion is formed using the film 3, and an N-type layer 5 and a buried contact layer 6, which will become the source and drain of the vertical transistor, are also formed. Next, the inside of the trench is oxidized, and an 8102 film 11 with a thickness of 10 to 20 nm is grown on the side wall surface where the channel portion 9 of the transistor is located. After this, boron ions 12, which determine transistor characteristics, are implanted diagonally from the trench opening through the 8102 film 11 into the channel region 9. The implantation angle may be selected so that the ions incident from the trench opening sufficiently reach the trench bottom. It can be seen that the impurity layer 13 having a −-like concentration is introduced into the region 9 by implantation, and this process is the same as that in manufacturing a normal horizontal structure transistor. Poron ions 12 are also implanted into the N shadow regions 4, 5.6. However, since the implantation is mainly for threshold voltage control, the concentration of the boron implanted layer is ~1017/cII, and the region 4
, 5.6, there are four surfaces in total, the two shown in the diagram with N-type impurity concentration and two surfaces perpendicular to these, so the oblique ion implantation was performed four times with the boron beam direction facing each surface. Must be. After ion implantation, S102 film 11
is removed with a hydrofluoric acid solution, the trench sidewall surface is oxidized again to grow a gate oxide film 8 with a thickness of 10 to 15 nm, and a polycrystalline silicon wiring 7 that will become a gate electrode is formed, as shown in Figure 1. A vertical transistor is completed in the memory cell as shown in the figure.

In order to obtain a uniform boron impurity distribution in the channel region of the trench sidewall, it is also possible to use a BSG film as shown in FIG. In Figure 2, 14 is approximately 30-50 nm
This is a polycrystalline silicon film with a certain thickness and was used as part of an etching mask when forming deep grooves. After exposing the trench sidewalls 9, a BSG film 16 containing boron at a predetermined concentration is deposited, and high-temperature Mabolon can be diffused onto the surface of the trenches 9 at a uniform concentration. After diffusion, BSG film 1
The polycrystalline silicon film 14 protects the thick S102 film 10 when the S102 film 6 is removed using a hydrofluoric acid etching solution. Finally, the film 14 is removed and a gate oxide film and a gate electrode are formed as shown in FIG.

Another method for uniformly introducing impurities into the trench sidewalls is diffusion from a gas phase such as plasma doping. However, the oblique ion implantation method is most suitable for K in order to accurately and controllably introduce low concentration impurities such as setting a threshold voltage.

It goes without saying that the present invention can be applied not only to the vertical transistors in the memory cells shown in the embodiments, but also to vertical transistors incorporated in other devices.

Effects of the Invention As described above, in the present invention, impurities can be uniformly introduced into the sidewalls of the trench by simple means such as oblique ion implantation, so even if the transistor is vertical, it is different from a normal transistor. No structure is realized, therefore impurity concentration setting,
Characteristics can be predicted without difficulty, and its effects are demonstrated.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view explaining a first embodiment of manufacturing a vertical transistor according to the present invention, FIG. 2 is a cross-sectional view explaining a second embodiment of the present invention, and FIG. 3 is a cross-sectional view of a conventional vertical transistor. The impurity distribution diagram, FIG. 4, is a cross-sectional view of a conventional vertical transistor. 1...High concentration P type silicon, 2...P
Type epitaxial layer, 3, 10, 11...51
02 film, 4...polycrystalline silicon electrode, 6...
... N-type layer, 6 ... Buried contact layer, 7
...Polycrystalline silicon wiring, 8...Gate oxide film, 9...Channel region, 12...
...Boron ion, 13...Boron implanted layer, 1
4...Polycrystalline silicon film, 16...B
SG membrane. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 3
Figure 4 &! J

Claims (3)

[Claims] (1) A semiconductor device including a vertical transistor that uses a sidewall surface region of a trench formed in a semiconductor substrate as a channel, and in which impurities introduced into the channel region are uniformly distributed in the direction of the sidewall surface. (2) A method for manufacturing a semiconductor device in which impurities are introduced into a portion of the sidewall surface region of a trench formed in a semiconductor substrate, which is to become a channel of a transistor, so as to have a uniform distribution in the direction of the sidewall surface. . (3) The method for manufacturing a semiconductor device according to claim 2, wherein the impurity introduction method is oblique ion implantation.