JPH0831568B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a MOS (Metal-Oxide-Semiconductor) type semiconductor memory device, and in particular, each memory cell is composed of one transistor and one capacitor. The present invention relates to a semiconductor memory device.

(Prior Art) As the degree of integration of a semiconductor memory device has advanced, it has become necessary to reduce the plane area occupied by the main surface of the semiconductor substrate per memory cell. Therefore, it is necessary to reduce the plane area of each of the transistor and the capacitor on the main surface of the substrate. However, if the capacitor is simply downsized, its storage capacity is reduced, which causes malfunction of the semiconductor memory device. Therefore, a semiconductor memory device having a capacitor structure called a stacked capacitor or a capacitor structure called a trench capacitor has been proposed.

The general structure of the semiconductor memory device having the trench capacitor structure was as described below. FIG. 4 is a diagram used for the explanation, and is a cross-sectional view schematically showing a semiconductor memory device having a trench capacitor, focusing on one memory cell portion thereof.

According to this semiconductor memory device, a groove 13 for forming a capacitor is provided in a predetermined region of a semiconductor substrate (silicon substrate) 11. Further, in the groove 13, a charge storage electrode 17 made of polysilicon, a capacitor dielectric film 19 formed by oxidizing the surface of polysilicon, and a cell plate 21 made of polysilicon are sandwiched with an insulating film 15 interposed therebetween. It is buried in order. In addition, a transfer gate transistor is formed in a region adjacent to the capacitor groove 13 of the semiconductor substrate 11.
23 are provided. Further, the charge storage electrode 17 is connected to one active region 25 of the transfer gate transistor 23, and the bit line is connected to the other active region 27.
29 is connected. In the figure, 31 is a gate electrode of the transfer gate transistor 23, 33 is a word line, and 35 is a word line.
Is an insulating film.

According to the semiconductor memory device as described above, since the capacitor is formed three-dimensionally by utilizing the groove 13, the required charge storage capacitance can be obtained while reducing the plane area occupied by the substrate surface of the capacitor. It was Further, since there is a capacitor in the substrate, there is an advantage that a soft error caused by α rays is unlikely to occur.

(Problems to be Solved by the Invention) However, even in the above-described semiconductor memory device using the trench capacitor, the capacitor and the transistor must be arranged in a plane on the semiconductor substrate. Therefore, it is necessary to secure an area for forming each of the capacitor and the transistor on the semiconductor substrate. Therefore, there is a limit in reducing the plane area of one memory cell.

Further, in order to reduce the plane area of one memory cell, the gate length and gate width of the transistor are also reduced.
However, such a reduction has a limit because it involves variations in the threshold voltage due to the short channel effect and the narrow channel effect. As one structure that can solve these problems, a semiconductor memory device including a large number of memory cells, in which each memory cell is an insulating film formed on a silicon substrate (also referred to as a “lower insulating film”). Each of the memory cells formed on the lower insulating film has a charge storage electrode, a first source / drain diffusion layer, a channel semiconductor layer, and a second source / drain diffusion layer. A columnar body including layers in this order, a capacitor dielectric film surrounding the charge storage electrode, a plate electrode surrounding the capacitor dielectric film, a gate insulating film surrounding the channel semiconductor layer, and a gate insulating film A semiconductor memory device having a structure including a gate electrode surrounding the is conceivable. According to this structure, the main portion of the transistor and the main portion of the capacitor are three-dimensionally overlapped in the columnar body, so that the plane area of one memory cell can be reduced, and the gate length can be reduced. The gate width is determined by the thickness of the channel semiconductor layer and is determined by the cross-sectional area of the channel semiconductor layer cut in the direction parallel to the main surface of the silicon substrate, and thus is not easily affected by the short channel effect and the narrow channel effect. Because. However, there has been no method for easily manufacturing a semiconductor device having such a structure.

(Means for Solving the Problem) In order to achieve this object, according to the present invention, there is provided a semiconductor memory device having a large number of memory cells, each memory cell being an insulating film formed on a silicon substrate. Each memory cell is formed on the (lower insulating film), and each memory cell has a charge storage electrode, a first source / drain diffusion layer, a channel semiconductor layer, and a channel semiconductor layer which are provided on the lower insulating film. A columnar body having two source / drain diffusion layers in this order, a capacitor dielectric film surrounding the charge storage electrode, a plate electrode surrounding the capacitor dielectric film, and a gate insulating film surrounding the channel semiconductor layer. In manufacturing a semiconductor memory device having a structure including a gate electrode surrounding the gate insulating film, an oxygen ion is implanted into a region of a predetermined depth from the surface of the silicon substrate by an ion implantation method. And a step of performing a heat treatment on the silicon substrate in which the oxygen ions have been implanted to oxidize the vicinity of the region in which the oxygen ions have been implanted, to obtain the lower insulating film, and the silicon substrate after the heat treatment. And a step of growing a high impurity concentration silicon layer and a silicon layer in this order using the silicon single crystal portion remaining on the surface layer of the silicon substrate as a seed, and the columnar structure on the surface of the grown silicon layer. A step of forming an etching mask for forming a silicon pillar as an intermediate for obtaining a body, and a portion of the formed silicon layer, a high impurity concentration silicon layer and the seed exposed from the etching mask Are removed to obtain the silicon pillar, and the silicon pillar portion having the high impurity concentration in the silicon pillar is provided. A step of obtaining a charge storage electrode, a step of forming an oxide film on a side surface of the silicon pillar by a thermal oxidation method, and a step of obtaining the capacitor dielectric film with a portion of the oxide film in contact with the obtained charge storage electrode, A step of forming a polysilicon layer with a predetermined thickness between the silicon pillars of the sample on which the capacitor dielectric film has been formed to obtain the plate electrode, and the silicon of the sample on which the plate electrode has been formed. The step of forming a first layer, which serves as a solid layer diffusion source for forming the first source / drain layer, with a predetermined thickness on the portion between the pillars, and the formation of the first layer are completed. A step of forming a gate electrode with a predetermined thickness on the portion between the silicon pillars of the sample, and a second source / drain layer on the portion between the silicon pillars of the sample after the formation of the gate electrode. Solid layer expansion to form Forming a second layer to be a source with a predetermined thickness, and diffusing impurities of the first and second layer pillars into corresponding portions of the silicon pillar, respectively, and the first and second sources. And a step of forming a drain layer.

(Operation) According to the configuration of the present invention, since the SIMOX and the crystal growth technique are used, the lower insulating film for electrically separating each memory cell from the lower side thereof and the semiconductor layer for obtaining the silicon pillar are formed. And can be easily obtained respectively. Further, when the processing for forming the silicon pillar is completed, the charge storage electrode can be formed at the same time. The first and second source / drain diffusion layers are formed by solid layer diffusion of impurities from the first and second layers which are solid layer diffusion sources formed around the silicon pillar. Here, since the first layer serving as the solid layer diffusion source is formed on the plate electrode, the first layer is formed with a predetermined positional relationship with respect to the charge storage electrode facing the plate electrode. . Therefore, the first source / drain diffusion layer formed by using the first layer as a diffusion source is surely formed in a state where electrical connection with the charge integration electrode is secured, and The electric connection between the capacitor section and the capacitor section is stably ensured.

(Embodiment) An embodiment of a method for manufacturing a semiconductor memory device of the present invention will be described below with reference to the drawings. It should be noted that each of the drawings used for the description is only schematically shown to the extent that the present invention can be understood, and therefore the dimensions and shapes of the respective constituents, and the dimensional ratios between the respective constituents are also schematic, It should be understood that the invention is not limited to the illustrated example.

Description of Structure First, the structure of a semiconductor memory device manufactured by the manufacturing method of the embodiment will be described with reference to FIGS. 1 (A) and 1 (B). Here, FIG. 1 (A) is a perspective view showing a semiconductor memory device manufactured by the manufacturing method of the embodiment, focusing on one memory cell part thereof and showing a part of the semiconductor memory device. Further, FIG. 1B is a cross-sectional view showing the semiconductor memory device manufactured by the manufacturing method of the embodiment, focusing on the two memory cell portions and cut along the direction orthogonal to the bit lines. The relationship between the two figures is I in the perspective view shown in FIG.
The cross-sectional portion cut along the line -I has a relationship substantially corresponding to the portion P surrounded by the dotted line in the cross-sectional view shown in FIG. 1 (B). In FIG. 1 (A), some of the constituent components shown in FIG. 1 (B) are omitted.

In FIGS. 1A and 1B, 41 is a semiconductor substrate, for example, a p-type silicon substrate. An insulating film 43 such as a silicon oxide film 43 is provided on the p-type silicon substrate 41. The semiconductor memory device manufactured by the manufacturing method of the embodiment has a large number of memory cells on the silicon oxide film 43. Note that one memory cell is a portion P surrounded by a dotted line in FIG.

Each memory cell is provided on the silicon oxide film 43,
For example, an n ⁺ type silicon layer 45 as the charge storage electrode 45, for example an n type silicon layer 47 as the first source / drain diffusion layer 47, a silicon layer 49 as the channel semiconductor layer 49, and a second source / drain layer. For example, a columnar body 53 having an n-type silicon layer 51 as the order 51 is provided. Further, each memory cell further includes a capacitor dielectric film 55 formed of, for example, a silicon oxide film surrounding the charge storage electrode 45, a plate electrode 57 formed of, for example, polysilicon surrounding the capacitor dielectric film 55, and a channel semiconductor layer 49. A gate insulating film 59 made of, for example, a silicon oxide film, and a gate electrode made of, for example, polysilicon, surrounding the gate insulating film 59.
61 and.

Here, the cross-sectional shape of the above-mentioned columnar body 53 taken in the direction parallel to the main surface of the silicon substrate 41 is, in the case of this embodiment,
It has a substantially square shape. However, the cross-sectional shape can be any suitable shape according to the design of the semiconductor memory device. The cross-sectional area of the columnar body 53 is determined according to the design of the semiconductor memory device. The columnar body of this example
The method of forming 53 will be described in the section of the manufacturing method described later.

Further, in this semiconductor memory device, the charge storage electrode 45, the capacitor dielectric film 55, and the plate electrode 57 described above are used.
A capacitor is constituted by The capacitance of this capacitor depends on the dielectric constant and film thickness of the capacitor dielectric 55,
Height of the charge storage electrode 45, the capacitor dielectric film 55, and the plate electrode 57 (dimensions in the direction perpendicular to the main surface of the silicon substrate 41)
Can be determined by Therefore, these parameters are set to appropriate values according to the desired capacitor capacity.

Further, in this semiconductor memory device, since the layer thickness of the above-described channel semiconductor layer 49 becomes a substantial gate length, the layer thickness of the channel semiconductor layer 49 has an appropriate value according to the design of the semiconductor memory device. To do.

Further, in FIGS. 1A and 1B, 63 is a bit line made of, for example, an aluminum thin film. The bit line 63 in this embodiment is a columnar body as shown in FIG. 1 (B).
The second source / drain diffusion layer 51 at the upper end of 53 is provided so as to be connected to the second source / drain diffusion layer 53 at the end surface parallel to the main surface of the capacitor substrate 41.

Next, some components shown in FIG. 1 (B) and not shown in FIG. 1 (A) will be described.

In FIG. 1 (B), 65 structurally contributes as a spacer layer. For example, PSG (Phospho Sil)
icate Glass) layer. The PSG layer 65 will function as an impurity diffusion source for forming the first source / drain diffusion layer 47 in terms of the manufacturing process, which will be described in detail later. Furthermore, 67 is the gate electrode 61 in the manufacturing process.
Used as a mask when obtaining
It is a layer. Further, 69 structurally contributes as an intermediate insulating layer, and is, for example, a PSG layer. This PSG layer 69
As will be described later in detail, when viewed from the manufacturing process, it functions as an impurity diffusion source for forming the second source / drain diffusion layer 51.

The above is the description of the structure of the semiconductor memory device manufactured by the manufacturing method of the embodiment. However, the configuration described above is merely an example, and various modifications can be added.

For example, the PSG layer 67 included in the semiconductor memory device manufactured by the manufacturing method of the embodiment is a layer that remains because of the manufacturing process (details will be described later). Both good.

Further, in order to ensure the electrical connection between the bit line 63 and the second source / drain diffusion layer, for example, the second line
As shown in the figure, the upper side surface of the second source / drain diffusion layer 51 is exposed from the PSG layer 69, and the bit line 63 is formed on the upper surface and the exposed side surface of the second source / drain diffusion layer 51.
May be connected.

Description of Manufacturing Method Next, an example of a method of manufacturing the semiconductor memory device of the present invention will be described. FIGS. 3 (A) to 3 (S) are diagrams used for the explanation, and a state of the semiconductor memory device in the main steps of the manufacturing process pillar is shown in a sectional view at the same position as in FIG. 1 (B). Is shown. In these figures,
The same components as those shown in FIG. 1 are designated by the same reference numerals. Further, in order to avoid complication of the drawing, some hatching showing the cross section is omitted.

First, 10 ¹⁸ O ⁺ ions 71 are added to the p-type silicon substrate 41.
The implantation is performed under the condition that the acceleration voltage is, for example, about 180 KeV on the order of / cm ³ . As a result, O ⁺ ions are implanted at a position of depth d (approximately 130 nm) when viewed from the surface of the silicon substrate 41 (FIG. 3 (A)).

Next, the O ⁺ ion-implanted silicon substrate is annealed under predetermined conditions. As a result, a layer 43 of a silicon oxide film is obtained in the silicon substrate 41, and the surface layer portion 41a of the silicon substrate 41 remains a silicon single crystal (FIG. 3 (B)). The technique described with reference to FIGS. 3A and 3B is known as SIMOX (Separation by Implanted Oxygen).

Next, using the surface layer portion 41a of the silicon substrate as a seed, a n ⁺ type silicon layer 45a as a silicon layer having a high impurity concentration is formed by a known crystal growth technique to have a thickness of, for example, about 3 μm (see FIG. C)). This n ⁺ type silicon layer 45a
Will later become the charge storage electrode 45. In the step of forming the n ⁺ silicon layer 45a, the surface layer portion 41a of the silicon substrate 41 also becomes an n ⁺ type silicon layer.

Next, a single crystal silicon layer 73 is formed on the n ⁺ type silicon layer 45a by a known crystal growth technique to have a thickness of, for example, about 5 μm (FIG. 3 (D)).

Next, a silicon oxide film (not shown) having a film thickness of 1 μm, for example, is formed on the single crystal silicon layer 73 by, for example, the CVD method, and a resist (not shown) is applied on the silicon oxide film. Next, this resist is patterned by a known photolithography technique to form a resist pattern 77. Then, using the resist pattern 77 as a mask, the silicon oxide film is patterned by a known etching technique to form a mask 75 made of SiO ₂ (FIG. 3 (E)).

Next, the resist pattern 77 is removed, and then the portions of the silicon single crystal layer 73 and the n ⁺ -type silicon layer 45a exposed from the mask 75 are silicon-oxidized by anisotropic etching using the mask 75 made of SiO ₂ as a mask. Each is removed until the film 43 is exposed to obtain a silicon pillar 79. At the end of the step of obtaining the silicon pillar 79, the charge storage electrode 45 is obtained (FIG. 3 (F)).

Next, a film thickness of, for example, 10 is formed on the silicon pillar 79 by thermal oxidation.
A 0Å silicon oxide film 55a is formed. A portion of the silicon oxide film 55a surrounding the charge storage electrode 45 becomes a capacitor dielectric film 55 (FIG. 3 (G)).

Next, on the upper side of the silicon substrate 41 having the silicon pillar 79 and the like, by a method such as a CVD method having excellent step coverage,
The polysilicon layer 57a is formed to have a film thickness (about 2.5 .mu.m) which is almost the same height as the charge storage electrode 45, for example. This polysilicon layer 57a will later become the plate electrode 57. Therefore, in order to reduce the resistance, a polysilicon layer containing impurities such as phosphorus at a high concentration is used.
Then, a flattening layer 81 for flattening the step is formed on the polysilicon layer 57a (FIG. 3 (H)). In addition,
The flattening layer 81 needs to be a material that enables selective etching performed in the next step, and can be made of, for example, a resist.

Next, under the etching conditions such that the flattening layer 81 and the polysilicon layer 57a can be etched at a constant rate and the silicon oxide film 55a is not substantially etched, specifically, for example, a barrel type etching apparatus is used. Under the condition that the etching gas used is CF ₄ gas or a mixed gas of CF ₄ and O ₂ ,
The flattening layer 81 and the polysilicon layer 57a are etched by a predetermined amount. This etching was performed until the surface of the portion of the polysilicon layer 57a on the silicon oxide film 43 was exposed. As a result, the plate electrode 57 having a film thickness of 2.5 μm is obtained (FIG. 3 (I)).

Next, on the upper side of the silicon substrate 41 on which the plate electrode 57 is formed, a solid layer diffusion source for forming the first source / drain diffusion layer is formed by a method such as a CVD method having excellent step coverage. For example, a PSG layer 65a containing phosphorus as an impurity in a high concentration, for example, is formed to a predetermined thickness as one layer. This PSG layer 65a is the first source shown in FIG.
It has a function as an impurity diffusion source for forming the drain diffusion layer 47 and a function as a spacer layer. Specifically, phosphorus in the PSG layer 65a penetrates the silicon oxide film 55a by the heat treatment performed later and reaches the region of the silicon pillar 79 surrounded by the PSG layer 65a to form the first source / drain diffusion layer 47. . Therefore, the layer thickness of the PSG layer 65a is determined in consideration of the layer thickness of the first source / drain diffusion layer 47. The layer thickness of the PSG layer 65a in this embodiment is 1 μm. Then, a flattening layer 83 for flattening the step is formed on the PSG layer 65a (third part).
(Figure (J)). The flattening layer 83 needs to be a material that enables selective etching performed in the next step, and can be made of, for example, a resist or the like.

Next, under such etching conditions that the flattening layer 83 and the PSG layer 65a can be etched at a constant rate and the silicon pillar 79 is not substantially etched, specifically, for example, RIE (reactive ion etching). ) Apparatus is used to etch the flattening layer 83 and the PSG 65a by a predetermined amount under the condition that the etching gas is CHF ₃ , C ₂ F ₆ or C ₃ F ₈ gas. This etching was performed until the surface of the portion of the PSG layer 65a on the plate electrode 57 was exposed. As a result, a PSG layer 65 having a film thickness of 1 μm and having a function as a spacer and a diffusion source is obtained (FIG. 3 (K)).

Next, a silicon oxide film 59a is formed on a portion of the silicon pillar 79 exposed from the PSG layer 65 by a thermal oxidation method (third part).
(Figure (L)). A part of the silicon oxide film 59a becomes the gate insulating film 59. Therefore, the film thickness of the silicon oxide film 59a is set to an appropriate film thickness according to the design of the semiconductor memory device.

Next, a polysilicon layer 61a having a predetermined thickness is formed on the upper side of the silicon substrate 41 on which the silicon oxide film 59a has been formed for forming a gate electrode by a method such as a CVD method having excellent step coverage. The polysilicon 61a contains impurities such as phosphorus in a high concentration in order to reduce the resistance. The thickness of the polysilicon layer 61a substantially determines the channel length of the transistor. Therefore, the layer thickness of the polysilicon layer 61a is set to an appropriate layer thickness according to the design of the semiconductor memory device. The layer thickness of the polysilicon layer 61a in this embodiment is 1 μm. Then
On the polysilicon layer 61a, for example, C having excellent step coverage is provided.
The PSG layer 67 is formed to a predetermined thickness by a method such as the VD method.
Further, a flattening layer 85 for flattening the step is formed on the PSG layer 67 (FIG. 3 (M)). Note that this flattening layer
85 needs to be a material that enables selective etching to be performed in the next step, and can be made of, for example, a resist or the like.

Next, under the condition that the flattening layer 85 and the PSG layer 67 can be etched at a constant speed and the polysilicon layer 61a is not substantially etched, specifically, for example, CHF ₃ , an etching gas using an RIE device, The flattening layer 85 and the PSG layer 67 are etched by a predetermined amount under the conditions of C ₂ F ₆ or C ₃ F ₈ gas. This etching was performed by removing the flattening layer 85 and the PSG layer 67 so that the PSG layer 67 remained under the silicon pillar 79 with a film thickness of 0.5 μm (FIG. 3 (N)).

Next, the polysilicon layer 61a is etched, but the PSG layer
67 is a condition that does not substantially etch. Specifically, for example, a barrel type etching device is used to supply an etching gas.
The polysilicon layer 61a is etched by a predetermined amount under the condition of CF ₄ gas or a mixed gas of CF ₄ and O ₂ . In the case of this embodiment, the surface of the polysilicon layer 61a is a PSG layer in this etching.
It was carried out to a position slightly higher than the surface of 67. The remaining portion of the polysilicon layer 61a after this etching and the portion of the silicon oxide film 59a between the silicon pillar 79 become the gate insulating film 59 (FIG. 3 (O)). The polysilicon layer 61
When etching a, the surface of the polysilicon layer 61a is PSG layer 67.
You may perform it until it becomes flush with the surface of.

Next, the polysilicon layer 61a after this etching is completed.
A resist is applied on the PSG layer 67 and the PSG layer 67 (not shown), and then a resist pattern corresponding to the gate electrode shape is formed by a known method (not shown). Then, the polysilicon layer 61a and the PSG layer 67 are formed. The unnecessary portions of are removed to obtain the gate electrode 61 (FIG. 3 (P)).

Next, the silicon substrate 41 on which the formation of the gate electrode 61 is completed
A high concentration of, for example, phosphorus as a first layer serving as a solid layer diffusion source for forming the first source / drain diffusion layer by a method such as a CVD method having excellent step coverage on the upper side of the The PSG layer 69 is formed to have a film thickness capable of completely filling the silicon pillar 79 (FIG. 3 (Q)). This PSG
Layer 69 is the second source / drain diffusion layer shown in FIG.
It has a function as an impurity diffusion source for forming 51 and a function as an intermediate insulating layer.

Next, under the condition that the PSG layer and the silicon oxide film can be etched and the silicon is not substantially etched, specifically, for example, using an RIE device, etching gas is CHF ₃ , C ₂ F _2.
The PSG layer 69 and the silicon oxide film 59a are etched by a predetermined amount under the condition of ₆ or C ₃ F ₈ gas. This etching in this embodiment was performed until the upper end of the silicon pillar 79 was exposed (FIG. 3 (R)).

Next, from the top of the silicon pillar 79 to this silicon pillar 79,
P ⁺ ions 87 are implanted under the condition that the acceleration voltage is, for example, about 70 KeV. Then, a predetermined annealing process is performed. In this annealing step, the PSG layer 65 containing a high concentration of phosphorus 65
From the silicon pillar 79 to the region facing the PSG layer 65
9 diffuses, and as a result, the first source / drain diffusion layer 47 is formed on a predetermined portion of the silicon pillar. Similarly, PSG layer 6
Phosphorus atoms in the region of the silicon pillar 79 facing the PSG layer 69 from 9
89 diffuses, and as a result, the second source / drain diffusion layer 51 is formed on a predetermined portion of the silicon pillar 79. Further, the P ⁺ ions 87 implanted by the ion implantation form a high-concentration diffusion layer on the upper part of the silicon pillar 79 for improving the connection with the bit line (FIG. 3 (S)).

Then, an aluminum film having a film thickness of, for example, 6000Å is formed in the upper region of the silicon substrate including the second source / drain diffusion layer 51 by a known film forming method (not shown). After that, the aluminum film is patterned by the known photolithography technique and etching technique to obtain the bit line 63, and the semiconductor memory device shown in FIG. 1B is obtained.

The above is an example of the method for manufacturing the semiconductor memory device of the embodiment. According to the manufacturing method described above, it is possible to obtain the effect that the positional relationship between the first and second source / drain diffusion layers 47 and 51 and the gate electrode 61 can be determined in a self-aligned manner.

It should be understood that the above-described manufacturing method is merely an example, and the method, the numerical conditions used in the description, the material used, the device used, etc. are merely examples.

(Effects of the Invention) As is apparent from the above description, according to the method of manufacturing a semiconductor memory device of the present invention, a lower insulating film for electrically separating each memory cell on the lower side thereof, The semiconductor layer for obtaining the silicon pillar can be easily obtained respectively. Further, when the process of forming the silicon pillar is completed, the charge storage electrode can be formed at the same time. Further, the first source / drain diffusion layer formed on the charge storage electrode side is formed in a state where the electric connection with the charge storage electrode is surely ensured, so that the electrical connection between the transistor part and the capacitor part is made. Secure connection. Therefore, the semiconductor memory device having the following features can be easily manufactured.

Since the main part of the transistor and the main part of the capacitor are three-dimensionally stacked on the semiconductor substrate, the plane area occupying the main surface of the semiconductor substrate of each memory cell can be very small.

Since the gate length of the transistor can be determined by the thickness of the channel semiconductor layer, a desired gate length can be secured without increasing the plane area of the transistor.

Since the gate electrode surrounds the channel semiconductor layer, the cross-sectional area of the current path can be increased as compared with the conventional planar transistor. Therefore, the generation of hot electrons can be reduced.

Therefore, it is possible to provide a semiconductor memory device which has a high degree of integration and is not easily affected by the short channel effect and the narrow channel effect.

Further, according to the semiconductor memory device of the present invention, it is possible to obtain further unique effects as described below.

The capacitor capacity can be easily increased by increasing the height of the capacitor section.

Since the capacitor has a structure in which it is filled with the insulating film provided on the semiconductor substrate and the high-concentration polysilicon that is the plate electrode, a soft error due to α-rays is unlikely to occur.

... The source / drain diffusion layer of the transistor and the bit line can be contacted by using the upper end of the silicon pillar and the side wall near the upper end, so that the contact area with the bit line is large and a highly reliable wiring structure can be obtained. To be

[Brief description of drawings]

FIG. 1 (A) is a perspective view showing a memory cell part of a semiconductor memory device manufactured by the manufacturing method of the embodiment by cutting away a part thereof, and FIG. 1 (B) is a manufacturing method of the embodiment. Sectional drawing which shows the 2 memory cell part of the manufactured semiconductor memory device, FIG. 2 is a principal part sectional view which shows the modification of the semiconductor memory device manufactured by the manufacturing method of Example, FIG. (S) is a process drawing showing an example of a method of manufacturing a semiconductor memory device manufactured by the manufacturing method of the embodiment, and FIG. 4 is a sectional view showing an example of a conventional semiconductor memory device. 41 …… Semiconductor substrate, 43 …… Insulating film 45 …… Charge storage electrode 47 …… First source / drain diffusion layer 49 …… Channel semiconductor layer 51 …… Second source / drain diffusion layer 53 …… Column Body 55 …… Capacitor dielectric film 57 …… Plate electrode, 59 …… Gate insulating film 61 …… Gate electrode, 63 …… Bit line 65,67,69 …… PSG layer.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 27/04

Claims (1)

[Claims] 1. A semiconductor memory device comprising a large number of memory cells, wherein each memory cell is formed on an insulating film (lower insulating film) formed on a silicon substrate, and each memory is formed. The cell has a columnar body including a charge storage electrode provided on the lower insulating film, a first source / drain diffusion layer, a channel semiconductor layer, and a second source / drain diffusion layer in this order, and It has a structure including a capacitor dielectric film surrounding the charge storage electrode, a plate electrode surrounding the capacitor dielectric film, a gate insulating film surrounding the channel semiconductor layer, and a gate electrode surrounding the gate insulating film. In manufacturing a semiconductor memory device, a step of implanting oxygen ions into a region of a predetermined depth from the surface of a silicon substrate by an ion implantation method, and a step of implanting oxygen ions in the silicon substrate A step of performing a heat treatment to oxidize the vicinity of the oxygen ion-implanted region to obtain the lower insulating film; and a silicon single layer remaining on the surface of the silicon substrate on the silicon substrate after the heat treatment. A step of growing a high-impurity-concentration silicon layer and a silicon layer in this order by using the crystal part as a seed, and forming a silicon pillar as an intermediate for obtaining the pillar-shaped body on the surface of the grown silicon layer. And a step of forming an etching mask, and removing portions of the formed silicon layer, high impurity concentration silicon layer and seed from the etching mask to obtain the silicon pillar and the silicon pillar. In the step of obtaining the charge storage electrode with the high-impurity concentration silicon layer portion, and by a thermal oxidation method on the side surface of the silicon pillar. The oxide film is formed,
A step of obtaining the capacitor dielectric film with a portion of the oxide film in contact with the obtained charge storage electrode; and a polysilicon layer having a predetermined thickness between the silicon pillars of the sample on which the capacitor dielectric film has been formed. Forming a layer and obtaining the plate electrode with the layer, and a solid layer diffusion source for forming a first source / drain layer on a portion between the silicon pillars of the sample on which the plate electrode has been formed. Forming a first layer having a predetermined thickness, and forming a gate electrode with a predetermined thickness on a portion between the silicon pillars of the sample on which the first layer has been formed, A step of forming a second layer having a predetermined thickness as a solid layer diffusion source for forming a second source / drain layer on a portion between the silicon pillars of the sample on which the gate electrode has been formed. And the impurities in the first and second layers Method of manufacturing a semiconductor memory device which comprises a step of forming a corresponding said first and second source-drain layer by diffusing each portion of an object the silicon pillar.