JPS61144059A - Semiconductor memory storage - Google Patents

Abstract

PURPOSE:To obtain a small-sized dRAN cell having large capacitance by forming a projecting section in substantially the same width as a groove to a frame-shaped capacitor electrode surrounding a cell, shaping a similar configuration gate electrode to the inner wall of the projecting section through self- alignment and integrally forming the gate electrode with a gate electrode for an adjacent memory cell through a breaking section in the projecting section. CONSTITUTION:A silicon nitride film 21 is formed to a P<-> type silicon substrate 11, the substrate is etched in a latticed and striped manner while using the nitride film 21 as a mask, boron ions are implanted to the base, and a field oxide film 13 is buried flatly. The whole surface of the field oxide film 13 is etched, a thin oxide film 14 is shaped by thermally oxidizing the surface of a groove 12 while being left only on the bottom of the groove 12, and N<+> polycrystalline silicon is buried flatly to form a capacitor electrode 15. A projecting section in the capacitor electrode 15 is removed. The whole surface of N<+> polycrystalline silicon 24 is etched in the vertical direction through reactive ion etching. Accordingly, a frame-shaped /gate electrode (a word line) self- aligned with the inner wall of the capacitor electrode 15 blocks a capacitor removing section, and is shaped integrally regarding a cell in the line direction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, particularly a dynamic RAM.

[Technical background of the invention and its problems]

Conventionally, as a dRAM cell, one described in Japanese Patent Application Laid-Open No. 59-2362 is known. FIG. 4(,1) is a plan view, and FIG. 4(b) is a cross-sectional view of the entrance. That is, S made by P
Grooves (L2) are dug in the T-substrate (11) in the form of checkered stripes, a layer of soil is formed at the bottom of the grooves, and a field oxide film (13) is provided. And in this groove, a thin acid film (14)
A capacitor electrode (15) is provided on the bottom plate surface, and a capacitor electrode (15) is provided on the surface of the base plate via a gate acid film (16).
1'7) is provided. In addition, gate electrodes (18) are formed on both sides of the gate electrode (17), and an oxide film (1
9) Enter through the opened contact hole C1! Wiring (20) is provided.

Such a dR input M cell can obtain a large storage capacity because the surrounding area of the cell can be used as a capacitor, but there is a problem that the cell area is large. For example, in the memory cell, the capacitor electrode (15) has a protruding portion on the cell,
Also, the gate voltage of MQSFET for cell selection @ (17)
n+! between and the capacitor electrode (15). if (18
), which is one of the reasons why a large cell area is required.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and an object of the present invention is to provide a compact and large capacity dR input M cell.

[Summary of the invention]

In the present invention, a frame-shaped capacitor 1 surrounding a cell is provided with a protrusion having substantially the same width as the groove, a gate electrode having a similar shape is self-aligned to the inner wall of the protrusion, and the gate electrode is placed in a field region. The main point is that one date electrode of an adjacent memory cell is formed via the missing part of the protrusion provided in the first part.

〔Effect of the invention〕

According to the present invention, there is no protrusion of the capacitor electrode onto the cell, and there is no need for an impurity layer between the capacitor electrode and the gate electrode, making it possible to obtain a dRAM cell with a large capacity while reducing the size of the cell.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

Figure 1 is a plan view, Figures 2 (a) to (e) are the eight people'
It is a sectional view F or B, -B' sectional view.

First, a silicon nitride film (
21), and using this as a mask, the substrate is patterned in a checkered pattern.
etching. Then, ions of boron (I) (22) are formed on the bottom surface. Then, CVD5iQ
, to bury the field oxide film (13) flatly (
Figure 2 a).

The field oxide film (13) here is further etched over the entire surface, leaving only the bottom of the groove (12), and then the surface is thermally oxidized to form a thin oxide film (14), “Capacitor electrode buried flat with polycrystalline silicon (15)
(Figure 2b).

Thereafter, a resist mask having a rectangular opening CD) is provided, and using this resist mask and the silicon nitride film C21 as an etching mask, the protruding portion of the 1 μ wide capacitor electrode 09 is removed from a part of the memory cell boundary in the row direction.

At this time, the capacitor and electrode 09 are removed deeper than the surface of the substrate, and the arsenic film (14) appearing on the side wall of the substrate in the removed portion is removed by wet etching, and the boron is thermally diffused.
(23) is formed. And silicon nitride film (21)
is removed and the entire structure is thermally oxidized to form a gate oxide film (16). If the groove (L2) in the substrate is formed by taper etching, the thermal diffusion of boron can also be performed by boron ion implantation. Further, a polycrystalline silicon layer having a thickness of 1ζ5oooA is formed by CVD (vapor phase growth) method (FIG. 2C).

Then, reactive ion etching (Ig) is used to etch the entire surface of the polycrystalline silicon (n10 polycrystalline silicon width) to a thickness of 500 OA in one vertical direction. As a result, a frame-shaped gate self-aligned with the inner wall of the capacitor polarization (15) is connected to the pole 07) (word W
a> is formed integrally with the cells in the row direction, closing the capacitor removal portion. This self-aligned gate electrode (
Since the channel length of 17) is determined by the thickness of the grown n+ polycrystalline silicon (24), it is not affected by mask misalignment.

The O'' layer (25) is formed by ion implantation of K-ζ-3.Then, the entire surface is covered with a silicon oxide film (19) by CVD, a contact hole C is opened, and the A7 wiring (20) is formed.
' (bit lines) are formed in the column direction (Fig. 2d).

e).

Thus, according to this embodiment, the capacitor electrode width is defined by the groove width, and the gate electrode (17) is provided in close contact with the capacitor electrode (15), making it possible to reduce the size of the cell.

Further, in the above embodiment, the groove (12) provided in the field area
A p-layer (22) and a field M ('CM (13)) were provided at the bottom, but as shown in Fig. 3, a p-middle layer (32) was formed by thermal diffusion on the entire surface of the p''Si substrate (31), and then p7si+threat(
33) was epitaxially grown as a substrate, and 9
If ([2) is formed to reach p''lii (32), T6 can be done without needing these.Using a p medium-sized SM substrate fc p-1m (33) epitaxially grown, a p-substrate The groove (L2) may be formed in a different manner.

[Brief explanation of drawings]

Fig. 1 is a plan view explaining the present invention in detail, Fig. 2(a)
~(e) is a cross-sectional view of the process,! FIG. 8 in the figure, 11... Semiconductor substrate, 12... Camphor, 15... Capacitor electrode, 17... Gate electrode, 20... -Aj wiring. Representative Patent Attorney Kensuke Chika (and 1 other person) Figure 1 Figure 2 Figure 2 Figure 4

Claims (1)

[Claims] In a semiconductor memory device in which a capacitor electrode is formed in a trench provided in a field region of a semiconductor substrate surrounding a memory cell region, the capacitor electrode has a protrusion on the main surface of the substrate with substantially the same width as the trench; 1. A semiconductor memory device characterized in that a frame-shaped gate electrode is provided in self-alignment with an inner wall, and this gate electrode is integrally formed with a gate electrode of an adjacent memory cell through a cutout of the protrusion.