JPS6324657A - Manufacture of semiconductor memory - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor memory easily by etching Si by a method wherein, after forming multiple island regions in a semiconductor substrate, sidewalls of prospective MOS capacitor forming region of respective regions are exposed by etching island regions. CONSTITUTION:An oxide film 2 is formed on a p-type Si substrate 1; a photoresist 3 is pattern-formed in an island region to etch the film 2; first a field groove 4 is formed. Later, a p-type layer 5 for isolating element is formed on the bottom of this groove 4. Second, the resist 3 and the film 2 are removed to bury another oxide film 6 flatly in the groove 4. Third, another groove 8 is formed to expose the sidewalls and bottoms in a prospective sidewall capaci tor forming region. Fourth, an n-type layer 10 to be a substrate side electrode of MOS capacitor is formed. Successively, a capacitor part insulating film is formed to form a capacitor electrode 12. Through these procedures, a semicon ductor memory can be manufactured easily by Si etching process only without etching-back an in sulating film with a cell buried therein.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a process for forming a capacitor on a semiconductor substrate, and particularly to a method for manufacturing a semiconductor memory device having a memory cell structure of one transistor/one capacitor. .

(Prior Art) Conventionally, as a memory device formed on a semiconductor substrate, there is an MO8 type dynamic RAM (DRAM) in which a memory cell is configured by - MOS transistors and one MOS capacitor.
RAM) is known.

The biggest problem with the high integration and miniaturization of DRAM is
The problem is how to keep the capacitance of the MOS capacitor large while reducing the memory cell area. As a method of maintaining the capacitance of a MOS capacitor without increasing the area occupied by the memory cell, a structure has been proposed in which not only the upper surface of the memory cell region but also the side wall of the boundary with the field region is used as a MOS capacitor.

For example, IEDM'84 PP, 244. A FOLDE
D CAPA-CITORCELL (F, C, C,
) FORFUTURE MEGABITDRAMs, M
, Wada, ni, Hieda, and S, Watan.
abe.

Toshiba Corporation
aki, JAPAN. As a conventional means for realizing this structure, as shown in FIG. 9, insulating films 24 and 25 are buried flat in grooves 22 and 23 (FIG. 9(b)) formed in a semiconductor substrate 21 (FIG. 9(b)). C)), for example, when patterning the photoresist 26 in FIG.
d)).

Using this as a mask, any part of the insulating film 24 is buried.
The end side walls of each island region are exposed, leaving an oxide film 27 of a thickness necessary for element isolation. Thereafter, a first gate oxide film is formed by a well-known process, and then a capacitor electrode 28 is formed and patterned.

Form a transfer gate. The most difficult steps in this conventional process are from the step shown in FIG. 9(d) to the step shown in FIG. 9(e).
This is a process in which the buried insulating film corresponding to the step ) is etched, leaving a thickness necessary for element isolation.

That is, the problem in this case is that the capacitor forming surface 29 shown in FIG. 9(d) is inevitably partially exposed and damaged when etching the insulating films 24 and 25, resulting in deterioration of the charge retention characteristics of the cell. Also, it is difficult to control the thickness of the insulating film 27 shown in FIG. 9(e), and if the etching is done too much, element isolation will not be achieved and the DRAM will be a defective product, and if the etching is not done enough, the capacitor area on the sides of the trench end will be reduced. However, sufficient charge capacity cannot be obtained, which impairs the operating margin of the DRAM.

(Problems to be Solved by the Invention) The present invention has been made in view of the above-mentioned problems, and provides a structure in which not only the upper surface of the memory cell region but also the side wall at the boundary with the field region is used as a MOS capacitor. It is an object of the present invention to provide a method for easily manufacturing a cell having a cell structure without etching back an insulating film in which a cell is embedded.

[Structure of the invention]

(Means and effects for solving the problems) The present invention is directed to a structure in which not only the upper surface of the memory cell region but also the side wall at the boundary with the field region is used as a MOS capacitor. In the method of the present invention for obtaining such a structure, first, a plurality of island regions each having an insulating film embedded flatly around one periphery are formed in an array on a semiconductor substrate. Then, using the buried insulating film and the Si etching resistant film obtained by patterning as masks, Si is etched in the area around the area where the MOS capacitor is to be formed in each island area. Expose the side walls. A region where a gate electrode of a MOS transistor is to be formed and an insulating film around the region are continuously arranged across a plurality of island regions in one direction.

The Si island region is kept flat and flat without being etched. Then, MOS capacitor electrodes are formed on the side surfaces and top surfaces of the exposed island regions via insulating films, and gate electrodes of MOS transistors are formed on the top surfaces of each island region via gate insulating films.

According to the present invention, after forming a plurality of island regions in which insulating films are flatly embedded in a semiconductor substrate, the side walls of the M and 08 capacitor formation regions of each island region are exposed by Si etching of the island regions. , unlike the conventional method of etching the buried insulating film leaving the thickness of the insulating film necessary for element isolation and exposing the side walls of the MOS capacitor formation area of each island region, the insulating film is etched. This may cause device isolation to fail, or the insulating film may not be etched enough.
Problems such as insufficient capacitor capacity do not occur. Furthermore, since the upper surface of the island region where the capacitor is to be formed is covered with a mask, there is no fear that it will be removed by etching.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

Figures 1 (a), (b), (C) to Figure 7 (a)
), (b), and (C) are diagrams for explaining the manufacturing process of a dRAM according to an embodiment of the present invention. In these figures, (a) is a plan view, and (b) is its A-A
It is a li side view, and (C) is a perspective view. First, as shown in FIG. 1, an oxide film 2 is formed on a p-type Si substrate 1,
A photoresist 3 serving as an etching mask is patterned on the island region on which a memory cell will be formed by a known method, and the oxide film 2 is etched.First, a field groove 4 is formed by reactive ion etching (RIE). do. Thereafter, a p-type layer 5 for element isolation is formed at the bottom of the trench 4 by ion implantation or vapor diffusion. In this embodiment, the island area is formed by arranging two bits to form one convex rectangular pattern.

After that, the photoresist 3 and the oxide film 2 are removed, and as shown in FIG.
10, ) 6 is deposited by vapor phase epitaxy, and a photoresist 7 is further applied to flatten the surface. Then, the photoresist 7 and the oxide film 6 are etched by RIE with substantially the same etching speed ζ under the following conditions.
As shown in FIG. 3, an oxide film 6 is buried flatly.

Next, as shown in FIG. 4, a photoresist 7 is patterned to cover areas other than the area where the sidewall capacitor is to be formed and the surrounding field area, and the area where the sidewall capacitor is to be formed, which is a part of the Si island area, is filled with oxidation. Etching is performed using the film 6 and the resist 7 as a mask to form a groove 8 and expose the sidewall and bottom of the area where the sidewall capacitor is to be formed.

By forming the groove 8 shallower than the groove 4, element isolation is better achieved than when the groove 8 is deeper than the groove 4.

Next, as shown in FIG. 5, after removing the resist 7, the MO
A photoresist 9 covering the area where the S transistor is to be formed and the field area around it is patterned, and impurity ions are implanted to form an n-type NJ 10 that will become the substrate side electrode of the MOS capacitor. The thick oxide film 6 remains flatly buried in the field groove 4 around the region where the MOS transistor is to be formed. Subsequently, as shown in FIG. 6, a thermal oxide film with a thickness of, for example, 100 mm is formed as the capacitor part insulating film 11, and a first layer polycrystalline silicon film is deposited and patterned to form the capacitor electrode 1.
form 2. As is clear from the figure, the capacitor electrode 2 is not only located on the upper surface of the end of each island region, but also on the field groove 4.
Three side walls exposed at the boundary between the two sides are formed so as to face each other. After this, as shown in FIG.
For example, a thermal oxide film of xooi is formed on each island region as a
A gate electrode 14 is formed from a second layer polycrystalline silicon film. The gate electrode 14 is arranged continuously in the vertical direction in FIG. 7(a) so as not to overlap the capacitor electrode 12,
It becomes a word line. Then, using the gate electrode 14 and the capacitor electrode 12 as masks, impurities are diffused to form n-type layers 15 and 16 that will become the source and drain. Finally, as shown in FIG. 8, an element retention film 17 such as an oxide film (Sin) is formed on the entire surface by vapor phase growth, and a contact hole for wiring is opened in this to form a contact hole for the gate electrode 14. At wires 18 are formed in the intersecting direction to commonly connect the drains of the MOS transistors of the memory cells. This M wiring 18 becomes a bit line.

The dRAM according to this embodiment utilizes not only the flat surface of the convex memory cell region but also the side walls of the peripheral field trench 8 as a MOS capacitor, and effectively
The capacitor area is very large.

The present invention is not limited to the above embodiments.

For example, in the above embodiment, after a field trench was formed by etching the Si substrate, an oxide film was buried in the trench.

As a method of forming a plurality of island regions in such a manner that an insulating film is embedded around the island regions, a first step may be employed. That is, first, a thick insulating film is selectively formed in a convex pattern in the field region of the Si substrate. After depositing an insulating film on the entire surface by CVD, this is
It may be etched using IE or the like. Thereafter, a Si layer is selectively grown on the exposed surface of the Si substrate to a thickness similar to that of the insulating film. As a result, a flat substrate equivalent to that of the above embodiment can be obtained.

The pond water invention can be modified in various ways without departing from its spirit.

〔Effect of the invention〕

According to the present invention, the difficult process of etching back the insulating film in which the cell is embedded, which has a structure in which not only the upper surface of the memory cell region but also the side wall of the boundary with the field region is used as a MOS capacitor, leaving a certain thickness. Without, S
DRAM can be easily manufactured by only etching the embedded insulating film, and is caused by variations in cell capacitance and variations in element isolation ability caused by variations in the thickness of the insulating film left after etching back the buried insulating film. performance deterioration can be suppressed.

[Brief explanation of drawings]

FIGS. V to 8 are structural explanatory diagrams for explaining the manufacturing process of a DRAM according to an embodiment of the present invention, and FIG. 9 is a cross-sectional explanatory diagram showing the conventional manufacturing process. DESCRIPTION OF SYMBOLS 1...p-type Si substrate, 2...oxide film, 3...photoresist% 4...field trench, 5...p-type layer, 6...oxide film S7... Photoresist, 8.
...Groove formed in Si island region, 9...Photoresist, 10...n-type layer. DESCRIPTION OF SYMBOLS 11... Capacitor insulating film, 12... Capacitor electrode, 13... Gate insulating film, 14... Gate electrode (
15.16...n-type layer, 17...element protective film, 18...AA wiring (bit line). Agent Patent Attorney Nori Ken Yudo Chika Kikuo Takehana (a) tIE1 (c) Figure 1 (a) Figure 2 (C) (a) (c) Figure 3 (a) Figure 4 (λ) (b) (b) (a) (b) @Figure 7 (a) Figure 8

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor memory device having a memory cell structure of one transistor/one capacitor, which includes the steps of: forming a plurality of island regions in which an insulating film is flatly embedded in a semiconductor substrate; and the island region. A step of etching a portion of the insulating film in a self-aligned manner to the side of the buried insulating film to expose the end sidewalls of each island region, and etching a first gate oxide film so as to cover the sidewalls and top surface of each exposed island region. 1. A method of manufacturing a semiconductor memory device, comprising the step of forming a MOS capacitor electrode through a step of forming a MOS capacitor electrode. (2) The method of manufacturing a semiconductor memory device according to claim 1, wherein the etching depth of the island region is shallower than the depth of the buried insulating film.