JPS592362A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase the capacitance of a capacitor while reducing a plane area of the capacitor by forming the capacitor to the side surface of a groove formed to a predetermined section on a substrate and forming an insulating film for isolation to the bottom of the groove. CONSTITUTION:A pad silicon oxide film 203 on the bottom 82 of the groove is removed through etching, a silicon oxide film 41 is formed only onto the bottom 82 of the groove through selective oxidation in wet oxygen while using silicon nitride films 72, 74 as masks, and the silicon nitride films 72, 74 and pad silicon oxide films 202, 203 are removed through etching. As a result of a series of said processes, the groove 10 with the thick silicon oxide film 41 for isolation is formed onto the bottom. A silicon oxide film 21 is formed to the whole surface as an insulating film for the capacitor, and a substance such as phosphorus doped polycrystalline silicon 31 is deposited so as to completely fill the groove 103 as a conductor thin-film and patterned, thus forming the phosphorus doped polycrystalline silicon 31 only to a desired section.

Description

[Detailed Description of the Invention] Inventively N4cMOS isolated by an insulator at the trench bottom N5rc
The present invention relates to a #p conductor device having a capacitor and a method for manufacturing the same.

For example, in a dynamic random access memory (hereinafter abbreviated as -1ITr type dRAM) that is composed of a cell consisting of one transistor and one capacitor, a large number of capacitors that are electrically isolated from each other are formed on a semiconductor substrate. Is it necessary? 0Here, we will explain the structure of the ITr type dRA VI cell and its manufacturing method, with emphasis on the capacitor 8.0 A plan view and A-A of the cell part of the ITr type dRAM manufactured using conventional technology. Cross-sectional views taken along the line are shown in Figure 1 u) and (b). In the following explanation, it is assumed that the MOS transistor is an n-channel type.

Even in the case of the p-channel type, the conductivity type of the source train diffusion layer and channel stopper, which will be described later, is completely the same except that the conductivity type is transparent.

In FIG. 1 U), the region surrounded by broken lines is composed of one transistor and one capacitor. The d capacitor formed by the l memory cell is insulated from the p-type silicon substrate 1 by T4-thin II! 12 and a conductive thin film 3. The insulator thin film 2 has a thickness of lOO~500A,
By thermally oxidizing the silicon substrate! A silicon oxide film or a silicon nitride film formed by a chemical vapor deposition method (hereinafter abbreviated as CVD method) or the like is used. Is it an impurity such as phosphorus for the conductor thin film 3? Metals such as doped polycrystalline silicon TFCU aluminum, molybdenum, etc. are used. Further, a very thick silicon oxide film 4 is provided between different capacitors, and a channel stopper region 11 is provided in one of the capacitors for electrical isolation. MO8F'ET adjacent to the capacitor has ♂ diffusion r@lO>↓ which becomes the source/drain, a gate insulating film 20 and a gate electrode (word'[1l) 30↓
9 losses. After the bit line 6 is formed via the interlayer insulating film 5, the diffusion layer 1OVc is in contact with the diffusion layer 1OVc from the through hole 1000 area.

Next, as shown in FIG. 2 and below, a pad silicon oxide 11i200 layer is deposited on the silicon substrate 1 as shown in FIG. 2 and below. Then, the silicon nitride film 7o with a thickness of 1000λ was completely destroyed by CVD, and then the silicon nitride film 7o was patterned using a mask. r: Etching is removed and silicon nitride film 70 is etched only on the element region 81, and a bad silicon oxide film 200 is removed.
Take it from the laminating machine so that it remains.

Next, a p-type impurity such as boron is ion-implanted into the turned resist 111k mask, and heat treatment is performed to form a channel stopper region 11 with a high substrate concentration of gold on the surface between the isolation regions.

Next, the Bc laminated T mask shown in Figure 3 is oxidized (hereinafter V-
By performing selective oxidation (called selective oxidation), a thickness of 70,005. Four opposing silicon oxide films are formed. Next, the silicon nitride film 7o (3) and the silicon oxide film 200' are removed by etching to expose the entire surface of the silicon substrate 1 above the active region 81.

Next, as shown in FIG. 4, two silicon oxide films are formed on the vc1 element region 81 as insulating thin films for the capacitor, for example by thermal oxidation. Furthermore, an example of a conductive thin film is Lintalk's polycrystalline silicon 3'? r is deposited and subjected to buttering. below.

After forming a gate insulating film to form the structure shown in FIG. 1, a vaporized layer of molybdenum, for example, is patterned to form a gate electrode 30, and then a conductive thin film @3 and a gate electrode 30 are formed. into a mask.

By ion-implanting n-type impurities such as arsenic and applying heat treatment! lln+diffusion layer lO is formed. Next, after forming 5 interlayer insulating films and forming 1000 through holes, a bit #6ffi is formed by vaporizing and buttering, for example, aluminum.
The method of forming RAM was used. In order to increase the cylindrical density of the device, it is effective to make the capacitor area smaller. However, in a structure like (4) shown in Figure 1, if the total area of the capacitor region is reduced, the capacitance will decrease, so the storage current will increase in VV and noise. The disadvantage is that there is less margin for etc. Further, during selective oxidation, oxidation progresses to the capacitor forming region, forming a so-called bird's beak, making it difficult to miniaturize the isolation portion.

Furthermore, since a surface level difference is formed between the separation part and the capacitor, there is a drawback that electrodes and wiring are easily disconnected.

In order to eliminate all of these drawbacks, the present invention forms a capacitor on the side surface of a groove formed in the bottom part of the semiconductor substrate, and forms an insulating film for isolation at the bottom of the groove.
The purpose of this is to make it possible to increase the valley tt of the capacitor and to reduce the planar area of the Ic capacitor.

In order to achieve the above object, the present invention provides a semiconductor device having at least two or more capacitor groups, in which a hook region vc included in glIITIiJ' of at least one groove formed in an auxiliary neck region of a main surface of a semiconductor substrate is provided. The gist of the invention is a semiconductor device characterized in that a capacitor is formed and a region electrically isolated from the bottom of the trench is destroyed.

The present invention includes a step of forming a groove in a predetermined region of the main surface of a semiconductor substrate, forming a first insulating film in the groove area including at least the side surface of the groove, and forming a second insulating film at the bottom of the groove.・By forming a conductive thin film on the first insulating film, two or more capacitors are electrically isolated at the bottom of the groove, at least in the groove. The gist of the invention is a method of manufacturing a semiconductor device characterized by including a step of forming a region including a side surface.

Next, the accompanying drawings of the uninvented embodiments will be explained.

It should be noted that the embodiments are merely illustrative, and we reserve the right to make any changes or improvements without departing from the spirit of non-invention.

A description will be given of a case in which an ITr type d RAM cell vci using the capacitor/separation combined structure is implemented by implementing the capacitor structure and its manufacturing method according to the uninvented method 151,111 and 2 by 113tIc.

(Example 1) As shown in FIG.
A bad silicon oxide film 201 is formed by thermal oxidation on the p-type (specific resistance: 2 to 5 ncrn), a silicon nitride film 71 is formed by CVD method, and a resist 9 subjected to rC patterning is formed thereon.

Next, as shown in FIG. 6, using the resist 9 as a mask, a silicon nitride film 71. The groove 100 is completely formed by etching the silicon oxide film 201 and the silicon substrate. For the above-mentioned etching, a highly anisotropic etching method is used, for example, a semi-rectangular plate electrode type plasma etching apparatus or a reactive sputter etching apparatus [k].

Next, as shown in FIG. 7, after removing the VCl resist 9, thermal oxidation is performed using silicon nitride 1la 72 as a mask.
A pad silicon oxide film 203 is formed only on the inner surface of the key 100, and a silicon nitride film 73 (7) is further formed on the entire main surface including the inner surface of the p key, for example, by CVD. Here, the groove VC 101 with the silicon nitride film 73 formed on its inner surface is etched.Next, as shown in FIG.
Step 9 is to etch the C-p silicon nitride film 73', leaving the silicon nitride film 74 only on the groove surface of the groove 101.
Here, the silicon nitride film 74 is formed only on the 911 plane, and the symbol 102 is formed on the fc groove.
■Ion implantation with a size of 4 x 10"m and heat treatment for 30 minutes at 100°C in nitrogen to form a sieve region with a p-type impurity concentration, that is, a channel stop bulge, near the surface of the Kj9 groove bottom surface 82. -11 is formed.Next, after etching and removing the pad silicon oxide film 203 on the p-groove bottom surface 82 with a buffered hydrofluoric acid solution, as shown in FIG.
c1 Use the silicon nitride film 72 and the cut 74 as a mask.

Selective oxidation is carried out at 1000° C. in a moist Li&O layer to destroy the silicon oxide film 41 with a thickness of 0.3 to 1/Jm on the bottom surface 82 of the groove 1, and then a silicon lid is formed. 72 Work 74. Then, the silicon oxide films 202 (8) and 203 are removed by etching. As a result of the above series of steps, a trench 103 having a thick silicon oxide film 41 for isolation only at the bottom is formed. Next, as shown in FIG. 1O, a silicon oxide film 21 is formed as a capacitor insulating film by thermal oxidation, for example, by thermal oxidation.
Vc is formed, and then, as a conductive thin film, for example, lind polycrystalline silicon 31 is deposited so as to completely fill the groove 103'i, and by patterning, rind polycrystalline silicon is formed only in desired areas. I agree with Silicon 31.

Above, as Example 1, the method of forming 8 m of isolation insulation at the bottom of the trench using selective oxidation and forming a capacitor in the area including at least the side surfaces of the trench has been explained. Next, as Example 2, A method of forming an isolation insulating film at the bottom of a trench using a method of burying an insulator into a trench will be described.

(Example 2) First, as shown in FIG.
According to the method, a silicon oxide film is formed on a silicon substrate 1, and the silicon oxide film and the silicon substrate 1 are etched using a patterned resist as a mask.
l Silicon oxide film 42 and groove 100 [groove width (0.5 μm
<W≦1.2/un).

Groove depth d (1,0/jm≦d<5.OPtn)]
k form.

Note that the one-line etching VC uses the highly anisotropic etching method described in the first embodiment. Next, boron is ion-implanted as a channel stopper using the silicon oxide film 42 as a mask under the conditions described in Example 1, and heat-treated to form a P-type impurity concentration on the bottom surface 82 of the trench 100. A high area channel stopper 11 is formed. Next, as shown in FIG. 12, the silicon oxide film 42 is removed by etching using a buffered hydrofluoric acid solution and a pad oxide film 204 is formed on the entire surface by thermal oxidation. An example of a silicon dispersion film method other than thermal oxidation of silicon is a substrate temperature of 700 to 90°C.
At 0°C, the thickness t/j was measured by CVD using silane (St) I, carbon dioxide (CO) and hydrogen (H).
m(0,5W≦t≦W) As shown in FIG. The total thickness of silicon oxide film tox (0,3-s tox < 1
．． 0, however, toX leaves a small amount of light for d processing,
Add a number 44 to the silicon oxide film. At this time, a portion of the butt silicon oxide film 204 is also etched, leaving the butt silicon oxide film 205 only between the silicon oxide film 44 and the silicon substrate l. Silicon oxide film 44 on the bottom
What number i04 is 0 or more in the groove in which the 14th mark is formed?
r As shown, the capacitor insulating film 21 and the conductor thin film 31 are formed by the same process as in Example 1. The case where AklTr type dRAM (/J cell part r is applied) will be explained.

(Embodiment 3) FIGS. 15(a) and 15(b) show a half view and a cross section, respectively, of a memory cell using the groove-type capacitor S structure according to the invention. The cross-sectional view (b) is taken along the line A-A' in the plan view (a) (11). In the plan view (A), the trtfC, ta area surrounded by broken lines is one unit of a cell consisting of one transistor and one capacitor.

A through hole 10 is formed in the n+ expansion M layer 10 at the center of the cell.
Bit 6 is connected via 00. Word @32 is formed so as to surround 1000 through holes. The peripheral VC of the cell was formed by the method described in Example 1 or 2. A groove capacitor isolation combination structure is provided.

As explained above, according to the invention, one semiconductor substrate #11 is formed, the groove bottom yc isolation part is formed, and the capacitor is formed on the groove side surface, so that the separation capital and the capacitor part in the semiconductor device are formed. There is an advantage that miniaturization can be carried out at the same time. In addition, in Example IVc, the bird's beak formed by selective oxidation is formed vertically in the groove 11tllifl, so the separation area is reduced as when using the conventional technique. It will not bring about an increase in the number of people. In Embodiment 2, there is no problem with bird's beak because the single-selective oxidation method is not used.The above-mentioned groove (12) is filled with a conductive thin film at the end (12) and is separated from the capacitor section. The problem of the difference in surface level between the capitals has also been resolved.

The invention can be used for the memory cell part of ITr type dRAM,
In this case, the planar area of the capacitor section on the substrate can be reduced to a fraction of that of the substrate without changing the capacitance, which has the effect of greatly contributing to the miniaturization of the memory cell section.

[Brief explanation of the drawing]

Figure 1 @) and (b) are I Tr manufactured by conventional technology.
In the partial structural diagrams of a type D RAM cell, (a) is a plan view, (b) is a sectional view taken along the line A-A' in (a), and Figs. 2 to 4 show the manufacturing method according to the conventional technology. 5 to 1θ are process diagrams to explain the manufacturing method (Example 1) based on the non-inventive r, and FIGS. Figure 15 is a partial structural diagram of the memory cell of the ITr type d RAM (Example 3) manufactured using the Uninventive Society, and (A) is a half-plane diagram for explaining 2). Figure, (b) is (
b) A sectional view taken along line A-A' at r. ■...Silicon substrate, 2...Insulating film for capacitor, 3...Polycrystalline silicon, 4...
...Silicon oxide film, 5...Interlayer insulating film, 6
...Bit 11! , 9... Resist, IO・
... Diffusion layer, 11 ... Channel stopper, 20 ... Kate insulating film, 21 ...
・Insulating film for capacitors, silicon insulating film, 30...
...Gate electrode, 31...Conductor thin film%32...
...Word line, 41-45...Silicon acid (I
JI, 7o~77...Silicon nitride film, 80.
. . . Inter-element isolation region, 81 . . . Element region, 82 . . . Bottom surface of capacitor isolation groove, 83.
...Groove separation chain acid, 100-104 ...Groove%
111...Resist, 200-209...
...Pad silicon oxide film, 1000 ...Through hole patent applicant 1 Telegraph and Telephone Corporation (15)

Claims (1)

[Claims] (1) In a semiconductor device having at least two or more capacitors, a region VC chiyabashita is formed including the side surface of at least one trench formed in the PJI foot region of the main surface of the semiconductor substrate, and the bottom of the trench A semiconductor device characterized in that a region electrically isolating the capacitor is formed in the semiconductor device 0 (2) A groove is formed in the 19T foot region of the main surface of the semiconductor substrate, and a region that meets at least the side surfaces of the ridge groove. A step of forming a first insulating film on the bottom of the groove, a step of forming a second insulating film on the bottom of the groove, and a step of forming a conductive thin film in the entire shape Fy, "j" by laminating it on the first insulating layer. 2. A method for manufacturing a semiconductor device, comprising: forming a surface area V including at least two or more capacitors t1 electrically isolated at the bottom of the groove.