KR950012551B1 - Structure of dram cell and manufacturing method thereof - Google Patents
Structure of dram cell and manufacturing method thereof Download PDFInfo
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- KR950012551B1 KR950012551B1 KR1019920010357A KR920010357A KR950012551B1 KR 950012551 B1 KR950012551 B1 KR 950012551B1 KR 1019920010357 A KR1019920010357 A KR 1019920010357A KR 920010357 A KR920010357 A KR 920010357A KR 950012551 B1 KR950012551 B1 KR 950012551B1
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- dram cell
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Abstract
Description
제1도는 종래의 스택형 디램 셀 구조 단면도.1 is a cross-sectional view of a conventional stacked DRAM cell structure.
제2도는 종래의 트랜치형 디램 셀 구조 단면도.2 is a cross-sectional view of a conventional trench type DRAM cell structure.
제3도는 본 발명의 디램 셀 공정 단면도.3 is a cross-sectional view of a DRAM cell process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
17 : 기판 18, 23 : CVD 산화막17 substrate 18, 23 CVD oxide film
19 : 실리콘 20 : 게이트19 silicon 20 gate
21 : 정션 22 : 비트라인21: junction 22: bit line
24, 26 : 폴리실리콘 25 : 유전체24, 26 polysilicon 25 dielectric
본 발명은 디램(DRAM) 소자에 관한 것으로, 특히 64메가 디램급에 적당하도록 한 디램 셀 구조 및 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to DRAM devices, and more particularly, to a DRAM cell structure and a manufacturing method suitable for a 64 mega DRAM class.
종래의 스택(Stack)형 디램 셀 제조방법은 제1도에 도시한 바와 같이 기판(1)에 필드 영역과 액티브 영역을 한정하여 필드 영역에 채널 스톱이온을 주입한 후 필드산화막(2)을 성장시킨다.In the conventional stack-type DRAM cell manufacturing method, as shown in FIG. 1, the field oxide layer 2 is grown after the channel stop ion is injected into the field region by defining the field region and the active region in the substrate 1. Let's do it.
그리고 게이트산화막(3)과 게이트 폴리실리콘 및 캡산화막(5)을 차례로 증착하고 포토/에치 공정에 의해 액티브 영역과 필드산화막(2)위에 각각 게이트(4)를 형성한 후 소오스/드레인 영역 형성을 위한 저농도 n-이온을 주입한다.After the gate oxide film 3 is deposited, the gate polysilicon and the cap oxide film 5 are sequentially deposited, and the gate and drain regions are formed on the active region and the field oxide layer 2 by photo / etch processes, respectively. Inject low concentrations of n - ions.
그다음 전면에 산화막(6)을 증착하고 이를 식각하여 게이트측벽(6)을 형성한 후 고농도 n-이온주입하여 LDD(Lightly Doped Drain) 구조를 갖는 소오스/드레인을 형성한다.Then, an oxide film 6 is deposited on the entire surface and etched to form a gate sidewall 6, and then a high concentration n − ion is implanted to form a source / drain having a lightly doped drain (LDD) structure.
이어서 전면에 산화막(7)을 증착하고 메몰콘택(Burried Contact)형성을 위해 산화막(7)을 포토/에치한다.Subsequently, an oxide film 7 is deposited on the entire surface, and the oxide film 7 is photo / etched to form a burried contact.
그후 스토리지 노드 도핑된 폴리실리콘(8)과 커패시터 유전체막(9) 및 플레이트 노드 폴리실리콘(10)을 차례로 형성하고 포토/에치 공정으로 불필요한 부분을 제거함으로써 커패시터를 형성한다.Then, the capacitor is formed by sequentially forming the storage node doped polysilicon 8, the capacitor dielectric layer 9, and the plate node polysilicon 10, and removing unnecessary portions by the photo / etch process.
그리고 표면에 표면평탄화용 SOG(Spin On Glass)(11)를 증착하고 액티브 영역의 게이트 사이에 포토/에치 공정으로 비트라인 콘택을 형성한 뒤 전면에 비트라인을 형성한다.Then, the surface flattening SOG (Spin On Glass) 11 is deposited on the surface, a bit line contact is formed between the gates of the active region by a photo / etch process, and then a bit line is formed on the front surface.
제2도 종래 트랜치(trench)형 디램 셀의 구조를 단면으로 나타낸 것으로 기판(13) 내부에 트랜치를 파고 트랜치에 커패시터를 제조한 후 커패시터 사이의 기판(13) 표면에 게이트(14)와 정션(15)을 형성하여 트랜지스터를 형성하여 게이트(14) 사이의 정션(15)에 이어지도록 비트라인(16)을 형성하였다.FIG. 2 is a cross-sectional view of a structure of a conventional trench type DRAM cell, and a trench is formed in the substrate 13 and a capacitor is manufactured in the trench, and then the gate 14 and the junction (14) are formed on the surface of the substrate 13 between the capacitors. 15 was formed to form a transistor to form a bit line 16 to follow the junction 15 between the gates 14.
그러나 상기와 같은 종래의 스택형 디램셀의 구조 및 제조방법에 있어서는 공정이 복잡하여 제조하기가 어렵고 셀 면적을 극소화시켜야 하는 현실에 부응하기가 어려운 결점이 있고 트랜치형 디램 셀에 있어서는 비교적 공정은 단순하나 기판(13)에 트랜치를 파고 셀을 제조하므로 누설(leakage) 특성이 약해지기 쉬운 결점이 있다.However, in the structure and manufacturing method of the conventional stack type DRAM cell as described above, it is difficult to manufacture due to the complicated process, and it is difficult to meet the reality of minimizing the cell area, and the process of the trench type DRAM cell is relatively simple. However, since the trench is manufactured by digging a trench in the substrate 13, a leakage characteristic is liable to be weakened.
본 발명은 이와 같은 종래의 결점을 해결하기 위한 것으로 공정을 단순화한 디램 셀의 구조 및 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above-mentioned drawbacks and to provide a structure and a manufacturing method of a DRAM cell which simplifies the process.
이하에서 이와 같은 목적을 달성하기 위한 본 발명의 실시예를 첨부된 도면을 참고로 하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.
제3도는 본 발명의 공정 단면도로 먼저 제3a도와 같이 기판(17)위에 절연을 위한 제1CVD 산화막(18)을 형성하고 그 위에 액티브 영역으로 사용하기 위한 실리콘(19)을 형성한다.3 is a cross-sectional view of the process of the present invention, first forming a first CVD oxide film 18 for insulation on a substrate 17 as shown in FIG. 3A, and then forming silicon 19 for use as an active region thereon.
그리고 제3b도와 같이 실리콘(19)을 에치하여 액티브 영역을 한정한다.As shown in FIG. 3B, the silicon 19 is etched to define the active region.
다음에 제3c도와 같이 상기 실리콘(19)위에 게이트(20)을 형성하고 N+이온주입에 의한 정션(21)을 형성한다.Next, as shown in FIG. 3C, the gate 20 is formed on the silicon 19, and the junction 21 by N + ion implantation is formed.
이어서, 제3d도와 같이 비트라인(22)을 형성하고 절연을 위한 제2CVD 산화막(23)을 두껍게 증착한다.Subsequently, as shown in FIG. 3D, the bit line 22 is formed and the second CVD oxide film 23 for the insulation is deposited thickly.
다음에 제3e도와 같이 제1, 제2CVD 산화막(18)(23)과 실리콘(19)에 걸쳐 기판(17)표표면까지 에치하여 콘택홀을 형성한다.Next, as shown in FIG. 3E, contact holes are formed by etching the first and second CVD oxide films 18 and 23 and silicon 19 to the surface of the substrate 17. FIG.
또한, 제3f도와 같이 전표면에 스토리지노드용 폴리실리콘(24)을 형성하여 패터닝(patterning)하고 유전체(25)를 형성한 후 플레이트용 폴리실리콘(26)을 형성한다.In addition, as shown in FIG. 3F, the polysilicon 24 for the storage node is formed and patterned on the entire surface, and the dielectric 25 is formed to form the polysilicon 26 for the plate.
이상에서 설명한 바와 같이 본 발명은 제1CVD 산화막(18)위에 실리콘(19)을 이용한 액티브 영역을 형성하여 셀간 격리를 위한 필드산화 공정이 필요없어져 공정이 용이해지고, 격리 효과도 향상시킬 수 있다.As described above, the present invention forms an active region using silicon 19 on the first CVD oxide film 18, eliminating the need for field oxidation for inter-cell isolation, thereby facilitating the process and improving the isolation effect.
또한, 액티브 영역의 실리콘(19) 두께로 정션 깊이 조절이 용이하고 두꺼운 제1CVD 산화막(18)으로 기판(17)과 액티브 영역을 격리시키므로 기판(17)으로의 전류 누설이 전혀없으며, 구조상 스토리즈 노드간도 모두 산화막으로 격리되어 있어 셀간 누설도 거의 없게 된다.In addition, the junction depth can be easily controlled by the thickness of the silicon 19 in the active region, and the first 17 oxide layer 18 is used to isolate the substrate 17 from the active region, so that there is no current leakage to the substrate 17. All the livers are separated by an oxide film, and there is almost no leakage between cells.
또한, 구조상 깊은 트랜치 형상의 커패시터 제조가 가능하여 충분한 커패시턴스를 얻을 수 있는 효과가 있다.In addition, it is possible to manufacture a deep trench-shaped capacitor in the structure, there is an effect that can obtain a sufficient capacitance.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920010357A KR950012551B1 (en) | 1992-06-15 | 1992-06-15 | Structure of dram cell and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920010357A KR950012551B1 (en) | 1992-06-15 | 1992-06-15 | Structure of dram cell and manufacturing method thereof |
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| Publication Number | Publication Date |
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| KR940001395A KR940001395A (en) | 1994-01-11 |
| KR950012551B1 true KR950012551B1 (en) | 1995-10-18 |
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| KR1019920010357A KR950012551B1 (en) | 1992-06-15 | 1992-06-15 | Structure of dram cell and manufacturing method thereof |
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