JP2661357B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a trench capacitor.

[Conventional technology]

As a conventional technique for forming a trench capacitor in a method of manufacturing a semiconductor device, a formation method described below can be given.

First, as shown in FIG. 3A, a field oxide film 2 for element isolation is formed on a P-type silicon substrate 1 by a LOCOS method. Then, grooves 3-1 and 3-2 are formed in the element formation region partitioned by the field oxide film 2, and a capacitance insulating film 4 such as silicon oxide is formed on the inner walls of the grooves 3-1 and 3-2 and on the substrate surface. Form. Further, a capacitor polysilicon film 5 is formed on the capacitor insulating film 4 as a capacitor electrode. In order to reduce the resistance of the capacitance polysilicon film 5, phosphorus diffusion is performed in a POCl ₃ atmosphere to remove the phosphorus glass on the capacitance polysilicon film 5, thereby obtaining a structure as shown in FIG.

Next, a silicon oxide film 9 is formed on the capacitance polysilicon film 5 as shown in FIG.

Next, as shown in FIG. 3C, the trenches 3-1 and 3-2 and the buried polysilicon film 7 are formed on the wafer surface to fill the trenches.

Next, as shown in FIG. 3 (d), the entire surface of the wafer is uniformly and isotropically etched using a wet etching technique to remove the buried polysilicon film 7 other than inside the groove. Here, the silicon oxide film 9 serves as a protective film for the polysilicon film 5, and furthermore, the buried polysilicon film 7-
It is also a guide for the remaining etching of 1,7-2. Finally, as shown in FIG. 3 (e), an interlayer oxide film 8 is formed to provide insulation between the capacitance polysilicon film 5 and the gate of the driving transistor formed in a later step. . Each time several heat treatments are applied until the device is completed, oxygen is thermally diffused from the interlayer oxide film to the capacitance polysilicon film and the buried polysilicon film, and the polysilicon is oxidized. Here, in particular, since the capacitor polysilicon film is phosphorus-doped, it is accelerated and oxidized, and the wedge-shaped silicon oxide film 11-1,
11-2,11-3,11-4 are formed.

[Problems to be solved by the invention]

In this conventional method of manufacturing a semiconductor device, oxygen is removed from the interlayer insulating film at the stage of forming the interlayer oxide film and every time several heat treatments are performed until the device is completed. Thermal diffusion into the polysilicon film occurs. In particular, when the capacitance polysilicon film and the buried polysilicon film in the groove opening are oxidized, volume expansion occurs only in that portion, and a stress acts in a direction to widen the groove opening. In the case of a very strained groove, a defect occurs in the silicon substrate in the opening. Then, this defect causes a leakage current, and there is a problem that it is difficult to hold the charge.

In addition, there is a problem in that the portion of the capacitive polysilicon film deposited other than in the groove, which is in contact with the interlayer oxide film, is oxidized and thinned, and the resistance as a capacitive electrode increases.

[Means for Solving the Problems] In a method for manufacturing a semiconductor device according to a first aspect of the present invention, an insulating region for element isolation is formed on a surface portion of a semiconductor substrate to divide an active region, and a groove is formed in the active region. Forming, forming a capacitive insulating film on the inner wall of the trench and on the substrate surface, forming a capacitive polysilicon film on the capacitive insulating film, and forming a silicon nitride film on the capacitive polysilicon film. Forming a buried polysilicon film on the silicon nitride film to fill the groove, removing the buried polysilicon film from a portion other than the inside of the groove, Forming an interlayer insulating film on the buried polysilicon film on the surface.

The method of manufacturing a semiconductor device according to the second aspect of the present invention may further comprise forming an insulating region for element isolation on a surface portion of the semiconductor substrate to partition an active region, forming a groove in the active region, and forming an inner wall of the groove. Forming a capacitive insulating film on the surface of the substrate, forming a capacitive polysilicon film on the capacitive insulating film, and forming a silicon oxide film on the capacitive polysilicon film;
Forming a buried polysilicon film on the silicon oxide film to fill the trench, removing the buried polysilicon film from a portion other than the inside of the trench, Forming a silicon nitride film on the buried polysilicon film, and forming an interlayer insulating film on the silicon nitride film.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIGS. 1 (a) to 1 (e) are cross-sectional views of a semiconductor chip for explaining an embodiment of the first invention of the present application, in the order of steps.

First, as shown in FIG. 1 (a), the specific resistance is 5Ω · cm,
A field oxide film 2 for element isolation having a thickness of 500 to 700 nm on a P-type silicon substrate 1 having a plane orientation of (100) by the LOCOS method.
To form Then, a groove 3 having a depth of 3.5 to 4.0 μm and a width of about 1 μm is formed in the element formation region partitioned by the field oxide film 2.
-1,3-2 are formed, and a capacitive insulating film 4 of silicon oxide or the like is formed on the inner walls of the grooves 3-1 and 3-2 and on the substrate surface to a thickness of about 6 nm. Further, a capacitor polysilicon film 5 having a thickness of 230 to 270 nm is formed on the capacitor insulating film 4 as a capacitor electrode. In order to lower the resistance of the capacitive polysilicon film 5, heat treatment is performed in a POCl ₃ atmosphere at 800 to 900 ° C. for about 40 minutes to diffuse phosphorus. When the phosphorus glass on the capacitance polysilicon film 5 is removed, a structure as shown in FIG. 1A is obtained.

Next, as shown in FIG.
A 20 to 40 nm silicon nitride film 6 is deposited thereon by using the CVD method.

Next, as shown in FIG. 1 (c), a non-doped buried polysilicon film 7 for filling in the trench is deposited to a thickness of 700 to 900 nm on the trenches 3-1 and 3-2 and on the wafer surface. At this stage, grooves 3-1 and 3-
It is important to fill 2 with a buried polysilicon film without gaps.

Then using a wet etch techniques as shown in FIG. 1 (d), the entire surface of the wafer surface, performs equally isotropic etching by HF-HNO ₃ based etchant, other than the groove buried poly The silicon 7 is removed, and buried polysilicon films 7-1 and 7-2 are formed inside the trench. Here, silicon nitride film 6
Serves as a protective film for the capacitance polysilicon film 5 and also serves as a measure of the remaining etching of the buried polysilicon film 7 other than the groove portion visually.

Finally, as shown in FIG. 1 (e), the interlayer oxide film 8 is formed to a thickness of 120 to 1 in order to provide insulation between the capacitor polysilicon film 5 and the gate of the driving transistor used in a later step.
Deposit 80 nm.

The semiconductor substrate undergoes various thermal oxidation steps in the semiconductor device manufacturing process after the capacitor forming process. However, the capacitor polysilicon film is oxidized due to the presence of the silicon oxide film 6 having high oxidation resistance on the capacitor polysilicon film. However, wedge-shaped oxidation at the interface between the buried polysilicon film and the capacitor polysilicon film in the groove opening, which is seen in the prior art, is prevented, and no stress acts in the direction of opening the groove. Further, the capacitance silicon film other than the groove is not oxidized, and the resistance does not increase as a capacitance electrode.

2 (a) to 2 (e) are sectional views for explaining an embodiment of the second invention of the present application. The difference from the above-described embodiment is that a silicon nitride film for preventing oxidation of the capacitance polysilicon film is not grown on the capacitance polysilicon film, but a silicon oxide film is formed on the capacitance polysilicon film, and silicon nitride for preventing oxidation is formed. Forming a film on the buried polysilicon film.

First, a field oxide film, a trench, a capacitor insulating film, and a capacitor polysilicon film are sequentially formed in the same manner as described with reference to FIG. 1A, and phosphorus diffusion is performed to remove phosphorus glass.

Next, as shown in FIG. 2A, a silicon oxide film 9 is deposited on the capacitance polysilicon film 5 to a thickness of about 40 nm by the CVD method.

Next, as shown in FIG. 2 (b), the grooves 3-1 and 3-2
And a non-doped buried polysilicon film 7 on the wafer surface
Is deposited to fill the grooves 3-1 and 3-2.

Next, as shown in FIG. 2 (c), using a wet etch techniques, the entire surface of the wafer surface, subjected to uniform isotropic etching by HF-HNO ₃ based etchant, buried except the groove The buried polysilicon film 7 is removed to leave buried polysilicon films 7-1 and 7-2 inside the trench. Here, the silicon oxide film 9 serves as a protective film for the capacitance polysilicon film 5,
In addition, it serves as a guide for visually checking the remaining portion of the buried polysilicon film 7 other than the groove portion.

Next, as shown in FIG. 2D, a silicon nitride film 10 is deposited to a thickness of 20 to 40 nm on the silicon oxide film 9 and the buried polysilicon films 7-1 and 7-2 exposed on the surface.

Next, as shown in FIG. 2E, an interlayer oxide film 8 is deposited on the silicon nitride film 10 to a thickness of 120 to 180 nm. According to this embodiment, the oxidization of the buried polysilicon films 7-1 and 7-2, which could not be prevented in the first invention, can be suppressed, and the prevention of volume expansion at the groove opening can be further ensured. .

〔The invention's effect〕

As described above, the present invention forms a silicon nitride film between a capacitive polysilicon film and an interlayer insulating film,
It is possible to prevent oxygen from thermally diffusing from the interlayer insulating film into the capacitive polysilicon film. In particular, since the capacitance polysilicon film in the groove opening is not oxidized, there is no volume expansion and the opening of the groove is not opened. As a result, it is possible to suppress the occurrence of a defect that causes a leakage current.

In addition, the capacitor polysilicon film other than the trench is not directly in contact with the interlayer insulating film and is not oxidized, so that the capacity polysilicon film does not become thinner and the resistance of the capacitor electrode can be prevented from becoming higher and lower.

[Brief description of the drawings]

FIGS. 1 (a) to 1 (e) are cross-sectional views shown in the order of steps for explaining one embodiment of the first invention of the present application, and FIGS. 2 (a) to 2 (e) are FIGS. 3 (a) to 3 (e) are cross-sectional views sequentially illustrating steps in order to explain an embodiment of the second invention of the present application, and FIGS. 3 (a) to 3 (e) illustrate prior art. 1. P-type silicon substrate, 2. Field oxide film, 3-1
3-2: groove, 4: capacitance insulating film, 5: capacitance polysilicon film, 6: silicon nitride film, 7-1, 7-2: buried polysilicon film, 8: interlayer oxide film, 9: silicon oxide film , 10: silicon nitride film; 11-1, 11-2, 11-3, 11-4: wedge-shaped silicon oxide film.

Claims (2)

(57) [Claims] An active region is defined by forming an insulating region for element isolation on a surface portion of a semiconductor substrate, a groove is formed in the active region, and a capacitive insulating film is formed on an inner wall of the groove and on a surface of the substrate. Forming a capacitor polysilicon film on the capacitor insulating film, forming a silicon nitride film on the capacitor polysilicon film, and forming a buried polysilicon film on the silicon nitride film. Filling the groove, and removing the buried polysilicon film from a portion other than the inside of the groove,
Forming an interlayer insulating film on the surface of the silicon nitride film and on the surface of the buried polysilicon film. 2. An active region is defined by forming an insulating region for element isolation on a surface portion of a semiconductor substrate, a groove is formed in the active region, and a capacitive insulating film is formed on an inner wall of the groove and on the substrate surface. Forming a capacitor polysilicon film on the capacitor insulating film, forming a silicon oxide film on the capacitor polysilicon film, and forming a buried polysilicon film on the silicon oxide film. Filling the groove, and removing the buried polysilicon film from a portion other than the inside of the groove,
A semiconductor device comprising: forming a silicon nitride film on the surface of the silicon oxide film and on the surface of the buried polysilicon film; and forming an interlayer insulating film on the silicon nitride film. Manufacturing method.