JPS6246556A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To stabilize the threshold voltage of a memory cell, and to improve the reliability by information writing by equalizing an impurity ion-implanted into a channel section for the memory cell. CONSTITUTION:A word line extended so that a plane shape thereof is zigzagged, a gate electrode 5 is shaped onto a gate insulating film 4 by a material having small crystal grains such as molybdenum silicide. An N-type impurity such as As or P is introduced to a P-type well 2 through a self-alignment method using the gate electrodes 5 to form N-type source-drain regions 6 in the P-type well 2. An inter-layer insulating film 7 consisting of PSG, etc. is applied on the whole surface, contact holes 8 are each bored onto the source-drain regions 6, and a plurality of aluminum wirings as data lines 9 are extended in parallel in the direction crossing with the gate electrodes 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device suitable for application to a read-only memory (ROM) in which a MOS field effect transistor is used as a memory cell.

[Background technology]

Various structures have been proposed for semiconductor memory devices such as mask ROMs that use MOS field effect transistors as memory cells, depending on the method for writing information, but recently, from the user's order to the completion of the ROM, The time to arrive (
In order to shorten the TAT (TAT), the entire memory cell is formed first, and then an impurity of the opposite conductivity type to the channel is ion-implanted onto the gate electrode of the memory cell in which information is to be written. A structure in which the threshold voltage is higher than that of other memory cells is used.

However, according to studies conducted by the present inventors, in this method, impurities are ion-implanted into the channel part through the gate electrode, and the ion-implantation effect varies depending on the graininess of the gate electrode, resulting in poor writing reliability. The problem arises that the

That is, in recent years, polycrystalline silicon has been used for the gate electrodes of MOS field effect transistors that constitute memory cells, but since the crystal grain size of this polycrystalline silicon is relatively large and inconsistent, Impurity ion permeability is poor at locations with large crystal grains, while impurity ion permeability is good at locations with small crystal grains. For this reason, the ion implantation effect in the channel portion varies depending on the graininess of the polycrystalline silicon crystal in each gate electrode, and therefore the threshold voltage in each memory cell also varies, reducing the reliability of information writing. That will happen.

Incidentally, this kind of ROM writing method is also described in Japanese Patent Laid-Open No. 130963/1983, which was previously filed by the present applicant.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that can uniformize impurity ion implantation into the channel portion of a memory cell, thereby stabilizing the threshold voltage of the memory cell and improving the reliability of information writing. It's about doing.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

(Summary of the Invention) A brief overview of typical inventions disclosed in this application is as follows.

In other words, by forming the gate electrode of the MOS field effect transistor that constitutes the memory cell from a material with small crystal grains, such as molybdenum silicide or tungsten silicide, impurities that pass through the gate electrode during ion implantation can be made uniform. The reliability of writing can be improved by stabilizing the threshold voltage of a memory cell to which information is written.

〔Example〕

1 and 2 show an embodiment in which the present invention is applied to a mask ROM using an N-channel MO8 field effect transistor as a memory cell. FIG. 1 is a plan view, and FIG.
It is a sectional view along the B line.

As shown in the figure, a P-type well 2 is formed in an N-type silicon substrate 1, and a field insulating film (S i Ox ) 3 having a substantially square planar shape is spaced apart on the main surface of the well.
Moreover, a gate insulating film (SiO□) 4 is formed between these. On the gate insulating film 4, a word line, that is, a gate electrode 5 extending so as to have a zigzag planar shape is formed of a material having small crystal grains, such as molybdenum silicide (MoSi). Then, by introducing N-type impurities such as As (arsenic) and P (phosphorus) into the P-type well 2 by a self-alignment method using this gate electrode 5, an N-type source/drain region is formed in the P-type well 2. 6 is formed.

After that, a glabellar insulating film 7 such as PSG is deposited on the entire surface, and contact holes 8 are formed on the source and drain regions 6, respectively, and then a plurality of aluminum wires as data lines 9 are connected in a direction intersecting the gate electrode 5. It extends parallel to the main line. As a result, a memory cell consisting of a plurality of MOS type field effect transistors is completed, and these are configured to have a predetermined low threshold voltage set so that no information is written.

Therefore, according to this ROM structure, when writing information to a selected MOS field effect transistor Q among all M9S field effect transistors, a resist layer 10 is formed on the top surface as shown in the figure. An opening 1 is formed by patterning the upper part of this MOS field effect transistor Q.
0a. Then, by ion-implanting an impurity of a conductivity type opposite to that of the source/drain region 6, for example, B (boron), boron is passed through the gate electrode 5 of the MOS field effect transistor Q from the opening 10a of the resist layer 10 to the channel thereof. Driven into the department. As a result, the threshold voltage of this MO5 type field effect transistor Q is increased, and information is held in a written state in a normal read operation.

In this case, since the gate electrode 5 of the MOS field effect transistor Q is formed of molybdenum silicide with small crystal grains, the impurities that permeate through the gate electrode 5 during the impurity ion implantation described above uniformly penetrate the gate electrode 5. It will be transmitted through and therefore evenly implanted into the channel portion. This results in
It is also possible to uniformly implant impurities into each memory cell, stably increasing each threshold voltage, and completing highly reliable information writing.

〔effect〕

(1) The gate electrode of the MOS field effect transistor that constitutes the memory cell of the ROM is made of a material such as molybdenum silicide with small crystal grains, so when impurities are ion-implanted for information writing, the channel part The implanted impurities can be made uniform, the threshold voltage of the memory cell can be stably increased, and the reliability of information writing can be improved.

(2) Improved write reliability can be achieved by configuring the gate electrode of the MOS field effect transistor that constitutes the memory cell with a material with small crystal grains, so all you have to do is change the material of the conventional gate electrode. There is no need to change the manufacturing process, and it can be easily formed.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the present invention can be similarly applied to a mask ROM using a P-channel MOS field effect transistor as a memory cell. Further, as the material of the gate electrode, tungsten silicide (WSiz) or other silicide metals, polycide made by extremely thinning a polycrystalline silicon layer, or the like may be used as long as the material has small crystal grains.

[Application field]

In the above description, the invention made by the present inventor was mainly applied to a semiconductor storage device having a mask ROM configuration, which is the field of application that formed the background of the invention, but the invention is not limited thereto. It can also be applied to semiconductor devices such as.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view taken along line BB in FIG. 1. 1... Silicon substrate, 2... P-type well, 3...
Field insulating film, 4... Gate insulating film, 5... Gate electrode word 'fa), 6... Source/drain region, 7... Interlayer insulating film, 8... Contact hole, 9... ...Data line, 10...Resist, Q...M
OS type field effect transistor (memory cell). Figure 1 Figure 2

Claims (1)

[Claims] 1. A MOS field effect transistor is used as a memory cell,
A semiconductor memory device in which information is written by controlling the threshold voltage by implanting impurity ions into the channel portion from above the gate electrode, the gate of the MOS field effect transistor constituting the memory cell. A semiconductor memory device characterized in that an electrode is formed of a material with small crystal grains. 2. The semiconductor memory device according to claim 1, wherein the gate electrode is formed of molybdenum silicide or tungsten silicide.