JPS6142168A - Read only memory - Google Patents

Abstract

PURPOSE:To reduce the occupation area by reducing the memory cell area per bit by a method wherein part of the second gate electrode is formed by lamination on the first gate electrode via insulation layer, and an impurity is introduced under the second gate electrode. CONSTITUTION:On the region serving as the channel of a semiconductor substrate 11, the first gate electrode that inputs word line signals is formed of a poly Si 14 via gate insulation film 13. Overlapping on the poly Si 14, the second gate electrode is formed of a poly Si 15. The poly Si 14 and the poly Si 15 are insulated from each other with an interlayer insulation film 16. At the gate part formed of the poly Si 15, a heavy-dose region 17 is formed by diffusing an N type impurity the same as for a diffused region or by its ion implantation. If a high potential is given to the word line 14 by the heavy-dose region 17, the channel is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to read-only memories (ROMs), and more particularly to mask ROMs that are preprogrammed at some stage of device manufacturing.

<Prior art> Parallel array method, series array method, and series-parallel array method have generally been developed as mask ROM data setting methods. Among these methods, when particularly high-speed operation is expected, the parallel array method is suitable. 0 Figures 4 to 7 show masks R that have been put into practical use in the past.
In the semiconductor substrate plan view and its equivalent circuit diagram showing the main parts of the OM, a diffusion region 2 of opposite conductivity type is formed in the semiconductor substrate;
A word line 7>E which becomes the gate of the KMO8 transistor in a direction perpendicular to the diffusion region 2 is formed of polysilicon 8, and a bit line is formed of a metal film 4 extending over the polysilicon 3 and parallel to the diffusion region 2. has been done.

v; When data is set in the mask ROM having the structure shown in FIG. indicates no contact.)
The ROM data is determined by

Furthermore, when setting data in a mask ROM having the structure shown in FIG.
Whether or not to form an S transistor is determined by the mask used when forming the diffusion region 2. In the figure, the polysilicon 31 forms the MOS transistor Tr+, but the polysilicon 3□ indicates that the diffusion region in the semiconductor substrate is indicated by the broken line. 6, and ROM data is set depending on the presence or absence of diffusion that can constitute a MOS transistor.However, the contact ROM setting method shown in Fig. 4 has the disadvantage that the area occupied per bit becomes large. In addition, the diffusion ROM setting method shown in Figure 6 reduces the area occupied per bit, but since the ROM data is set in the diffusion process, it takes a long time from setting the ROM data to completing the final product. There was a drawback.

<Object of the Invention> The present invention eliminates the drawbacks of the conventional mask ROM described above, and is superior to the contact ROM setting method in terms of occupied area.
Furthermore, it provides a mask ROM that is superior to the diffuse setting method in terms of required time.

<Example> An example applied to an N-channel MOS process will be described.

FIG. 1 schematically shows a plane of a semiconductor substrate, FIG. 2 is a sectional view taken along line AA' of the semiconductor substrate, and FIG. 3 is an equivalent circuit diagram.

In the figure, a semiconductor substrate 11 has a diffusion region 12 of opposite conductivity type.
is formed, and the diffusion region 12 is a region that functions as a source, a drain, etc. For example, the diffusion region 1 serving as a source
2 further has a diffusion region 12' formed in a perpendicular direction and is connected to the ground potential.

Semiconductor substrate 11 on which the diffusion regions 12 and 12' are formed
A first gate electrode for inputting a positive word line signal through a gate insulating film 13 is formed of a first layer of polysilicon 14 on a region that becomes a channel of the MOS transistor. A second gate electrode is formed of a second layer of polysilicon 15, partially overlapping the first layer of polysilicon 14. The first polysilicon layer 14 and the second polysilicon layer 15 are insulated by an interlayer insulating film 16. The first and second layer polysilicon 14
．． 15 serves as a gate electrode, and a continuous channel can be formed on the surface of the semiconductor substrate between the diffusion regions 12 and 12. A ground potential is applied to the second layer polysilicon 15.

However, in the above semiconductor structure alone, the channel can be made continuous using only the gate electrode made of the first layer of polysilicon 14, and since the second layer of polysilicon 15 is connected to the ground potential, the word line cannot be connected. Regardless of the potential of the certain gate electrode J4, the MOS transistor is always in an off state and cannot be used as a ROM. That is, M.O.
Since the S transistor is only in the off state, +1" and 10" data cannot be written.

Therefore, if the content of the ROM data to be written next is “region” or 1#
According to the above, heavy dose region 1 is formed by selectively diffusing the same N-type impurity as diffusion region 12 into the gate portion formed by the second layer polysilicon] 5 or by ion implantation.
form 7. Due to the heavy dose region 17, when the word line 14 is in a selected state (in this embodiment, a high potential is applied), a channel is formed in the MOS transistor M1, and the MOS transistor M1 is turned on.

Note that if the word line 14 is in a non-selected state (a low potential is applied in this embodiment), the corresponding MOS transistor is in an off state.

In addition, the MOS transistor M2, in which the heavy dose region as described above is not formed in the semiconductor substrate under the second layer polysilicon 5, cannot form a continuous channel even if a high potential is applied to the word line 14. It cannot function as a transistor.

In the figure, a bit line 18 is formed by a metal film on the semiconductor substrate on which the first and second polysilicon layers 14 and 15 are formed.
are formed and connected to the diffusion region 12 as necessary.

In the above embodiment, a heavy dose region was selectively formed using the second layer polysilicon 15 in a portion of the semiconductor substrate where a channel is formed, but the second layer polysilicon 15 other than the portion where a channel is formed is Since it is stacked on the first polysilicon layer 14 and separated from the surface of the semiconductor substrate, impurities can be introduced over the entire surface of the second polysilicon layer 15. That is, since the first layer polysilicon 14 is present, it acts as a mask and suppresses the introduction of impurities into the substrate surface, so that impurities are implanted only into the gate portion formed by the second layer polysilicon. In this case, the heavy dose region 17 can be formed by self-alignment using the first layer polysilicon 14 as a mask, and mask alignment becomes very easy.

The above explanation has been made using an N-channel MO8) Randisk as an example, but it is also possible to implement the same with a P-channel MOS transistor, and the peripheral circuit is configured with 0MO8 and only the ROM memory cell part is an N-channel MO8) Ranjisk. Exactly the same effect can be obtained by using a P-channel MOS transistor.

Further, in the description, polysilicon is used as the gate electrode material, but the gate electrode material need not be limited to polysilicon as long as it can constitute a two-layered gate such as polycide, silicide, refractory metal, etc.

<Effects> According to the present invention, as compared to the contact ROM setting method, since one contact can be shared by adjacent MOS transistors, the memory cell area per bit is reduced, and the occupied area can be reduced.

Furthermore, compared to the diffusion ROM setting method, the heavy-dose formation step for setting ROM data is performed after polysilicon formation, and the required time can be shortened.

[Brief explanation of drawings]

1 to 3 are a plan view, an AA' sectional view and an equivalent circuit diagram showing an embodiment of the present invention, FIG. 4 is a plan view of a conventional device, and FIG. 5 is a plan view of the same device. Equivalent circuit diagram of 6th
The figure is a plan view of another conventional device, and FIG. 7 is an equivalent circuit diagram of the same device. 1: Semiconductor substrate, 12: Diffusion region, 14: 2nd layer polysilicon, 15: 2nd layer polysilicon,
17: Heavy dose region, 18: Metal film.

Claims (3)

[Claims] (1) A first gate electrode to which an input signal for selecting a MOS transistor is applied and a second gate electrode to which a potential to turn off the MOS transistor is applied are connected to the second gate electrode through an insulating layer. A part of the electrode is formed by stacking it on the first gate electrode, and an impurity is introduced under the second gate electrode to make the channel continuous according to the contents of the ROM data to be set. Read-only memory. (2) The impurity for making the channel conductive is the first impurity.
2. The read-only memory according to claim 1, wherein the read-only memory is selectively introduced into an area of the semiconductor substrate located under the second gate electrode that does not overlap with the second gate electrode. (3) The impurity for making the channel conductive is the first impurity.
The impurity is introduced from above the second gate electrode using the gate electrode as a mask, and the impurity is locally introduced into the semiconductor substrate depending on the distance between each part of the second gate electrode and the surface of the semiconductor substrate. A read-only memory according to claim 1, characterized in that: