JP2838702B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a field effect transistor, and more particularly to a technique capable of realizing a method of manufacturing a large capacity ROM device.

[0002]

2. Description of the Related Art Generally, a mask ROM cell is manufactured by recording binary data "0" or "1" in a unit cell at the manufacturing stage, unlike a RAM. In a conventional mask ROM device, for example, one cell, which is a unit storage element, is mainly composed of an NMOS transistor.

FIG. 6 is a circuit diagram showing a partial cell of a ROM constituted by a NAND gate type. FIG. 7 shows an arrangement of bit lines and word lines when the circuit of FIG. 6 is formed on an actual semiconductor substrate. FIG. 8 is a sectional view taken along line III-III of FIG. As shown in FIG. 6, a selector line S / S to which a bit line selection signal is applied is applied.
Since the transistors Q11 and Q22 (or conversely, Q12 and Q21) connected to L are formed of depletion transistors, when a voltage is applied between the source and the drain, if no voltage is applied to the gate, Always turned on, the transistors Q12 and Q21
Since (or Q11 and Q22) are formed from enhancement transistors, ON or OFF is controlled by the gate voltage. The remaining transistors Q11, Q12, ···, Q1n, Q21, Q22,
.. , Q2n are transistors coded as enhancement transistors or depletion transistors by ROM data recording. Data recording in a mask ROM is performed by forming a depletion transistor or an enhancement transistor at a memory address determined by a word line and a bit line when a ROM device is manufactured.

Next, a method of reading data from such a ROM cell will be described. When a voltage is applied to the bit line and the word line, the word line voltage of the address to be read is applied at a different voltage from the other word line voltages, and a selector signal is applied to select one bit line. Appears on the bit line. Then, the voltage state of the bit line, that is, data is read by the sense amplifier.

A method for forming the above circuit on a substrate will be described with reference to FIGS. First, the semiconductor substrate 1
At 0, a field region 11 is formed to divide the active region 12 at a position where a bit line is formed.
Next, a gate insulating film 14 is formed on the active region,
The ion implantation 15 is performed at a position where a depletion transistor is to be formed, and ROM data is recorded.

Subsequently, polysilicon is deposited, the gate line 13 is patterned, ions are implanted into side surfaces of the gate line 13 to form source and / or drain regions 16, and a gate sidewall spacer (Sidewall spacer) 17 is formed. After that, the upper part is covered with the insulating film 18 to complete the cell manufacturing. Drain formed at one end of active area
The region is connected to the bit line through a metal wiring, and the source region formed at the other side end is connected to the ground Vss. Also, the polysilicon gates are each connected to a word line.

[0007]

In such a conventional field effect transistor, lithography is used to define the active region and the polysilicon gate line, and there is a limit in reducing the line width. There is a limit to raising. Therefore, the memory capacity of the ROM cell is increased, and larger area occupied by a cell forming region as it, productivity step stopped decreases, a problem that reliability of the product also decreases occurs.

[0008] The present invention has such has been made in view of the conventional problems, by laminating the two transistors, to provide a method of <br/> manufacturing a field effect transistor capable of improving the degree of integration With the goal.

[0009]

Therefore, a method of manufacturing a field-effect transistor according to the first aspect of the present invention is a method for manufacturing a field-effect transistor according to the first aspect.
Forming a field insulating film on a semiconductor substrate
A first gate insulating film on the active region
After forming, polysilicon is deposited and patterned
Forming a gate electrode, and masking the gate electrode.
Implanting predetermined impurity ions to
The first conductivity type is provided on the first conductivity type semiconductor substrate below both sides.
A first source region and a first drain of a second conductivity type having different rear regions;
Forming an in-region and the entire first conductivity type semiconductor substrate
An insulating film is deposited on the region, and the upper surface of the gate electrode is exposed.
The insulating film is etched back so that
Forming an insulating layer on the side surface;
Forming a second gate insulating film, with the second gate insulating film interposed therebetween;
To form a first conductive type semiconductor material layer on the gate electrode
Corresponding to both sides of the gate electrode of the semiconductor material layer
The second conductivity type impurity ions are implanted into the region to be
Forming a drain region and a second drain region .

According to this step , first, the first conductivity type half
A field insulating film is formed on a conductive substrate to divide an active region, a first gate insulating film is formed on the active region, and polysilicon is deposited and patterned to form a gate electrode. Next, the gate electrode is used as a mask.
Implant predetermined impurity ions, and
The first conductive type semiconductor substrate has a carrier of the first conductive type.
First source region and first drain region of different second conductivity types
Form an area. Next, over the entire first conductivity type semiconductor substrate area
Depositing an insulating film to expose an upper surface of the gate electrode;
Etch back the insulating film as shown in FIG.
An insulating layer is formed. Next, a second gate insulating film is formed on the surface of the gate electrode, a semiconductor material layer of a first conductivity type is formed on the second gate insulating film, and a second conductive material layer is formed on both sides of the gate electrode. The second source region and the second drain region are formed by implanting predetermined impurity ions having a shape, and two source and drain regions are vertically arranged with one gate electrode interposed therebetween.
A field effect transistor having the region and the drain region formed is formed.

According to a second aspect of the present invention, in the method of manufacturing a field effect transistor, the step of forming the gate electrode is performed.
Depletion after forming the first gate insulating film
Implantation of second impurity ions into the part where transistor is formed
This is the step of performing According to such a process , when a ROM cell is formed, coding is performed thereby.

[0012] In the manufacturing method of the field effect transistor according to the invention of claim 3, feel to the first conductivity type semiconductor substrate
Form active insulator to separate active areas
After the first gate insulating film is formed on the
Patterning and patterning to form a gate electrode
And an insulating film is deposited on the entire region of the first conductivity type semiconductor substrate.
Then, the insulating is performed so that the upper surface of the gate electrode is exposed.
Etch back film to form insulating layer on side of gate electrode
And insulating the side surface of the gate electrode and the gate electrode
Using the layer as a mask, predetermined impurity ions are implanted,
The first conductivity type is provided on the first conductivity type semiconductor substrate below both sides of the contact electrode.
A first source region of a second conductivity type having a different carrier from the first source region;
Forming a first drain region;
Forming a second gate insulating film on the surface;
A semiconductor material layer of the first conductivity type over the gate electrode
Forming the semiconductor material layer on both sides of the gate electrode.
A second conductivity type impurity ion is implanted into the corresponding region,
Forming a source region and a second drain region .

According to such a process , the invention of claim 1
Similar to the method for manufacturing the mowing field effect transistor, one of the field-effect transistor which two source and drain regions vertically through the gate electrode is formed is formed.

[0014]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIG. An example of a ROM cell which is manufactured by applying the manufacturing method of the field effect transistor according to an embodiment of the present invention shown in FIG. The configuration of the ROM cell array shown in FIGS. 6 and 7 is the same in the present embodiment, and the word lines and the bit lines are laid out so as to be orthogonal to each other.
It is sectional drawing of the I-III line.

As shown in FIG. 1, in the present embodiment, a p-type semiconductor substrate 1 of the first conductivity type is doped with n ⁺ impurity ions so as to have a predetermined interval and a predetermined width.
An n-type first source / drain region 2 is formed as a second conductivity type, and a silicon oxide film 4 as a first gate insulating film is located on the surface of the semiconductor substrate 1. Further, since the gate electrode 3 is formed on the silicon oxide film 4, a transistor is formed together with the first source / drain region 2. This transistor operates as a depletion transistor or an enhancement transistor depending on the ROM coding state. A second gate insulating film 5 is formed on the gate electrode 3, and the gate electrode 3 is insulated from the gate electrode 3 by a sidewall spacer.
A polysilicon layer 7 for a p-type TFT as a semiconductor material layer is formed on the second gate insulating film 5, and n ⁺ impurity ions are implanted at positions corresponding to the first source / drain regions. The second source / drain region 6 is located. Then, a silicon oxide film 8 as a passivation film is formed thereon.

Next, a method for manufacturing such a ROM cell will be described. First, as shown in FIG. 2, in order to form an active region in a p-type semiconductor substrate 51, a field insulating film 52 is formed by a LOCOS process, and an active region defined by the field insulating film 52 (a bit in FIG. 7). A first gate insulating film (oxide film) 53 is formed in the same as the line region).

Polysilicon is deposited on the first gate insulating film 53 formed by photolithography.
The gate electrode 54 is formed by a thography method.
Before forming the gate electrode 54, impurity ions are generally implanted at the position where the depletion transistor is to be formed in order to code ROM data.

However, in order to prevent a position error at the time of ROM coding, a primary gate electrode is formed only at a position where a depletion transistor is not formed. An electrode may be formed on the primary gate electrode and the ion implantation site to form a final gate electrode. An oxide film is deposited on the entire region of the semiconductor substrate 1 on which the gate electrode 54 is formed, and then etched back to form a sidewall spacer 55 of the oxide film on the side surface of the gate electrode 54. like this
Then, an oxide film is deposited on the entire region of the semiconductor substrate 1 and etched.
By backing, the space between the gate electrodes 54 is an insulating film.
Filling and flattening the surface of the gate electrode
Is preferred.

Next, as shown in FIG. 3, the semiconductor substrate 51
The entire surface by implanting n ⁺ impurity ions, the unmasked areas by the gate electrode 54, i.e., implanting impurity ions into the semiconductor substrate 51 on both sides beneath the region of the gate electrode 54. These impurity ions are thermally diffused in a later step to form first source / drain regions 56. After the above-described ion implantation step, a second gate insulating film 57 is formed on the exposed surface of the gate electrode 54 as shown in FIG. This second game
The insulating film 57 is formed by depositing an oxide film.

Next, as shown in FIG. 5, a p-type polysilicon layer (semiconductor material layer) for TFT is formed on the second gate insulating film 57, and an upper region corresponding to the first source / drain region 56 is formed. by implanting an n ⁺ impurity ions to form a second source / drain region 58. Then, a region 59 between the second source / drain regions 58 becomes a channel region of the TFT transistor.

Subsequently, the second source / drain regions 58 and
A silicon oxide film 66 is formed over the entire upper surface of the region 59 . By such a process, RO having the same cell structure as in FIG.
An M cell is manufactured. In the ROM cell having the above structure, a TFT transistor by a semiconductor material layer disposed on the gate electrode 54, a common transistor formed on a semiconductor substrate located under the gate electrode 54, gate electrode 54 To share.

In the subsequent steps, the gate electrodes 54 are connected by word lines, and the first source / drain regions 56 formed below the first gate insulating film 53 are connected to the bit lines as shown in FIG. Connected and grounded, the second TFT transistor on the second gate insulating film 57
The source / drain region 58, by grounding connected to the bit line as shown in FIG. 6, the general NAN
A D-type memory circuit is configured.

Therefore, the fabrication of the field effect transistor of the present invention
The ROM cell manufactured by the fabrication method has a first source /
A first transistor comprising a drain region 56 and the gate electrode 54, gate electrode and the second source / drain regions 68
And a second transistor comprising the pole 54. And
The first transistor and the second transistor share a gate electrode and are formed to be three-dimensionally stacked. Accordingly, when a predetermined voltage is applied to the gate electrode 54 as a word line, the first transistor and the second transistor are turned on at the same time.

Further, operation of the ROM device is not the same as conventional, it is possible to increase the cell array degree of integration about two times.

Further, the production of such a field effect transistor
Field-effect transistor manufactured by the method is not limited to the ROM cell of the present embodiment may be applied to look like. Further, in the present embodiment, the first conductivity type and the second conductivity type are p-type and n-type, respectively, but these can be reversed.

[0026]

As described above, according to the method of manufacturing a field effect transistor according to the first aspect of the present invention, two transistors sharing a gate electrode can be stacked. In particular, when such a method for manufacturing a field-effect transistor is applied to the manufacture of a ROM cell , the degree of integration can be doubled as compared with the related art, and the degree of integration is improved.

According to the method of manufacturing a field effect transistor according to the second aspect of the present invention, when applied to a ROM cell,
Can be coded. According to the manufacturing method of a field effect transistor according to the invention of claim 3, similarly
Two transistors sharing a gate electrode
Can be

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an embodiment of the present invention.

FIG. 2 is a sectional view showing the manufacturing process of FIG. 1;

FIG. 3 is a sectional view of the same.

FIG. 4 is a sectional view of the same.

FIG. 5 is a sectional view of the same.

FIG. 6 is a circuit configuration diagram of a general ROM cell.

FIG. 7 is a plan view of FIG. 6;

FIG. 8 is a sectional view taken along line III-III of FIG. 7;

[Explanation of symbols]

REFERENCE SIGNS LIST 1 p-type semiconductor substrate 2 first source / drain region 3 gate electrode 4 silicon oxide film 5 second gate insulating film 6 second source / drain region 7 polysilicon layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-21758 (JP, A) JP-A-5-63163 (JP, A) JP-A-4-146670 (JP, A) JP-A-4-146670 107859 (JP, A) JP-A-6-13564 (JP, A) JP-A-7-45716 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/8246 H01L 27 / 112 H01L 29/78

Claims (3)

(57) [Claims] 1. Field insulation on a first conductivity type semiconductor substrate
The active area is divided by forming a film,
After forming the first gate insulating film thereon, the polysilicon is evaporated.
And patterning to form a gate electrode , and using the gate electrode as a mask, injecting predetermined impurity ions.
Into the first conductive type semiconductor substrate below both sides of the gate electrode.
A first saw of a second conductivity type having a different carrier from the first conductivity type.
Forming a source region and a first drain region; and depositing an insulating film over the entire first conductivity type semiconductor substrate.
Etch the insulating film so that the upper surface of the gate electrode is exposed.
Forming an insulating layer on the side surface of the gate electrode
When the second gate insulating film formed on the gate electrode surface, said
2 First conductivity type on top of gate electrode via gate insulating film
Forming a semiconductor material layer, and forming a semiconductor material layer in regions corresponding to both sides of the gate electrode in the semiconductor material layer.
A second source region and a second source region;
Forming a drain region. 2. A field effect transistor, comprising:
Manufacturing method. 2. The method according to claim 1, wherein the step of forming the gate electrode comprises :
After forming the gate insulating film, depletion transition
Implanting a second impurity ion into a portion for forming a star
3. The field effect transformer according to claim 1, wherein
Method of manufacturing a resistor. 3. Field insulation on a first conductivity type semiconductor substrate.
The active area is divided by forming a film,
After forming the first gate insulating film thereon, the polysilicon is evaporated.
Depositing and patterning to form a gate electrode, and depositing an insulating film over the entire first conductivity type semiconductor substrate,
Etch the insulating film so that the upper surface of the gate electrode is exposed.
Forming an insulating layer on the side surface of the gate electrode
And a mask for the gate electrode and the insulating layer on the side surface of the gate electrode.
And implanting predetermined impurity ions,
The first conductivity type is a carrier on a lower first conductivity type semiconductor substrate.
Source region and first drain of a second conductivity type different from each other
Forming a region, forming a second gate insulating film on the surface of the gate electrode,
2 First conductivity type on top of gate electrode via gate insulating film
Forming a semiconductor material layer, and forming a semiconductor material layer in regions corresponding to both sides of the gate electrode in the semiconductor material layer.
A second source region and a second source region;
Forming a drain region. 2. A field effect transistor, comprising:
Manufacturing method.