JPS5856468A - Manufacture of semiconductor - Google Patents
Manufacture of semiconductorInfo
- Publication number
- JPS5856468A JPS5856468A JP56155284A JP15528481A JPS5856468A JP S5856468 A JPS5856468 A JP S5856468A JP 56155284 A JP56155284 A JP 56155284A JP 15528481 A JP15528481 A JP 15528481A JP S5856468 A JPS5856468 A JP S5856468A
- Authority
- JP
- Japan
- Prior art keywords
- film
- impurity
- gate
- rom
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 13
- 230000002708 enhancing effect Effects 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052796 boron Inorganic materials 0.000 abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 6
- 239000011574 phosphorus Substances 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 6
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- -1 boron ions Chemical class 0.000 abstract description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 101100087530 Caenorhabditis elegans rom-1 gene Proteins 0.000 description 1
- 101100305983 Mus musculus Rom1 gene Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- AQLLMLUUWKQYRG-UHFFFAOYSA-N [B++] Chemical compound [B++] AQLLMLUUWKQYRG-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法に係り％特にワンチッ
プマイクロコンピュータ等に内蔵される半導体マスクＲ
ＯＭ （Ｒｅａｄ ＯｎｌｙＭｓｍｏｒｙ ）の形成に
用いて好適な半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a semiconductor mask R built in a one-chip microcomputer or the like.
The present invention relates to a method of manufacturing a semiconductor device suitable for use in forming an OM (Read Only Msmory).
従来、ワンチップマイク−コンピュータのｆｆｉ憶装置
、特にユーザの要求によって書°き込みデータが定めら
れ６ ＲＯＭでは、一般にマスクＲＯＭが利用される。Conventionally, a mask ROM is generally used in a one-chip microphone-computer FFI storage device, especially in a ROM in which write data is determined according to a user's request.
かかるワンチップマイク−コンピュータは同一チップ上
に中央処理５５ （ＣＰＵ ） ｐ ＲＡＭ （１ｌａ
ｎｄａｎムｅｅ＠ｍｓ Ｍｅｍｏｒｙ ）、ＲＯＭ、
ｉｌｏ ボート等を塔載してなるが、ユーザにより書
き込みデータの指定されるＲＯＭは通常ＲＯＭ以外の部
分の製作工程の後に製作が行なわれ、％にユーザの要求
に応じるためにはマスクＲＯＭの製作工程に於て、半導
体装置の製品出荷に近い工程でマスクパターンを定めて
手番な短（する必要がある。Such a one-chip microphone-computer has a central processing unit 55 (CPU) p RAM (1 la
ndanmuee@msMemory), ROM,
The ROM, in which writing data is specified by the user, is usually manufactured after the manufacturing process of parts other than the ROM, and in order to meet the user's requests, it is necessary to manufacture a mask ROM. In the manufacturing process, it is necessary to determine the mask pattern and shorten the steps close to the shipping of the semiconductor device.
しかしながら、ナントゲート回路からなり、該当ビット
のトランジスタがデプリーシＢンＭ０８トランジスタ（
Ｔｒ ）か、エンハンスメントＭＯ８Ｔｒかによってデ
ータの書き込みを行うようにしたマスクＲＯＭでは製品
出荷の手番が長（なる欠点があった。However, it consists of a Nant gate circuit, and the transistor of the relevant bit is a depletive B M08 transistor (
A mask ROM in which data is written depending on whether the MO8Tr or the enhancement MO8Tr has a disadvantage in that it takes a long time to ship the product.
このよ５に手番が長くなる理由について、第１図を参照
して説明する。The reason why the number of turns becomes longer than 5 will be explained with reference to FIG.
尚、以後説明するＭＯ８ＦＥＴ（金属嫉化物半導体電界
効果形トランジスタ）！工、ＰＷｉ及びＮ型を含み、エ
ンハンスメン）ｊｌＴｒｔニゲ−Ｆ端子に零ホル）のバ
イアス電圧をかけたとき通常非導通であるが、特定の大
きさの電圧をゲート端子間に加えれば導通状態となる。Furthermore, the MO8FET (metal-jetide semiconductor field effect transistor) which will be explained later! When a bias voltage of zero (zero hole) is applied to the F terminal (incl. G, PWi, and N type), it is normally non-conductive, but if a voltage of a certain magnitude is applied between the gate terminals, it becomes conductive. becomes.
他方、デプリーション屋丁ｒ は、ゲート端子に加えら
れるバイアス電圧がな（ても導通しているが、適当なバ
イアス電圧がゲージ端子に加われば非導通状態となるも
のである。On the other hand, a depletion gate is conductive even when no bias voltage is applied to the gate terminal, but becomes non-conductive when an appropriate bias voltage is applied to the gauge terminal.
第１図を工、エンハンスメントＭＯ８ＦＥ丁 とデプリ
ーションＭＯ８ＦＫ丁 を同一基板に同時形成する場合
の工程を示すもので基板ｌは、例えばｐｍシリコンで厚
い酸化膜（フィールド酸化膜）２とゲート酸化膜３が形
成されボロン（Ｂ）が、イオン注入され左右のＭＯＳＦ
ＥＴ 作製領域の基板表面下には正確に制御されたボ
ロンが注入された層４が形成されるａ、（篤を図ム）、
、この状態でデプリーションＭＯ８Ｆ）ＣＴ とした
い部分（第１図外）で右側）のみに、リン（ｐ）のイオ
ン注入を行ってボロンが注入された層４にリンの不純物
を注入することでデプリーションモードのチャンネルを
作る。（第１図＄１）次に多結晶シリコン６をパターニ
ングしてゲート領域を形成し、ゲート酸化膜３の一部を
除去し。Figure 1 shows the process for simultaneously forming enhancement MO8FE and depletion MO8FK on the same substrate. Boron (B) is formed and ions are implanted into the left and right MOSFs.
A layer 4 in which precisely controlled boron is implanted is formed below the surface of the substrate in the ET fabrication region.
In this state, phosphorus (p) ions are implanted only in the part where depletion MO8F)CT is desired (on the right side outside of Figure 1), and phosphorus impurity is implanted into the layer 4 into which boron has been implanted. Create a plea mode channel. (FIG. 1 $1) Next, polycrystalline silicon 6 is patterned to form a gate region, and a portion of gate oxide film 3 is removed.
ｎ型不純物を拡散又はイオン注入してソース７とドレイ
ン８を形成する。（第１図ｔ−））このような工程によ
ると第１図１の左側のＭＯＳＦＥＴは、エンへンスメン
ト屋に、右側ｆ）ＭＯＳＦＥＴ ４工、デプリーション
屋に１つのマスクで作９ことができるが、手番は厚い酸
化膜２とゲート酸化膜３を作る工程で定められマスクＲ
ＯＭ等を作るときＫは冒頭に述べた手番が長い欠点とな
る＠これはＰ 又はヒ素（ムｍ ）等のＮ型不純物をイ
オン注入する時の射影飛程（Ｒｐ ） が小さいため
ゲート酸化膜３の様な薄い酸化膜しか通１）′″゛抜け
ないためであ金。A source 7 and a drain 8 are formed by diffusing or ion-implanting n-type impurities. (Fig. 1 t-)) According to this process, the MOSFET on the left side of Fig. 1 can be made by an enhancement shop, the MOSFET on the right side (f) can be made by 4 pieces, and the depletion shop needs 1 mask. , the turn is determined by the process of making thick oxide film 2 and gate oxide film 3, and mask R
When making OM etc., K has the drawback that it takes a long time as mentioned at the beginning @This is because the projected range (Rp) is small when ion implanting N-type impurities such as P or arsenic (Mm), so gate oxidation is required. This is because only a thin oxide film like film 3 can pass through.
本発明は、上述の欠点を除去したデプリーションＭＯＢ
ＦＥＴ とエンハンスメントＭＯ８ＦＩＣ〒 を用いて
書き込みを行う様にしたＲＯＭを用いて高集積化し得る
と共に手番が短い半導体装置の製造方法を提供するもの
で、その特徴とするところはグーＦ酸化膜形成後に不純
物注入によってデプリーション化したＦＩＴ ＆グー（
電極形成後選択的に不純物注入することでエンハンスメ
ント化した半導体装置の製造方法である。The present invention provides a depletion MOB that eliminates the above-mentioned drawbacks.
It provides a method for manufacturing semiconductor devices that can achieve high integration and shorten the steps by using a ROM in which writing is performed using FETs and enhancement MO8FICs. FIT & Goo depleted by impurity injection (
This is a method of manufacturing an enhanced semiconductor device by selectively implanting impurities after electrode formation.
以下１本発明の実施例を第２図につい【詳記する・
第２図（４）は、クエハとして例えば２Ｍ１シリコン基
板１上に＠化膜２ａ を形成し、窒化シリコン膜９を
酸化膜２ａ 上ＦＣＣＶＤ （Ｃｈ＠ｍ１ｅａｌ Ｖ
ａｐｏｕｒ Ｄｅｐｏｓｉｔｌｏｎ勢で積層したのち、
第２図（Ｂ） Ｋ示すように窒化シリコン膜９をバター
ニングし【ボロン（Ｂ＋）のイオン注入を行ないｇ２図
（Ｃ）の如き酸化工程によって厚い酸化膜（フィールド
酸化膜）２を形ｓ、ｊる。Embodiment 1 of the present invention will be described in detail below with reference to FIG. Upper FCCVD (Ch@m1eal V
After laminating with apour depositlon,
The silicon nitride film 9 is buttered as shown in FIG. 2 (B), boron (B+) ions are implanted, and a thick oxide film (field oxide film) 2 is formed by an oxidation process as shown in FIG. 2 (C). ,jru.
次に、第２図Φ）Ｋ示す如き工程によって窒化シリコン
膜９および二酸化シリコン２ａ をエツチングにより
除去し、その後ゲート酸化膜３を成長させる。Next, silicon nitride film 9 and silicon dioxide 2a are removed by etching in a step as shown in FIG. 2 Φ)K, and then gate oxide film 3 is grown.
この段階で、ｌ！２図（２））の如（マイクロプンビエ
ータのＲＯＭ以外の部分１例えばＣＰＵ部の半導体素子
にボロン（Ｂ＋）のイオン注入を行って、エンハンスメ
ント化したＦＥＴを得るためにシリコンウェハ表面下部
に閾値−節したポｐン層１２を形成する。尚、１１はレ
ジスト層である。At this stage, l! As shown in Figure 2 (2), boron (B+) ions are implanted into the semiconductor element of the micropunbiator other than the ROM 1, such as the CPU part, and a threshold value is implanted at the bottom of the silicon wafer surface to obtain an enhanced FET. - Form a knotted pop-on layer 12. Note that 11 is a resist layer.
次に、ポρン層の形成された部分に選択的に燐（Ｐ”）
をイオン注入する。この際、第２図便）に示す如＜ Ｒ
ＯＭ部分のＭＯＳＦＥＴ 部分も同時形成し、Ｐ＋を
イオン注入してデプリーション型ＦΣ丁不純物ド不純物
濃度の相違によりデプリーションモードを与えることに
なる。Next, phosphorus (P”) is selectively applied to the portion where the PON layer is formed.
ion implantation. At this time, as shown in Figure 2)
The MOSFET portion of the OM portion is also formed at the same time, and P+ ions are implanted to provide a depletion mode due to the difference in impurity concentration.
以下、説明ｊる工程ではＲＯＭ構造のみを説明する Ｏ
第２図側）で、デプリーション化されたＭＯＳＦＥＴは
、レジスト１１を除去した後に必要個所のみゲート酸化
膜３の部分の窓１５が第２図り）の如くエツチングで成
される。尚、１４はゲート酸化膜エツチング用レジスト
である。In the following steps, only the ROM structure will be explained (see Figure 2). In the depleted MOSFET, after removing the resist 11, the window 15 of the gate oxide film 3 is removed only at the necessary locations as shown in Figure 2. ) is done by etching. Note that 14 is a resist for etching the gate oxide film.
次の工程では、第２間知の如く全面にポリシリフン膜１
６が成長され、その後燐の不純物拡散を行うことでポリ
シリコンの抵抗値を下げる操作が行なわれる。In the next step, a polysilicon film is applied to the entire surface as shown in the second step.
6 is grown, and then an operation is performed to lower the resistance value of the polysilicon by diffusing phosphorus impurities.
次の工程で６エ、第２図（Ｉｌの如くゲート電極のパタ
ーニングが行なわれる０次に、１６い酸化膜１７を成長
させ、その−を通し、ヒ累（ム一）のイオン注入をおこ
なう。ヒ素のイオン注入後、薄い酸化膜１７を除去し、
更に、プルツク酸化１睦行なつり ・
更に、第２図（６）に示すようにＰ２Ｏ等の絶縁層２θ
が形成されて、第２図〜）の如く電極ｇ２１の形成が成
される。これらは、メルト工程を鮭て配線用のアルミニ
ウム（ムｌ）等が絶縁層上にバターニングされる。In the next step, a 16-thick oxide film 17 is grown, and through it, ion implantation is performed. After arsenic ion implantation, the thin oxide film 17 is removed,
Furthermore, as shown in Figure 2 (6), an insulating layer 2θ of P2O etc.
is formed, and the electrode g21 is formed as shown in FIGS. In these cases, aluminum (silver) for wiring is patterned onto the insulating layer using a melt process.
本発明を工上述の如（構成させたのでゲート績成長後Ｋ
ＲＯＭ部分を一度すべてデプリーシ日ソ化した後に射
影飛程の犬ぎいボロン（ＩＩ）をゲート電極が出来上っ
た後６Ｃ選択的にイオン注入し、エンハンスメン） Ｔ
ｒ を形成し、 ＲＯＭを完成するために手智が短く
、高集積化出来る特徴な有すΦ。Since the present invention was constructed as described above, K after gate performance growth
After the ROM part was completely depleted, 6C selective ions were implanted with projective range boron (II) after the gate electrode was completed, and enhancement was performed.
Φ has the characteristics of short length and high integration in order to form r and complete ROM.
本発明は、ボロンと燐の不純物が混合されΦためモビリ
ティでは問題はあるがＲＯＭ等に用いる場合には、これ
ら問題は大きな問題とはならない。In the present invention, since impurities of boron and phosphorus are mixed Φ, there is a problem with mobility, but when used in ROM etc., these problems do not become a big problem.
第１図（Ａ）〜ＩＣ）は、従来の輩０８ＦＥＴの裏作工
程を説明するための仙断面図、第２図（転）〜（転）は
本発明のＭＯ８ＦＩＴ Ｉ′）製作工程を１！明するた
めの側断面図である。
！・−・基板、２・・・酸化膜、３−ゲート酸化ｌｌ［
，９−・・窒化シリコン展、１１−レジスト層。
１２轡ポｅン層、１６−・・ポリシリコン層。
２Ｏ−ＰＥＧ等の絶縁層、１３−６層、１５・・・履め
込み多結晶シリコンコンタクト窓。
１７ 、１８°″″酸化膜、
１９・−・ソースおよびドレイン領域。
２１・・・電接コンタクト窓
特許出願人 富士通株式会社
’％−＋＋−％
ＯＬＬＪＬＬFigures 1 (A) to IC) are sacral cross-sectional views for explaining the back production process of the conventional MO8FET, and Figures 2 (Rotation) to (Rotation) show the production process of the MO8FIT I') of the present invention. FIG. ! ...Substrate, 2...Oxide film, 3-Gate oxide ll[
, 9-...Silicon nitride layer, 11-Resist layer. 12 - polysilicon layer, 16 - polysilicon layer. Insulating layer such as 2O-PEG, 13-6 layer, 15... Inserted polycrystalline silicon contact window. 17, 18°″″ oxide film, 19--source and drain region. 21...Electric contact window patent applicant Fujitsu Ltd.'%-++-% OLLJLL
Claims (1)
体基板に注入することにより、デプリーション化する工
程と、ゲート電極形成後に射影飛程の大きい不純物を選
択的に注入することにより、該デプリーション化したト
ランジスタを選択的にエンハンスメント化する工程を含
むこと′４を特徴とする半導体装置の製造方法。After the formation of the gate oxide film, the depletion process is performed by implanting an impurity with a small projection range into the semiconductor substrate, and after the formation of the gate electrode, the depletion process is performed by selectively implanting an impurity with a large projection range. 4. A method of manufacturing a semiconductor device, comprising the step of selectively enhancing transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56155284A JPS5856468A (en) | 1981-09-30 | 1981-09-30 | Manufacture of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56155284A JPS5856468A (en) | 1981-09-30 | 1981-09-30 | Manufacture of semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5856468A true JPS5856468A (en) | 1983-04-04 |
Family
ID=15602531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56155284A Pending JPS5856468A (en) | 1981-09-30 | 1981-09-30 | Manufacture of semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5856468A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6480069A (en) * | 1987-09-21 | 1989-03-24 | Hitachi Ltd | Semiconductor storage device and manufacture thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5333076A (en) * | 1976-09-09 | 1978-03-28 | Toshiba Corp | Production of mos type integrated circuit |
| JPS5534443A (en) * | 1978-08-31 | 1980-03-11 | Fujitsu Ltd | Preparation of semiconductor memory storage |
-
1981
- 1981-09-30 JP JP56155284A patent/JPS5856468A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5333076A (en) * | 1976-09-09 | 1978-03-28 | Toshiba Corp | Production of mos type integrated circuit |
| JPS5534443A (en) * | 1978-08-31 | 1980-03-11 | Fujitsu Ltd | Preparation of semiconductor memory storage |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6480069A (en) * | 1987-09-21 | 1989-03-24 | Hitachi Ltd | Semiconductor storage device and manufacture thereof |
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