JPH0131307B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuits, and more particularly to memory integrated circuits.

Conventional arrangements of MOS transistors in memory cells do not involve aligning them in one direction, and the number of contacts is usually twice the number of MOS transistors, and the pattern is determined by the spacing between metal wires within the same cell. It has been difficult to create a large capacity memory because there is a lot of wasted area and the memory area cannot be reduced.

SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned problems and to make a large capacity memory possible by obtaining memory cells with a small area.

The integrated circuit according to the present invention has a plurality of memory cells, and is characterized in that two wiring layers are provided in the direction of address lines, and one of the wiring layers is used as the address wiring. According to the present invention, it is possible to obtain a memory integrated circuit in which the area of each cell is small and a large number of memory cells are integrated with high density.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A MOS integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings.

The dynamic memory cell circuit includes sources 102, 105, 108, drains 101, 106, 109, and gates 103, 10, respectively, as shown in FIG.
Three MOS transistors with 4,107
Q ₁ , Q ₂ , Q ₃ and write line 110, read line 1
11 and an address line 112.

2 to 4 are diagrams showing a first embodiment of the MOS integrated circuit according to the present invention. Expressed in circuit symbols, the three-element MOS transistor of FIG. 1 constitutes a dynamic memory cell. .

FIG. 2 is a diagram showing the state before the formation of the first layer metal wiring, in which the read line diffusion region 201, the ground line diffusion region 202, the write line diffusion region 203, the source region 204 of the Q ₃ transistor (also the drain region of the Q ₂ transistor) ^Q1 transistor source region 205, _Q3 transistor gate region 206, _Q2 transistor gate region 207,
It consists of a gate region 208 of the Q ₁ transistor and a contact window 209 of the source region of the Q ₁ transistor.

Figure 3 is a diagram showing the state before forming the second layer metal wiring, and shows the gate metal wiring 31 of the _Q3 transistor.
0, _Q2 transistor gate metal wiring 311,
_Q1 transistor gate metal wiring 312 and through-hole contact window 31 to second layer wiring
Insulating layer 31 deposited on all surfaces except 4,315
It is composed of 3.

FIG. 4 shows a final plan view of an embodiment of the MOS integrated circuit according to the present invention in which a second layer wiring is formed on the state shown in FIG. A ground line diffusion region 402 (also serves as the source of _{the Q 2 transistor} ), a write line diffusion region 403 (also serves as the drain region of the Q ₁ transistor), a drain region 401, a source region 404,
MOS transistor _Q3 consisting of a gate region 406, a gate metal wiring 410, and a drain region 404
(also serves as the source of Q ₁ ), consists of a source region 402, a gate region 407, and a gate metal wiring 411
A MOS transistor Q ₂ , a MOS transistor Q ₁ consisting of a source region 405, a drain region 403, a gate region 408, and a gate metal wiring 412 having one contact window 409 inside, and through-hole contact windows 414 and 415 are arranged in a plane. The MOS transistor is composed of an insulating film 413 between the first and second layers, and a second address metal wiring 416, and the line connecting the centers of the source regions and the centers of the drain regions of these three MOS transistors is almost in a straight line. It is located in

According to the MOS integrated circuit according to the present invention, the lines connecting the centers of the source regions and the centers of the drain regions of each MOS transistor element constituting the memory cell are all aligned substantially in a straight line, so that the transistors in the memory cell can be arranged in two directions. Since it is located under the layer address wiring, the area of the memory cell is much smaller than that of a conventional memory cell. This second to fourth
The memory area in the figure is the area surrounded by x marks in the figure. Furthermore, since only one contact window is required for each memory cell, wasted portions of the diffusion region can be reduced.

Furthermore, since the number of metal wires in the bit direction within the memory cell is one, the spacing between the metal wires and the area occupied by the metal wires are reduced.

Dimensionally, the area of the memory cell shown in Figure 4 is extremely small at 22.5 microns x 112.5 microns, and is currently thought to be made using a special technology called silicon gate to minimize the size of the memory cell. Even compared to the memory 1103, it is less than 50%. Compared to MOS memory cells using conventional technology, it is a fraction to one-tenth that of MOS memory cells.

[Brief explanation of drawings]

The figures are diagrams for explaining the principle and structure of the present invention. Figure 1 is a diagram showing a 1-bit circuit diagram of a memory cell, and Figures 2 to 4 are diagrams showing a 1-bit circuit on a semiconductor substrate. FIG. 3 shows an embodiment of a MOS integrated circuit according to the present invention patterned on top. _Q1 to _Q3 : Transistors.

Claims (1)

[Claims] 1. In an integrated circuit having a plurality of memory cells, a first wiring layer and a second wiring layer are provided to overlap in the address line direction, and one of the wiring layers is used as the address line. integrated circuit.