JPS571253A - Integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the area of an IC having plural memory cells by a method wherein wirings of the first layer and the second layer are accumulated in the direction of an address line, and either of the layers is made as the address line. CONSTITUTION:A layer 401 for drain to be used both as a write line and a transistor (Tr)Q3, a source 402 to be used both as an earthing line and a TrQ2, a drain 403 to be used both as a write line and a TrQ1 are extended in the direction of bit, and the MOSTrQ3 consisted of a gate region 406, a gate metal wiring 410, a source 404, the MOSTrQ2 consisted of a drain 404 (a source of the Q1), a gate 407, a gate wiring 411, and the MOSTrQ1 consisted of a source 405 having an electrode window 400, a gate region 408, a gate wiring 412 are arranged, penetrating connecting holes 414, 415 are provided in an interlayer insulating film 413, and the address metal wiring 416 is provided on the second layer. The center of the sources and drains of the Tr's Q1-Q3 are arranged on a nearly straight line. By this constitution, because the transistors in the memory cells come under the address wiring of the second layer, the area of the cells (inside of x marks) become extremely small and the connecting hole can get along with one hole per cell, so that useless part of the diffusion region can be reduced.