JPS5457881A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5457881A
JPS5457881A JP12427277A JP12427277A JPS5457881A JP S5457881 A JPS5457881 A JP S5457881A JP 12427277 A JP12427277 A JP 12427277A JP 12427277 A JP12427277 A JP 12427277A JP S5457881 A JPS5457881 A JP S5457881A
Authority
JP
Japan
Prior art keywords
diffusion layer
polysi
channel
wiring
metal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12427277A
Other languages
Japanese (ja)
Inventor
Matsuo Ichinose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP12427277A priority Critical patent/JPS5457881A/en
Publication of JPS5457881A publication Critical patent/JPS5457881A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To increase the integration density of a metal GateMOS integrated circuit with the number of contact holes reduced, by using a PolySi wiring for the connection between a metal wiring and diffusion layer, etc.
CONSTITUTION: Inside N-type silicon substrate 1, P- diffusion layer 2 and either P+ diffusion layer 3 for a P-channel source and drain or a N+ diffusion layer for a N-channel source and drain are formed, and field oxidized film 5 and Gate oxidized film 6 are formed on it. Further, Mo metal wiring 7 and a PolySi layer are stacked in sequence, and P-channel and N-channel diffusion treatments are made respectively. Then, PolySi wiring 8 is formed. In this way, the diffusion layer and metal wiring are connected together by PolySi so as to reduce the number of contact holes, thereby reducing the area of wirings
COPYRIGHT: (C)1979,JPO&Japio
JP12427277A 1977-10-17 1977-10-17 Semiconductor device Pending JPS5457881A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12427277A JPS5457881A (en) 1977-10-17 1977-10-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12427277A JPS5457881A (en) 1977-10-17 1977-10-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5457881A true JPS5457881A (en) 1979-05-10

Family

ID=14881222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12427277A Pending JPS5457881A (en) 1977-10-17 1977-10-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5457881A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63204628A (en) * 1987-02-19 1988-08-24 Nec Corp Semiconductor integrated circuit device
US5326713A (en) * 1992-09-04 1994-07-05 Taiwan Semiconductor Manufacturies Company Buried contact process

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5297688A (en) * 1976-02-10 1977-08-16 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5297688A (en) * 1976-02-10 1977-08-16 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63204628A (en) * 1987-02-19 1988-08-24 Nec Corp Semiconductor integrated circuit device
US5326713A (en) * 1992-09-04 1994-07-05 Taiwan Semiconductor Manufacturies Company Buried contact process

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