JPH10178110A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a layout structure of a semiconductor storage device whose element area is reduced, by using a trench element separation technique and such a newest process technique as stacked via structure, to obtain a metal wiring layer structure of three layers or more. SOLUTION: In a P-well region and an N-well region in which an inverter, constituting a SRAM cell (static random access memory), is formed, the P-well region is divided into two sections and they are placed on both sides of the N-well region, and boundary lines BL1 and BL2 are so formed as to run in parallel with bit lines BL,/BL. By employing such a layout as above, diffusion layers ND1 and ND2 in the P-well region are provided with a simple form with no bent part, and a cell area is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a static random access memory (SRAM) having a CMOS structure.
ss memory) This relates to cell layout.

[0002]

2. Description of the Related Art An SRAM having a CMOS configuration is widely used as a storage device mounted on a logic IC. The most basic storage element constituting this storage device is a one-port memory cell (SRAM cell) shown in FIG. 16, which is composed of six transistors.

The inverter IN2 shown in FIG. 17 showing an equivalent circuit is constituted by the P-channel MOS transistor P1 and the N-channel MOS transistor N1, and the P-channel MOS transistor P2 and the N-channel MO transistor
The inverter IN1 is constituted by the S transistor N2. As described above, the inverters IN1 and IN2 have a relationship in which the input / output terminals are cross-connected to each other. The output terminal of the inverter IN1 and the input terminal of the inverter IN2 are
The input terminal of the inverter IN1 and the output terminal of the inverter IN2 are connected to the bit line / BL via the transfer gate transistor N4, and are connected to the bit line BL via the transfer gate transistor N3.
Further, the gates of the transistors N3 and N4 are connected to the word line W
L.

[0004] Such a 6-transistor memory cell has
Conventionally, they are arranged in a layout as shown in FIGS. Here, FIG. 10 includes a diffusion layer forming a transistor formed on the substrate surface, a polycrystalline silicon wiring layer formed on the upper surface thereof, and a first metal wiring layer 1 formed on the upper surface thereof. FIG. 11 shows an upper layer including second and third metal wiring layers 2 and 3 formed on the upper surface thereof. Symbols of contacts and via holes used in FIGS. 10 and 11 are shown in FIG.
12A, the symbols of the diffusion layer, the polycrystalline silicon film, and the metal wiring layer 1 used in FIG. 10 are shown in FIG. 12B, and the symbols of the metal wiring layers 2 and 3 used in FIG. ).

In parallel with the word line WL shown in FIG.
P-channel MOS transistor P1 shown in FIG.
Well region forming P2 and P2 and an N-channel type MO
There is a boundary line BL11 with the P-well region forming the S transistors N1 to N4. The upper part of the line AA parallel to the boundary line BL11 is a polycrystalline silicon wiring layer PL11 connected to the gate of the transistor P1 and a polycrystalline silicon wiring layer PL1 connected to the gate of the transistor P2.
2 are arranged in translation symmetry.

Further, below the line AA, a diffusion layer DR11 forming the transistors N1 and N3 and a diffusion layer DR12 forming the transistors N2 and N4 are mirrored on the y-axis orthogonal to the word line WL. Are located in

As is apparent from FIG. 10, in this layout, the ground line GND and the word line WL are connected to the metal wiring layer 3.
, Except that the bit lines BL and / BL are formed by the metal wiring layer 2, and all others are formed by the polysilicon wiring layers PL 11 and PL 12 and the metal wiring layer 1. Also, the polysilicon wiring layers PL11, P11
Since the word line WL constituted by L12 is connected to the word line WL of another memory cell adjacent to across the area of the memory cell, the metal wiring layer 3 is unnecessary in function. Further, the ground line GND can be formed of the metal wiring layer 2 in parallel with the bit lines BL and / BL. Therefore, the layouts shown in FIGS. 10 and 11 can be configured by the polysilicon wiring layers PL11 and PL12 and the metal wiring layers 1 and 2.

In such a conventional layout, design standards (design rules) limited by the process technology are as follows:
It was configured with a minimum area so as to satisfy the following conditions. (A1) The number of metal wiring layers is one or two. (A2) The design criteria for the minimum line width and minimum interval of the metal wiring layer are larger than those of the polycrystalline silicon layer (about twice). (A3) a contact hole which is an opening between the diffusion layer or the polysilicon wiring layer and the metal wiring layer 1;
The first through hole or the first via hole, which is the opening between the metal wiring layer 2 and the first through hole, is prevented from directly overlapping in the vertical direction. Also, the area of the contact hole is
Since it is about twice as large as the minimum line width of a normal metal wiring layer, the cell area is prevented from increasing by not providing many contact holes and through holes in the cell. (A4) There is a boundary between the N-well region and the P-well region between the P-channel MOS transistor and the N-channel MOS transistor. Element isolation is performed by the LOCOS method. Therefore, the separation width between the P well region and the N well region needs to be significantly larger (about four times) than the element separation width of the well region of the same conductivity type.

In order to satisfy the above conditions, the wiring was previously made of a polycrystalline silicon film as much as possible.
In the separation region between the P-well region and the N-well region, it is necessary to effectively use a wasteful region such as performing a cross connection of complicated wiring.

However, due to the recent progress in process technology, the following changes have been made in the design standards.

First, with the practical use of chemical mechanical polishing technology (CMP), the technology for flattening the metal wiring layer has advanced. (B1) Even if the number of metal wiring layers is increased to three or four, There is no significant decrease in yield. (B2) The design criteria for the minimum line width and minimum interval of the metal wiring layer are no different from the polycrystalline silicon layer. (C2) The borderless contact technology has been introduced, and the area of the contact portion can be formed according to the same design standard as the minimum line width of the metal wiring layer. In addition, a stacked via structure in which contact holes and through holes are formed directly on top of each other has become possible.

Further, when performing element isolation, LOCOS
(C1) The separation width between the P-well region and the N-well region is the same conductivity type well region (P-well region and P-well region,
The device isolation width in the N-well region and the N-well region) was almost the same.

With the progress of such process technology,
The layout as shown in FIGS. 10 and 11 cannot be said to have an optimal arrangement. For example, the polycrystalline silicon wiring layers PL11 and PL12 each have a T-shape and are arranged for translation with respect to each other. Further, since the N-channel MOS transistor N1 and the N-channel MOS transistor N3 are arranged so as to be orthogonal to each other, the diffusion layer is bent in an L-shape, which again wastes the cell area.

FIGS. 13 and 14 show an improved layout shown in FIGS. 10 and 11. FIG. The basic arrangements and geometric shapes of the transistors N1 to N4 and P1 to P2 are the same as those in FIGS. The difference is that the polycrystalline silicon layers PL11 and PL12 cross-connected in the layouts shown in FIGS.
In place of the metal wiring layer 2, and the bit lines BL and / BL and the ground line GND are formed by the metal wiring layer 3 with this change. FIG. 13 and FIG.
According to the layout shown in FIG. 4, the area is reduced by about 10% from that shown in FIGS.

However, in the layouts of FIGS. 13 and 14, transistors N1 and N3 and transistor N2
D4 and N4 must be formed in an L-shape, and the cell area is wasted.

[0016]

As described above, the layout of the conventional SRAM cell has a problem that the diffusion layer has a wasteful geometric shape such as an L-shape and the element area is large. Was.

The present invention has been made in view of the above circumstances, and has a three or more metal wiring layer structure using the latest process technology such as a trench device isolation technology and a stacked via structure, so that the device area can be reduced. It is an object of the present invention to provide a layout structure of a semiconductor memory device that can be reduced.

[0018]

A semiconductor memory device according to the present invention comprises a first N-channel MOS transistor and a first P-channel MOS transistor.
A first inverter including a channel type MOS transistor, a second N-channel type MOS transistor, and a second P-channel type MOS transistor, wherein an input terminal is connected to an output terminal of the first inverter; First
A second inverter having an output terminal connected to the input terminal of the inverter, a source connected to the output terminal of the first inverter, a drain connected to the first bit line,
Third N-channel type MO having gate connected to word line
An S transistor, and a fourth N-channel MOS transistor having a source connected to an output terminal of the second inverter, a drain connected to a second bit line, and a gate connected to the word line, The arrangement directions of the source / drain of the first, second, third and fourth N-channel MOS transistors and the first and second P-channel MOS transistors are the first, second,
It is set so as to be parallel to the boundary between the P-well region where the third and fourth N-channel MOS transistors are formed and the N-well region where the first and second P-channel MOS transistors are formed. It is characterized by having.

Here, the P-well region has first and second regions.
And the first and second P-well regions are arranged on both sides of the N-well region where the first and second P-channel MOS transistors are arranged.
The first and third N-channel MOS transistors are formed in the first P-well region, and the second and fourth N-channel MOS transistors are formed in the second P-well region. Good.

Also, a first polysilicon wiring layer used for a gate of the third N-channel MOS transistor, a gate of the first N-channel MOS transistor, and a first P-channel MOS transistor A third polysilicon wiring layer used for the gate of the fourth N-channel type MOS transistor; and a second polysilicon wiring layer used for the gate of the fourth N-channel type MOS transistor. A fourth polysilicon wiring layer used for the gate of the channel type MOS transistor and the gate of the second P-channel type MOS transistor is arranged in parallel, and the first polysilicon wiring layer and the third polysilicon wiring layer are arranged in parallel. Is formed separately from the polycrystalline silicon wiring layer, and is electrically connected to a metal wiring layer forming the word line through a contact. It can have.

The first, second, third and fourth N
Channel type MOS transistor and the first and second P
The arrangement direction of each source / drain of the channel type MOS transistor may be set to be parallel to the bit line.

Alternatively, the second polycrystalline silicon wiring layer and the third polycrystalline silicon wiring layer are arranged so as to be aligned in a straight line along the word line direction.
The polycrystalline silicon wiring layer and the fourth polycrystalline silicon wiring layer may be arranged in a straight line along the word line direction.

The first N-channel MOS transistor and the third N-channel MOS transistor are:
Formed in the same diffusion layer in the first P-well region;
The second N-channel MOS transistor and the fourth
Of the N-channel MOS transistor
It may be formed in the same diffusion layer in the well region.

The first and third N-channel type MOs
The S transistor and the first P-channel MOS transistor and the second and fourth N-channel MOS transistors and the first P-channel MOS transistor are point-symmetric with respect to the center of the memory cell. It is desirable to arrange them so that

The first and second bit lines are connected to the first and second bit lines.
A power supply line connected to the source of the second P-channel MOS transistor is formed of a second metal wiring layer, and connected to the word line and the sources of the first and second N-channel MOS transistors. The ground line may be formed of a third metal wiring layer.

A first polysilicon wiring layer used for a gate of the third N-channel MOS transistor, a gate of the first N-channel MOS transistor, and a gate of the first P-channel MOS transistor A third polycrystalline silicon wiring layer used for the gate of the fourth N-channel MOS transistor, and a second polycrystalline silicon wiring layer used for the gate of the fourth N-channel MOS transistor. A fourth polycrystalline silicon wiring layer used for the gate of the MOS transistor and the gate of the second P-channel type MOS transistor is arranged in parallel, and the word line is separated into first and second metal wiring layers. The first polysilicon wiring layer and the third polysilicon wiring layer are formed separately, and the metal wiring layer Through Ntakuto, the first,
The layout can also be made so as to be electrically connected to the second metal wiring layers.

First and second sense amplifiers are independently connected to the first and second bit lines, respectively. At the time of writing, the first and second word lines in the same cell are simultaneously connected. At the time of selection and reading, the first and second word lines independently select different cells, and the first and second sense amplifiers pass the respective cells through the first and second bit lines. It is also possible to output the data read from the.

In any of the above inventions, the transistor between the first and second inverters and the first and second bit lines has N
Although a channel type MOS transistor is used, a configuration using a P-channel type MOS transistor may be employed.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIGS. 1 and 2 show layouts of the SRAM cells constituting the semiconductor memory device according to the first embodiment of the present invention. FIG. 1 shows a diffusion layer formed on the surface of a semiconductor substrate, a polycrystalline silicon film formed on the upper surface thereof, and a base including a metal wiring layer 1, and FIG. 2 shows a metal wiring layer 2 and a metal wiring layer 2 formed on the upper surface thereof. 3 indicates an upper layer including 3. Various symbols in FIG. 3A are cell boundaries, contacts and vias 1 used in FIGS.
3B, the symbol in FIG. 3B is a diffusion layer, a polycrystalline silicon film, a metal wiring layer 1, and the symbol in FIG.
3 are shown.

As shown in FIG. 1, a P-channel MOS is provided at the center.
An N-well region in which transistors P1 and P2 are formed is arranged, a P-well region in which N-channel MOS transistors N1 and N3 are formed on both sides thereof, and a P-well region in which N-channel MOS transistors N2 and N4 are formed. Is arranged.

The gate of the word line transistor N3 connected to the word line WL and the gate of the transistor N4 are
It is composed of separated polysilicon wiring layers,
The word lines WL formed of the metal wiring layer 3 are separately connected via stacked vias. As shown in FIG. 2, the bit lines BL and / BL are
Are formed separately. The power supply line Vdd is formed in a central portion between the bit lines BL and / BL by a metal wiring layer 2 in parallel with the bit lines. The word line WL is formed of a metal wiring layer 3 in a direction orthogonal to the bit lines BL and / BL, and the ground line GND is formed of two metal wiring layers 3 parallel to both sides of the word line WL. In addition, the contact to the substrate in the P well region is a contact + via 1+
The stacked via structure including the via 2 electrically connects the grounded metal wiring layer 3 to the diffusion layer in the P-well region.

FIGS. 10 and 11 or FIGS. 13 and 14
In the conventional layout shown in FIG. 1, boundary lines BL11 and BL12 between the N-well region and the P-well region
It ran perpendicular to L and / BL. On the other hand, the layout according to the first embodiment is characterized in that the boundary lines BL1 and BL2 between the N-well region and the P-well region run parallel to the bit lines BL and / BL.
Thus, the P-channel type MOS transistor P1 and the N-channel type MOS transistor N1 forming the inverter with the boundary between the well regions having different conductivity types are positioned in parallel with the N-channel type MOS transistor N3 of the transfer gate transistor. Can be arranged. As a result, the N-type diffusion layer ND1 in the P well region where the transistors N1 and N3 are formed and the N-type diffusion layer ND2 where the transistors N2 and N4 are formed are parallel to the bit lines BL and / BL without bending. Therefore, it is possible to prevent the useless area from being generated.

Further, in this embodiment, one of the inverter and the transfer gate transistor N3 composed of the transistor P1 and the transistor N1 and the other inverter and the transfer gate transistor N4 composed of the transistor P2 and the transistor N2 are connected to the center of the SRAM cell. There is also a feature in that they are arranged point-symmetrically with respect to. By arranging in this way, the transistors P1, P2,
It is not necessary to connect the wiring connecting the gates and drains of N1 and N2 so as to cross the space, and the wiring area can be reduced.

The polysilicon wiring layer PL1 of the transistors N1 and P1 and the polysilicon wiring layer PL2 of the transistor N4 are arranged on a straight line parallel to the word line WL, and similarly, the polysilicon wiring layers of the transistors N3 and P2 are arranged. The wiring layer PL2 and the polysilicon wiring layer PL4 of the transistor N2 can be arranged on a straight line in parallel with the word line WL. That is, all the polysilicon wiring layers PL1 to PL4 and the metal wiring layers 2 and 3 are parallel,
The diffusion layers ND1 and ND2 are arranged so as to be orthogonal to the diffusion layers, and the formation of the bent portion which has existed in the related art is unnecessary.

By the way, in this layout, as shown in FIG. 1, two isolation regions exist between two P-well regions and N-well regions. However, by using the trench isolation technology, the isolation width between well regions of different conductivity types can be reduced to approximately the same as the isolation width between well regions of the same conductivity type. An increase in area is suppressed. As a result, according to the present embodiment, about 35 times more than the conventional case shown in FIGS.
% Area can be reduced.

According to the first embodiment, not only the cell area can be reduced, but also the effect of reducing noise can be obtained for the following reasons. In the layout according to the present embodiment, the length of the cell in the horizontal direction (x direction), that is, the length in the word line WL direction is equal to the vertical direction (y direction).
, That is, the bit lines BL and / BL are relatively long. This facilitates the layout of the sense amplifiers arranged between the cells in the x-direction pitch and connected to the bit lines BL and / BL.

Further, the cell shape is relatively smaller than x in the y direction.
The length in the direction reduces the number of cells connected in the word line WL direction as compared with the conventional layout. As the number of cells connected to one word line is smaller, the cell current flowing at the time of reading decreases. Therefore, according to the present embodiment, power consumption can be reduced.

In a logic IC, a bus line is often run on a memory cell by using a fourth metal wiring layer. For the following reasons, the bit line BL and / or the bit line per cell are used.
An effect is also obtained that a large number of wiring resources in the BL direction can be obtained. That is, when a bus line runs on a memory cell, if the bit lines BL, / BL and the bus line are arranged so as to run a long distance in parallel up and down, the signal change of the bus line becomes capacitive coupling noise and the bit line becomes This overlaps with the lines BL and / BL, causing a malfunction. In the present embodiment, such a malfunction can be prevented by disposing the bus line in parallel with the bit lines BL and / BL by removing right above the bit lines BL and / BL. Also, the bit lines BL, /
BL is made up of a metal wiring layer 2, and a ground line GND made of a metal wiring layer 3 and a word line WL are present between the BL and a bus line made up of a metal wiring layer 4 running on a memory cell. , Which acts as a metal shielding layer. For this reason, it is possible to reliably prevent the occurrence of a malfunction.

The layout of the semiconductor memory device according to the second embodiment of the present invention is as shown in FIGS. 4 and 5, and the symbols used are shown in FIGS. 6 (a) to 6 (c).

The present embodiment differs from the first embodiment in that a region for making contact from the word line WL formed by the metal wiring layer 3 to the polysilicon wiring layer is provided in the P-well region. In addition, the difference is that the ground line GND and the power supply line Vdd made of the metal wiring layer 2 are provided in parallel with the bit lines BL and / BL. The layout according to this embodiment is suitable when the isolation width of the well region is relatively larger than the element isolation width. In addition to the above-described effects of the first embodiment, this embodiment has the following advantages. Specific effects can be obtained.

The power supply line Vdd and the ground line GND are connected to the word line WL.
And the current flowing through all the cells connected to the selected word line is one power line Vdd
And flows into the ground line GND. On the other hand, as in the present embodiment, the power supply line Vdd and the ground line GND are connected to the bit line BL.
And BL in parallel, the current flowing to the power supply line Vdd and the ground line GND during reading or writing of a cell can be limited to one cell. As a result,
According to the second embodiment, it is possible to increase the operation margin for the electromigration and the voltage drop of the power supply line Vdd and the ground line GND as compared with the first embodiment.

Next, the layout of the semiconductor memory device according to the third embodiment of the present invention will be described with reference to FIGS. Compared with the second embodiment, two word lines WL1 and WL2 constituted by the metal wiring layer 3 are provided, and the gate of the transistor N3 and the transistor N3 are connected.
4 is connected to different word lines WL1 and WL2. Thus, the word line WL
Provision of two lines 1 and 2 makes it possible to independently control transistors N3 and N4 in one cell, and to transfer data from different cells to one set of bit lines BL and / BL. It becomes possible to read. Therefore, by connecting one sense amplifier to each of the bit line BL and the bit line / BL, it is possible to perform a single-ended read but as a two-port memory. At the time of writing, the same cell is selected by the word lines WL1 and WL2 to operate as a one-port memory. In this manner, in the present embodiment, a two-port memory can be realized at the time of reading, and a one-port memory can be realized at the time of writing, with the same cell area as a normal one-port memory.

The above embodiments are merely examples and do not limit the present invention. For example, the first
In the semiconductor memory devices according to the third to third embodiments, as shown in FIGS. 16 and 17, the transfer gate transistor is an N-channel type MOS transistor N.
3 and N4. However, FIGS. 21 and 2
2, the transfer gate transistor is composed of P-channel MOS transistors P3 and P4, and one SRAM cell is composed of four P-channel MOS transistors P1 to P4 and two N-channel MOS transistors N1 and N2. You may. In this case, the layout may be such that the P-well region is arranged at the center of the base, two N-well regions are arranged on both sides thereof, and the power supply line Vdd and the ground line GND are replaced on the upper ground.

For example, the layout in the case where the transfer gate transistor in the first embodiment is constituted by P-channel MOS transistors P3 and P4 is as shown in FIGS. 18 and 19. On the upper ground, N-channel MOS transistors N1 and N2 are formed in one P-well region, and P-channel MOS transistors P1 and P3 are formed on both sides thereof.
The N-well region in which the N.sub.4 is formed is arranged, and the power supply line Vdd and the ground line GND are exchanged in the base.
Similarly, also in the second and third embodiments, the transfer gate transistor can be constituted by a P-channel MOS transistor.

[0045]

As described above, according to the semiconductor memory device of the present invention, the boundary between the P-well region and the N-well region where the inverter constituting the memory cell is formed is arranged in parallel with the bit line. Thus, the shape of the diffusion layer in the P-well region or the N-well region and the shape of the cross-connecting portion of the two inverters can be simplified without a bent portion, and the cell area can be reduced. is there.

[Brief description of the drawings]

FIG. 1 is a plan view showing a base layout in a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing an upper layout in the semiconductor memory device;

FIG. 3 is an explanatory diagram showing various symbols of contacts, vias, diffusion layers, and wiring layers used in FIGS. 1 and 2;

FIG. 4 is a plan view showing a base layout in a semiconductor memory device according to a second embodiment of the present invention;

FIG. 5 is an exemplary plan view showing an upper layout in the semiconductor memory device;

FIG. 6 is an explanatory diagram showing various symbols of contacts, vias, diffusion layers, and wiring layers used in FIGS. 4 and 5;

FIG. 7 is a plan view showing a layout of a base in a semiconductor memory device according to a third embodiment of the present invention.

FIG. 8 is a plan view showing an upper layout in the semiconductor memory device.

FIG. 9 is an explanatory diagram showing various symbols of contacts, vias, diffusion layers, and wiring layers used in FIGS. 7 and 8;

FIG. 10 is a plan view showing a layout of a base in a conventional semiconductor memory device.

FIG. 11 is an exemplary plan view showing an upper layout in the semiconductor memory device;

FIG. 12 is an explanatory diagram showing various symbols of contacts, vias, diffusion layers, and wiring layers used in FIGS. 10 and 11;

FIG. 13 is a plan view showing a layout of a base in another conventional semiconductor memory device.

FIG. 14 is a plan view showing an upper layout in the semiconductor memory device.

FIG. 15 is an explanatory view showing various symbols of contacts, vias, diffusion layers, and wiring layers used in FIGS. 13 and 14;

FIG. 16 is a circuit diagram showing a configuration of an SRAM cell.

FIG. 17 is a circuit diagram showing an electrically equivalent circuit configuration of the SRAM cell.

FIG. 18 is a plan view showing a layout of a base in a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 19 is a plan view showing an upper layout in the semiconductor memory device.

FIG. 20 is an explanatory diagram showing various symbols of contacts, vias, diffusion layers, and wiring layers used in FIGS. 18 and 19;

FIG. 21 is a circuit diagram showing a circuit configuration of an SRAM cell in a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 22 is a circuit diagram showing an electrically equivalent circuit configuration of the SRAM cell.

[Explanation of symbols]

 BL1 to BL8 Bit line WL, WL1, WL2 Word line GND Ground line Vdd Power supply line N1 to N4 N channel type MOS transistor P1 to P4 P channel type MOS transistor IN1, IN2 Inverter ND1, ND2 Diffusion layer PL1, PL2 Polycrystalline silicon wiring layer

Claims (11)

[Claims] A first inverter including a first N-channel MOS transistor and a first P-channel MOS transistor; a second N-channel MOS transistor and a second P-channel MOS transistor; A second inverter having an input terminal connected to an output terminal of the first inverter, and an output terminal connected to an input terminal of the first inverter; and a source connected to an output terminal of the first inverter. And
A third N-channel MOS transistor having a drain connected to the first bit line and a gate connected to the word line; a source connected to an output terminal of the second inverter;
A fourth N-channel MOS transistor having a drain connected to a second bit line and a gate connected to the word line; the first, second, third, and fourth N-channel MOS transistors And the arrangement direction of the source / drain of each of the first and second P-channel MOS transistors is the same as that of the first, second, third and fourth N-channel MOS transistors.
A semiconductor memory, which is set so as to be parallel to a boundary between a P well region in which an S transistor is formed and an N well region in which the first and second P-channel MOS transistors are formed. apparatus. 2. The P-well region comprises first and second well regions. The first and second well regions are provided on both sides of an N-well region in which the first and second P-channel MOS transistors are arranged. Two P-well regions, the first and third N-channel MOS transistors are formed in the first P-well region, and the second and fourth P-well regions are formed in the second P-well region. 2. The semiconductor memory device according to claim 1, wherein an N-channel MOS transistor is formed. 3. A first polysilicon wiring layer used for a gate of said third N-channel MOS transistor, a gate of said first N-channel MOS transistor, and said first P-channel MOS transistor. A third polysilicon wiring layer used for the gate of the fourth N-channel type MOS transistor; and a second polysilicon wiring layer used for the gate of the fourth N-channel MOS transistor. A fourth polysilicon wiring layer used for the gate of the channel type MOS transistor and the gate of the second P-channel type MOS transistor is arranged in parallel, and the first polysilicon wiring layer and the third polysilicon wiring layer are arranged in parallel. Formed separately from the polysilicon wiring layer and electrically connected to the metal wiring layer forming the word line through a contact. The semiconductor memory device according to claim 3, wherein. 4. The arrangement of the source / drain of each of said first, second, third and fourth N-channel MOS transistors and said first and second P-channel MOS transistors is directed to said bit line. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is set so as to be parallel to. 5. The first polycrystalline silicon wiring layer, wherein the second polycrystalline silicon wiring layer and the third polycrystalline silicon wiring layer are arranged so as to be aligned in a straight line along the word line direction. 4. The semiconductor memory device according to claim 3, wherein the layer and the fourth polysilicon wiring layer are arranged so as to be aligned in a straight line along the word line direction. 6. The first N-channel MOS transistor and the third N-channel MOS transistor,
The second N-channel MOS transistor and the fourth N-channel MOS transistor are formed in the same diffusion layer in the first P-well region;
Of the N-channel MOS transistor
6. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is formed in the same diffusion layer in the well region. 7. The first and third N-channel MOS transistors and the first P-channel MOS transistor, and the second and fourth N-channel MOS transistors and the first P-channel MOS transistor. 7. The semiconductor memory device according to claim 1, wherein the transistor is arranged so as to have a point-symmetric relationship with respect to a center of the memory cell. 8. The first and second bit lines and the first and second bit lines.
A power supply line connected to the source of the second P-channel MOS transistor is constituted by a second metal wiring layer, and connected to the word line and the sources of the first and second N-channel MOS transistors. 8. The semiconductor memory device according to claim 5, wherein the ground line is formed by a third metal wiring layer. 9. A first polysilicon wiring layer used for a gate of said third N-channel MOS transistor, a gate of said first N-channel MOS transistor, and said first P-channel MOS transistor A third polysilicon wiring layer used for the gate of the fourth N-channel type MOS transistor; and a second polysilicon wiring layer used for the gate of the fourth N-channel MOS transistor. A fourth polysilicon wiring layer used for a gate of the channel type MOS transistor and a gate of the second P-channel type MOS transistor is arranged in parallel, and the word line is formed of a first and a second metal wiring layer. The first polycrystalline silicon wiring layer and the third polycrystalline silicon wiring layer are formed separately, and the metal wiring layer Via contact, said first, claim 8, wherein each be electrically connected to the second metal interconnection layer
13. The semiconductor memory device according to claim 1. 10. The first and second sense amplifiers are independently connected to the first and second bit lines, respectively. At the time of writing, the first and second word lines in the same cell are written. Are simultaneously selected, and at the time of reading, the first and second word lines independently select different cells, and are respectively supplied from the first and second sense amplifiers via the first and second bit lines. 10. The semiconductor memory device according to claim 9, wherein data read from said cell is output. 11. A first transistor including a first N-channel MOS transistor and a first P-channel MOS transistor.
And a second N-channel MOS transistor and a second P-channel MOS transistor, wherein an input terminal is connected to an output terminal of the first inverter, and an output terminal is connected to an input terminal of the first inverter. A third inverter having a drain connected to the output terminal of the first inverter, a source connected to the first bit line, and a gate connected to the word line; A MOS transistor; a fourth P-channel MOS transistor having a drain connected to an output terminal of the second inverter, a source connected to a second bit line, and a gate connected to a word line; The source of each of the first and second N-channel MOS transistors and the first, second, third and fourth P-channel MOS transistors The arrangement direction of the drain and the drain is such that the P-well region in which the first and second N-channel type MOS transistors are formed and the N-type in which the first, second, third and fourth P-channel type MOS transistors are formed. A semiconductor memory device which is set so as to be parallel to a boundary line with a well region.