JP2013214776A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up access time in a multi-port SRAM.SOLUTION: Regarding a P-well region and an N-well region NW formed with a pair of CMOS inverters that constitute a multi-port SRAM cell, the P-well region is divided into two P-well regions PW1 and PW2. The two P-well regions are formed on two sides of the N-well region NW, so that boundaries between the regions are parallel to bit lines. A pair of access gates N3 and N5 and a pair of access gates N4 and N6 are formed in the two divided P-well regions, respectively, thereby, length of the bit lines can be made shorter, and wiring capacity can be reduced.

Description

  The present invention relates to a semiconductor memory device, and more particularly to a layout of a CMOS multi-port SRAM (Static Random Access Memory) cell.

  In recent years, as electronic devices become lighter, thinner and smaller, there is an increasing demand for realizing the functions of these devices at high speed. In such an electronic device, it is indispensable to mount a microcomputer now, and in the configuration of the microcomputer, it is indispensable to mount a large-capacity and high-speed memory. In addition, with the rapid spread of personal computers and higher performance, there is a need to increase the capacity of cache memory in order to realize faster processing. That is, the RAM used by the CPU when executing a control program or the like is required to be increased in speed and capacity.

  As this RAM, a DRAM (Dynamic RAM) and an SRAM are generally used. However, an SRAM is usually used for a portion requiring high-speed processing such as the above-described cache memory. As the structure of the SRAM, a high resistance load type composed of four transistors and two high resistance elements and a CMOS type composed of six transistors are known. In particular, a CMOS SRAM has a high reliability because a leakage current at the time of data retention is very small, and has become a mainstream at present.

  Generally, reducing the element area of a memory cell means not only miniaturization of the memory cell array but also high speed. Therefore, conventionally, various layouts have been proposed for the memory cell structure in order to realize faster operation of the SRAM.

  For example, according to the “semiconductor memory device” disclosed in Japanese Patent Application Laid-Open No. 10-178110, the boundary line between the P well region and the N well region where the inverter constituting the memory cell is formed is arranged in parallel to the bit line. Therefore, the shape of the diffusion region in the P well region or the N well region and the shape of the cross connection portion of the two inverters are simplified without a bent portion, and as a result, the cell area can be reduced.

  21 and 22 are layout diagrams of the “semiconductor memory device” disclosed in Japanese Patent Laid-Open No. 10-178110. In particular, FIG. 21 shows a base including a diffusion region formed on the surface of a semiconductor substrate, a polycrystalline silicon film formed on the upper surface thereof, and a first metal wiring layer, and FIG. 22 is formed on the upper surface thereof. Further, the upper land including the second and third metal wiring layers is shown.

  As shown in FIG. 21, this memory cell has an N well region in which P channel type MOS transistors P101 and P102 are formed in the center, and P channel in which N channel type MOS transistors N101 and N103 are formed on both sides thereof. A well region and a P well region in which N channel type MOS transistors N102 and N104 are formed are arranged.

  Here, P-channel MOS transistors P101 and P102 and N-channel MOS transistors N101 and N102 constitute a cross-connected CMOS inverter, that is, a flip-flop circuit, and N-channel MOS transistors N103 and N104 are It corresponds to an access gate (transfer gate).

  As shown in FIG. 22, bit lines BL and / BL are separately formed as second metal wiring layers, and are connected to one of the semiconductor terminals of lower access gate MOS transistors N103 and N104, respectively. The power supply line Vdd is formed in the center between the bit lines BL and / BL as a second metal wiring layer in parallel with the bit line, and is connected to one of the semiconductor terminals of the lower P-channel MOS transistors P101 and P102. Connected. Further, word line WL is formed as a third metal wiring layer in a direction perpendicular to bit lines BL and / BL, and is connected to the gates of lower N-channel MOS transistors N103 and N104. The ground line GND is formed as two third metal wiring layers in parallel on both sides of the word line WL.

  As a result of forming the memory cell in such a layout, an N-type diffusion region in the P-well region where the MOS transistors N101 and N103 are formed and an N-type diffusion region where the MOS transistors N102 and N104 are formed are connected to the bit line. It can be formed linearly in parallel with BL and / BL, and generation of useless areas can be prevented.

  Further, since the length in the horizontal direction of the cell, that is, the length in the word line WL direction is relatively longer than the length in the vertical direction, that is, the length of the bit lines BL and / BL, the bit lines BL and / The layout of the sense amplifier connected to BL is facilitated, the number of cells connected to one word line is reduced, and the cell current flowing at the time of reading, that is, power consumption can be reduced.

  The above-described SRAM memory cell is an example of a so-called 1-port SRAM. On the other hand, in recent years, multiprocessor technology has been introduced as one of the means for realizing high-speed computers, and a plurality of CPUs are connected to one memory. There is a need to share areas. That is, various layouts have been proposed for a 2-port SRAM that enables access from two ports to one memory cell.

  For example, according to the “memory cell” disclosed in Japanese Patent Application Laid-Open No. 07-7089, the second port is arranged symmetrically with the first port, and formed in the same layer at the same time as the first port. A 2-port SRAM configuration is realized. FIG. 23 is a layout diagram of a “memory cell” disclosed in Japanese Patent Application Laid-Open No. 07-7089.

  In FIG. 23, P-channel MOS transistors P201 and P202 and N-channel MOS transistors N201 ′, N202 ′, N201 ″ and N202 ″ constitute a CMOS inverter, that is, a flip-flop circuit, which is cross-connected to each other. Channel-type MOS transistors NA, NB, NA2, and NB2 correspond to access gates (transfer gates).

  That is, in FIG. 23, N-channel MOS transistors NA and NB can be accessed from one port via word line WL1, and N-channel MOS transistors NA2 and NB2 are connected to the other port via word line WL2. It is possible to access from.

  The conventional memory cell has a problem that the wiring structure of the bit line is large and the delay increases because the layout structure is long in the bit line direction, and the “semiconductor memory” disclosed in Japanese Patent Application Laid-Open No. 10-178110 is disclosed. The “device” solves this problem for a 1-port SRAM.

  However, in this “semiconductor memory device”, in general, the above-described problems have not been solved for a two-port SRAM including two sets of access gates and driving MOS transistors. Further, the “memory cell” disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 07-7089 shows the layout of the 2-port SRAM cell, but the second port is greatly changed in the layout of the 1-port SRAM cell. It is intended to provide a layout that can be easily added without the need to reduce the 2-port SRAM cell in the bit line direction.

  The present invention has been made to solve the above problems, and relates to a P-well region and an N-well region in which a pair of CMOS inverters constituting a multiport SRAM cell is formed. The P-well region is divided into two. Arranged on both sides of the N well region, the boundary thereof is located in parallel with the bit line, and a pair of access gates are formed in two divided P well regions, respectively, so that the length in the bit line direction is short. An object is to obtain a semiconductor memory device of a memory cell.

  In order to solve the above-described problems and achieve the object, in the semiconductor memory device according to the present invention, the first word line, the second word line, the first positive phase bit line, the first The CMOS inverter is configured to include a negative-phase bit line, a second positive-phase bit line, a second negative-phase bit line, a first N-channel MOS transistor, and a first P-channel MOS transistor. A CMOS inverter is configured by including a first CMOS inverter, a second N-channel MOS transistor, and a second P-channel MOS transistor, and the first storage node is used as the first storage node. Connected to the output terminal of the CMOS inverter, and the output terminal of the CMOS inverter is used as the second storage node to input the first CMOS inverter. A second CMOS inverter connected to the terminal; a gate connected to the first word line; a drain connected to the first positive-phase bit line; and a source connected to the first storage node. N-channel MOS transistor, a fourth N-channel having a gate connected to the first word line, a drain connected to the first negative-phase bit line, and a source connected to the second storage node And a fifth N-channel MOS transistor having a gate connected to the second word line, a drain connected to the second positive-phase bit line, and a source connected to the first storage node. A sixth N-channel MOS transistor having a gate connected to the second word line, a drain connected to the second anti-phase bit line, and a source connected to the second storage node; The first and second P-channel MOS transistors are formed in an N-well region, and the first, third, and fifth N-channel MOS transistors are formed in a first P-well region. The second, fourth and sixth N-channel MOS transistors are formed in a second P-well region.

  The semiconductor memory device according to the next invention is characterized in that, in the above invention, the first and second P well regions are formed on both sides of the N well region.

  In the semiconductor memory device according to the next invention, in the above invention, the first positive-phase bit line, the first negative-phase bit line, the second positive-phase bit line, and the second negative-phase bit line are provided. The extending direction of each bit line and a boundary line between the first and second P well regions and the N well region are parallel to each other.

  In the semiconductor memory device according to the next invention, in the above invention, a boundary line between the first and second P-well regions and the N-well region corresponds to each of the first and second word lines. It is characterized by being orthogonal to the stretching direction.

  In the semiconductor memory device according to the next invention, in the above invention, the first P-channel MOS transistor and the first, third and fourth N-channel MOS transistors each have a gate region. The second word line is formed so as to be parallel to the extending direction of the first word line and on the same straight line, the second P-channel MOS transistor, the second, fifth and sixth The N-channel MOS transistor is formed such that each gate region is parallel to the extending direction of the second word line and is located on the same straight line.

  In the semiconductor memory device according to the next invention, in the above invention, the third and fifth N-channel MOS transistors have their source diffusion regions and drain diffusion regions located on the same straight line, and The fourth and sixth N-channel MOS transistors are formed so as to be arranged parallel to the extending direction of the first and second positive-phase bit lines, and each of the fourth and sixth N-channel MOS transistors has a source diffusion region and a drain diffusion region. It is formed so as to be located on the same straight line and to be arranged in parallel with the extending direction of the first and second reversed-phase bit lines.

  In the semiconductor memory device according to the next invention, in the above invention, the drain diffusion region of the third and fifth N-channel MOS transistors is formed by a common first n + diffusion region, and the fourth The drain diffusion region of the sixth N-channel MOS transistor is formed by a common second n + diffusion region.

  In the semiconductor memory device according to the next invention, in the above invention, a drain diffusion region of the first N-channel MOS transistor and a drain diffusion region of the third and fifth N-channel MOS transistors are provided. Are connected by a first metal wiring in an upper layer through a contact hole, and the drain diffusion region of the second N-channel MOS transistor and the drain diffusion regions of the fourth and sixth N-channel MOS transistors are In this case, the upper metal layer is connected by a second metal wiring through a contact hole.

  In the semiconductor memory device according to the next invention, in the above invention, the extending direction of the first and second metal wirings is parallel to the extending direction of the first and second word lines. It is characterized by.

  In the semiconductor memory device according to the next invention, in the above invention, the first and second positive phase bit lines, the first and second negative phase bit lines, the power supply line, and the GND line Each extending direction is perpendicular to the first and second word lines.

  In the semiconductor memory device according to the next invention, in the above invention, the drain diffusion regions of the first, third and fifth N-channel MOS transistors are formed by a common first n + diffusion region, The drain diffusion regions of the second, fourth, and sixth N-channel MOS transistors are formed by a common second n + diffusion region.

  In the semiconductor memory device according to the next invention, in the above invention, the first n + diffusion region and the drain diffusion region of the first P-channel MOS transistor are connected to the upper layer through a contact hole. The second n + diffusion region and the drain diffusion region of the second P-channel MOS transistor are connected by an upper second metal wiring through a contact hole. It is characterized by.

  In the semiconductor memory device according to the next invention, the first word line, the second word line, the first positive phase bit line, the first negative phase bit line, and the second positive phase A first CMOS inverter comprising a bit line, a first N-channel MOS transistor and a first P-channel MOS transistor to constitute a CMOS inverter; a second N-channel MOS transistor and a second P-channel; The CMOS inverter is configured to include a MOS transistor, the input terminal of the CMOS inverter is connected as the first storage node to the output terminal of the first CMOS inverter, and the output terminal of the CMOS inverter is connected to the second memory. A second CMOS inverter connected as a node to an input terminal of the first CMOS inverter, and a gate connected to the first CMOS inverter; A third N-channel MOS transistor having a drain connected to the first positive-phase bit line, a source connected to the first storage node, and a gate connected to the first word line A fourth N-channel MOS transistor having a drain connected to the first reversed-phase bit line, a source connected to the second storage node, and a gate connected to the first storage node. A fifth N-channel MOS transistor, a gate connected to the second word line, a drain connected to the second positive-phase bit line, and a source connected to the drain of the fifth N-channel MOS transistor A sixth N-channel MOS transistor connected to each other, wherein the first and second P-channel MOS transistors are formed in an N-well region, and the first and third N-channel MOS transistors are formed. The channel type MOS transistor is formed in a first P well region, and the second, fourth, fifth and sixth N channel type MOS transistors are formed in a second P well region. To do.

  In the semiconductor memory device according to the next invention, a third word line, a first positive phase bit line, a second negative phase bit line, and a gate are further connected to the second storage node. The seventh N-channel MOS transistor, the gate connected to the third word line, the drain connected to the second anti-phase bit line, and the source connected to the drain of the seventh N-channel MOS transistor. And an eighth N-channel MOS transistor connected to the second N-channel MOS transistor, wherein the seventh and eighth N-channel MOS transistors are formed in the first P-well region.

  The semiconductor memory device according to the next invention is characterized in that, in the above invention, the second and third word lines are a common word line.

  The semiconductor memory device according to the next invention is characterized in that, in the above invention, the first and second P well regions are formed on both sides of the N well region.

  In the semiconductor memory device according to the next invention, in the above invention, the extending directions of the first positive-phase bit line, the first negative-phase bit line, and the second positive-phase bit line, A boundary line between the first and second P-well regions and the N-well region is parallel.

  In the semiconductor memory device according to the next invention, in the above invention, a boundary line between the first and second P-well regions and the N-well region is defined by each of the first and second word lines. It is characterized by being orthogonal to the stretching direction.

  In the semiconductor memory device according to the next invention, in the above invention, the first P-channel MOS transistor and the first, fourth, and sixth N-channel MOS transistors each have a gate region. The second P-channel MOS transistor, the second, third, and fifth transistors are arranged on the same straight line and arranged in parallel to the extending direction of the first word line. The N-channel MOS transistors are characterized in that the respective gate regions are located on the same straight line and are arranged in parallel to the extending direction of the second word line.

  In the semiconductor memory device according to the next invention, in the above invention, the first and third N-channel MOS transistors include a drain diffusion region of the first N-channel MOS transistor and the third N-channel MOS transistor. The second and fourth N-channels are formed so that source diffusion regions of the channel-type MOS transistor are located on the same straight line and arranged in parallel to the extending direction of the first positive-phase bit line. In the MOS transistor, the drain diffusion region of the second N-channel MOS transistor and the source diffusion region of the fourth N-channel MOS transistor are located on the same straight line, and the first antiphase bit line The fifth and sixth N-channel MOS transistors are arranged in parallel to the extending direction of the fifth N-channel MOS transistor. The drain diffusion region of the N-type MOS transistor and the source diffusion region of the sixth N-channel type MOS transistor are located on the same straight line and are arranged in parallel to the extending direction of the second positive-phase bit line. It was formed as follows.

  In the semiconductor memory device according to the next invention, in the above invention, the drain diffusion region of the first N-channel MOS transistor and the source diffusion region of the third N-channel MOS transistor are the same in the first The drain diffusion region of the second N-channel MOS transistor and the source diffusion region of the fourth N-channel MOS transistor are formed of a common second n + diffusion region, The drain diffusion region of the fifth N-channel MOS transistor and the source diffusion region of the sixth N-channel MOS transistor are formed by a common third n + diffusion region.

  In the semiconductor memory device according to the next invention, in the above invention, the second P-channel MOS transistor and the second and fifth N-channel MOS transistors have a linear gate region. They are connected by a common polysilicon wiring.

  In the semiconductor memory device according to the next invention, in the above invention, the first and second positive phase bit lines, the first negative phase bit line, the power supply line, and the GND line are extended. The direction is perpendicular to the first and second word lines.

  In the semiconductor memory device according to the next invention, in the above invention, the first P-channel MOS transistor and the first, fourth, sixth and seventh N-channel MOS transistors are respectively The gate region is formed to be parallel to the extending direction of the first word line and located on the same straight line, the second P-channel MOS transistor, the second, third, The fifth and eighth N-channel MOS transistors are formed so that the respective gate regions are parallel to the extending direction of the second word line and located on the same straight line. And

  In the semiconductor memory device according to the next invention, in the above invention, the first and third N-channel MOS transistors include a drain diffusion region of the first N-channel MOS transistor and the third N-channel MOS transistor. The source diffusion region of the channel type MOS transistor is formed so as to be parallel to the extending direction of the first positive phase bit line and located on the same straight line, and the second and fourth N channel types In the MOS transistor, the drain diffusion region of the second N-channel MOS transistor and the source diffusion region of the fourth N-channel MOS transistor are parallel to the extending direction of the first antiphase bit line. The fifth and sixth N-channel MOS transistors are formed on the same straight line, and the fifth and sixth N-channel MOS transistors The drain diffusion region of the MOS transistor and the source diffusion region of the sixth N-channel MOS transistor are parallel to the extending direction of the second positive-phase bit line and located on the same straight line. The seventh and eighth N-channel MOS transistors are formed so that the drain diffusion region of the seventh N-channel MOS transistor and the source diffusion region of the eighth N-channel MOS transistor are the second inverse. It is characterized by being formed so as to be parallel to the extending direction of the phase bit lines and located on the same straight line.

  In the semiconductor memory device according to the next invention, in the above invention, the drain diffusion region of the first N-channel MOS transistor and the source diffusion region of the third N-channel MOS transistor are the same in the first The drain diffusion region of the second N-channel MOS transistor and the source diffusion region of the fourth N-channel MOS transistor are formed of a common second n + diffusion region, The drain diffusion region of the fifth N-channel MOS transistor and the source diffusion region of the sixth N-channel MOS transistor are formed by a common third n + diffusion region, and the seventh N-channel MOS transistor The drain diffusion region and the source diffusion region of the eighth N-channel type MOS transistor have a common fourth n + It was formed by diffusing region characterized.

  In the semiconductor memory device according to the next invention, in the above invention, the second P-channel MOS transistor and the second and fifth N-channel MOS transistors have a linear gate region. The first P-channel MOS transistor and the first and seventh N-channel MOS transistors are connected by a common first polysilicon wiring, and each of the first and seventh N-channel MOS transistors has a linear second common gate region. It is connected by polysilicon wiring.

  As described above, according to the present invention, the first, third, and fifth N-channel MOS transistors that are electrically connected to the positive-phase bit line, and the second, Since the fourth and sixth N-channel MOS transistors are formed in the separated P well regions, respectively, in particular, the juxtaposed direction of these well regions is set to be perpendicular to the normal phase and reverse phase bit line directions. By doing so, it is possible to apply a layout that shortens the length of the bit line, and there is an effect that high-speed access is possible.

  According to the next invention, since the first and second P well regions are arranged on both sides of the N well region, the N channel type MOS transistors formed in the first and second P well regions, respectively, The connection wiring distance with the P channel type MOS transistor formed in the well region can be made uniform, and an optimum layout with shorter wiring can be employed.

  According to the next invention, since the extending direction of each bit line is parallel to the boundary line between the first and second P well regions and the N well region, the length of each word line can be shortened. Considering the above, there is an effect that a layout in which the length of each bit line is the shortest becomes possible.

  According to the next invention, since the extending direction of each word line is perpendicular to the boundary line between the first and second P well regions and the N well region, the length of each bit line is preferentially shortened. In consideration of this, there is an effect that a layout in which the length of each word line is minimized is possible.

  According to the next invention, the gate regions of the first P-channel MOS transistor and the first, third and fourth N-channel MOS transistors are formed so as to be positioned on the same straight line. The wiring for connecting these gates can be formed into a straight line shape, and the gate regions of the second P-channel MOS transistor and the second, fifth, and sixth N-channel MOS transistors can also be used. Since the gates are formed so as to be positioned on the same straight line, the wiring for connecting these gates can be formed into a straight line shape, thereby producing an effect that a short wiring can be obtained.

  According to the next invention, since the sources and drains of the third and fifth N-channel MOS transistors functioning as access gates are located on the same straight line, the third and fifth N-channel MOS transistors. The arrangement interval of the transistors can be reduced. Similarly, in the fourth and sixth N-channel MOS transistors, the sources and drains are located on the same straight line. The arrangement interval of the channel type MOS transistors can be reduced, and the degree of integration of the memory cells can be improved.

  According to the next invention, in the third and fifth N-channel MOS transistors and the fourth and sixth N-channel MOS transistors, the drain diffusion region is formed by a common n + diffusion region. There is an effect that the n + diffusion region can be reduced and the parasitic capacitance due to the n + diffusion region can be reduced.

  According to the next invention, the drain diffusion regions of the first N-channel MOS transistor and the third and fifth N-channel MOS transistors are connected by the first metal wiring in the upper layer, and the second Since the drain diffusion regions of the N-channel MOS transistor and the fourth and sixth N-channel MOS transistors are connected by the second metal wiring in the upper layer, the first and second metal wirings are According to the arrangement position of the drain diffusion region described above, it is possible to form a straight line, thereby producing an effect that a short wiring can be obtained.

  According to the next invention, since the extending directions of the first and second metal wirings are parallel to the extending direction of each word line, the lengths of these metal wirings are also set to optimum lengths in the same manner as the word lines. There is an effect that can be done.

  According to the next invention, since the extending directions of the bit lines, the power supply lines, and the GND lines are perpendicular to the word lines, the lengths of these wirings can be minimized and the high speed is achieved. There is an effect that access becomes possible.

  According to the next invention, in the first, third and fifth N-channel MOS transistors and the second, fourth and sixth N-channel MOS transistors, the drain diffusion region is a common n + diffusion region. Since it is formed, the metal wiring between these drain diffusion regions can be omitted.

  According to the next invention, the first n + diffusion region, the drain diffusion region of the first P-channel MOS transistor, the second n + diffusion region, and the drain diffusion region of the second P-channel MOS transistor are: Since each of the metal wirings is connected by an upper layer metal wiring, the metal wiring can be formed in a straight line shape according to the arrangement positions of the drain diffusion region and the n + diffusion region, and thereby a short wiring can be obtained. Play.

  According to the next invention, in the circuit constituting the 2-port SRAM cell using the fifth and sixth N-channel MOS transistors as the read ports, the first and second electrically connected to the positive-phase bit line are provided. Since the 3rd and 5th N channel type MOS transistors and the 2nd and 4th N channel type MOS transistors connected to the anti-phase bit line are respectively formed in the separated P well regions, By making the juxtaposition direction of the well regions perpendicular to the normal-phase and reverse-phase bit line directions, it is possible to apply a layout that shortens the length of the bit line, thereby enabling high-speed access. Play.

  According to the next invention, the fifth and sixth N-channel MOS transistors are used as the first read port, and the seventh and eighth N-channel MOS transistors are used as the second read port. In the circuit constituting the 3-port SRAM cell, the first, third and fifth N-channel MOS transistors electrically connected to the positive phase bit line, and the second and fourth connected to the negative phase bit line. And the seventh N-channel MOS transistor are respectively formed in the separated P-well regions, and in particular, the juxtaposed direction of these well regions is perpendicular to the normal phase and reverse-phase bit line directions. As a result, it is possible to apply a layout that shortens the length of the bit line, and there is an effect that high-speed access is possible.

  According to the next invention, in the circuit constituting the differential read type two-port SRAM cell that performs the read operation by the difference in potential between the second normal phase bit line and the second reverse bit line, The first, third and fifth N-channel MOS transistors electrically connected to the first and third N-channel MOS transistors connected to the opposite-phase bit line are separated from each other. In particular, a layout in which the lengths of the bit lines are reduced by making the juxtaposed direction of the well regions perpendicular to the normal phase and reverse phase bit line directions is applied. It is possible to achieve high speed access.

  According to the next invention, since the first and second P well regions are arranged on both sides of the N well region, the N channel type MOS transistors formed in the first and second P well regions, respectively, The connection wiring distance with the P channel type MOS transistor formed in the well region can be made uniform, and an optimum layout with shorter wiring can be employed.

  According to the next invention, since the extending direction of each bit line is parallel to the boundary line between the first and second P well regions and the N well region, the length of each word line can be shortened. Considering the above, there is an effect that a layout in which the length of each bit line is the shortest becomes possible.

  According to the next invention, since the extending direction of each word line is perpendicular to the boundary line between the first and second P well regions and the N well region, the length of each bit line is preferentially shortened. In consideration of this, there is an effect that a layout in which the length of each word line is minimized is possible.

  According to the next invention, the gate regions of the first P-channel MOS transistor and the first, fourth and sixth N-channel MOS transistors are formed so as to be positioned on the same straight line. The wiring for connecting these gates can be formed into a straight line shape, and the gate regions of the second P-channel MOS transistor and the second, third, and fifth N-channel MOS transistors are also used. Since the gates are formed so as to be positioned on the same straight line, the wiring for connecting these gates can be formed into a straight line shape, thereby producing an effect that a short wiring can be obtained.

  According to the next invention, since the drain of the second N-channel MOS transistor and the source of the fourth N-channel MOS transistor are located on the same straight line, these second and fourth N-channel MOS transistors The arrangement interval of the transistors can be reduced, and the drain of the fifth N-channel MOS transistor and the source of the sixth N-channel MOS transistor are similarly located on the same straight line. The arrangement interval of the six N-channel MOS transistors can be reduced, and the degree of integration of the memory cells can be improved.

  According to the next invention, in each of the first and third N-channel MOS transistors and the fifth and sixth N-channel MOS transistors, one of the semiconductor terminals is formed by a common n + diffusion region. The n + diffusion region can be reduced, and the parasitic capacitance due to the n + diffusion region can be reduced.

  According to the next invention, the second P-channel MOS transistor and the second and fifth N-channel MOS transistors have their gate regions connected to each other by a linear common polysilicon wiring. The arrangement interval between these MOS transistors can be reduced, and the degree of integration of the memory cells can be improved.

  According to the next invention, since the extending directions of the bit lines, the power supply lines, and the GND lines are perpendicular to the word lines, the lengths of these wirings can be minimized and the high speed is achieved. There is an effect that access becomes possible.

  According to the next invention, the gate regions of the first P-channel MOS transistor and the first, fourth, sixth and seventh N-channel MOS transistors are formed so as to be positioned on the same straight line. Therefore, the wiring for connecting these gates can be formed into a straight line shape, and the second P-channel MOS transistor and the second, third, fifth and eighth N-channel MOS transistors. Each of the gate regions is also formed so as to be positioned on the same straight line, so that the wiring for connecting these gates can be formed into a straight line shape, thereby obtaining an effect that a short wiring can be obtained. Play.

  According to the next invention, since the drain of the second N-channel MOS transistor and the source of the fourth N-channel MOS transistor are located on the same straight line, these second and fourth N-channel MOS transistors The arrangement interval of the transistors can be reduced, and the drain of the fifth N-channel MOS transistor and the source of the sixth N-channel MOS transistor are similarly located on the same straight line. The arrangement interval of the six N-channel MOS transistors can be reduced, and the drain of the seventh N-channel MOS transistor and the source of the eighth N-channel MOS transistor are also located on the same straight line. The arrangement interval of these seventh and eighth N channel type MOS transistors can be reduced. An effect that it is possible to improve the integration degree of the memory cell.

  According to the next invention, in each of the first and third N-channel MOS transistors, the fifth and sixth N-channel MOS transistors, and the seventh and eighth N-channel MOS transistors, one of the semiconductor terminals is provided. Is formed by a common n + diffusion region, the n + diffusion region can be reduced, and the parasitic capacitance due to the n + diffusion region can be reduced.

  According to the next invention, the second P-channel MOS transistor and the second and fifth N-channel MOS transistors have their gate regions connected to each other by the straight common polysilicon wiring, Since the P-channel MOS transistor and the first and seventh N-channel MOS transistors have their gate regions connected to each other by a common linear polysilicon wiring, the arrangement interval between these MOS transistors is reduced. It is possible to improve the degree of integration of the memory cells.

FIG. 1 is a diagram illustrating an equivalent circuit of the semiconductor memory device according to the first embodiment. FIG. 2 is a layout diagram of the memory cells of the semiconductor memory device according to the first embodiment. FIG. 3 is a layout diagram of the memory cells of the semiconductor memory device according to the first embodiment. FIG. 4 is a layout diagram of the memory cells of the semiconductor memory device according to the first embodiment. FIG. 5 is a layout diagram of the memory cells of the semiconductor memory device according to the first embodiment. FIG. 6 is an explanatory diagram for explaining various symbols such as contact holes and via holes. FIG. 7 is a layout diagram of the memory cells of the semiconductor memory device according to the second embodiment. FIG. 8 is a diagram illustrating an equivalent circuit of the semiconductor memory device according to the third embodiment. FIG. 9 is a layout diagram of the memory cells of the semiconductor memory device according to the third embodiment. FIG. 10 is a layout diagram of the memory cells of the semiconductor memory device according to the third embodiment. FIG. 11 is a layout diagram of the memory cell of the semiconductor memory device according to the third embodiment. FIG. 12 is a layout diagram of the memory cells of the semiconductor memory device according to the third embodiment. FIG. 13 is a diagram illustrating an equivalent circuit of the semiconductor memory device according to the fourth embodiment. FIG. 14 is a layout diagram of the memory cells of the semiconductor memory device according to the fourth embodiment. FIG. 15 is a layout diagram of the memory cells of the semiconductor memory device according to the fourth embodiment. FIG. 16 is a layout diagram of the memory cells of the semiconductor memory device according to the fourth embodiment. FIG. 17 is a layout diagram of the memory cells of the semiconductor memory device according to the fourth embodiment. FIG. 18 is a diagram illustrating an equivalent circuit of the semiconductor memory device according to the fifth embodiment. FIG. 19 is a layout diagram of the memory cells of the semiconductor memory device according to the fifth embodiment. FIG. 20 is a layout diagram of the memory cells of the semiconductor memory device according to the fifth embodiment. FIG. 21 is a layout diagram showing a diffusion region formed on the surface of a semiconductor substrate, a polycrystalline silicon film formed on the upper surface thereof, and a base including a first metal wiring layer in a conventional semiconductor memory device. FIG. 22 is a layout diagram showing an upper surface including second and third metal wiring layers formed in an upper layer in a conventional semiconductor memory device. FIG. 23 is a layout diagram of a conventional memory cell.

  Embodiments according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
First, the semiconductor memory device according to the first embodiment will be described. FIG. 1 is a diagram illustrating an equivalent circuit of the semiconductor memory device according to the first embodiment. In FIG. 1, a P-channel MOS transistor P1 and an N-channel MOS transistor N1 (N1 ′) constitute a first CMOS inverter, and a P-channel MOS transistor P2 and an N-channel MOS transistor N2 (N2 ′). ) Constitutes the second CMOS transistor, and the input / output terminals are cross-connected between the CMOS inverters.

  That is, these MOS transistors P1, P2, N1, N1 ′, N2 and N2 ′ constitute a flip-flop circuit, which is the output point of the first CMOS inverter and the input of the second CMOS inverter in FIG. The logical state can be written and read at the storage node MA which is also a point and the storage node MB which is the output point of the second CMOS inverter and also the input point of the first CMOS inverter.

  N-channel MOS transistors N3, N4, N5 and N6 each function as an access gate. N-channel MOS transistor N3 has a gate connected to first word line WL0 and a source connected to storage node MA described above. The drain is connected to the first positive-phase bit line BL00. The N-channel MOS transistor N5 has a gate connected to the second word line WL1, a source connected to the storage node MA, and a drain connected to the second positive-phase bit line BL10.

  The N-channel MOS transistor N4 has a gate connected to the first word line WL0, a source connected to the storage node MB, and a drain connected to the first reversed-phase bit line BL01. The N-channel MOS transistor N6 has a gate connected to the second word line WL1, a source connected to the storage node MB, and a drain connected to the second reverse-phase bit line BL11.

  That is, by selecting the first word line WL0, the first positive-phase bit line BL00, and the first negative-phase bit line BL01, the stored value can be read by the first port, and the second word line WL1, By selecting the second positive-phase bit line BL10 and the second negative-phase bit line BL11, the stored value can be read by the second port.

  Here, the equivalent circuit itself shown in FIG. 1 is not different from the circuit of the conventional 2-port SRAM cell, but the semiconductor memory device according to the first embodiment is characterized in its structure. 2 to 5 are layout diagrams of the memory cells of the semiconductor memory device according to the first embodiment. FIG. 6 is an explanatory diagram for explaining various symbols such as contact holes and via holes shown in FIGS. First, FIG. 2 shows a layer including a well region formed in a semiconductor substrate, a diffusion region formed in the well region, and a polysilicon wiring layer formed on the upper surface thereof.

  In the memory cell of the semiconductor memory device according to the first embodiment, as shown in FIG. 2, the first P well region PW1, the N well region NW, and the second P well region PW2 are arranged in the planar direction on the semiconductor substrate. They are formed so as to be arranged in that order. That is, two P well regions PW1 and PW2 are divided and arranged on both sides of the N well region NW.

  In particular, these well regions include a boundary line between the first P well region PW1 and the N well region NW (hereinafter referred to as a first well boundary line), a second P well region PW2, and an N well region NW. The boundary line (hereinafter referred to as the second well boundary line) is formed in parallel with each other. Although not shown, isolation regions exist between the N well region NW and the first P well region PW1, and between the N well region NW and the second P well region PW2, respectively.

  1 is formed in the first P-well region PW1, and the P-channel MOS transistor shown in FIG. 1 is formed in the N-well region NW. Transistors P1 and P2 are formed, and N channel type MOS transistors N2, N2 ', N4 and N6 shown in FIG. 1 are formed in the second P well region PW2.

  Hereinafter, the structure of each layer shown in FIGS. First, in the layer shown in FIG. 2, in the first P well region PW1, two polysilicon wiring layers PL21 and PL22 extending in parallel in the direction perpendicular to the first well boundary line are formed. Similarly, in the second P well region PW2, two polysilicon wiring layers PL31 and PL32 that are juxtaposed in a direction perpendicular to the second well boundary line are formed.

  Further, a ridge-shaped polysilicon wiring layer PL11 extends from the N well region NW to the first P well region PW1 in a direction perpendicular to the first well boundary line, and its ridge end portion is a first P well. It is formed so as to be located in region PW1. In particular, as shown in FIG. 2, the flange end portion includes two translational axes (main axis and folding axis) constituting the flange end portion of the polysilicon wiring layer PL11. The shape matches the axis of PL22. In FIG. 2, the main axis of the polysilicon wiring layer PL11 coincides with the polysilicon wiring layer PL21. On the other hand, the other end of the polysilicon wiring layer PL11 is located on the second well boundary line.

  Similarly, from the N well region NW to the second P well region PW2, the eaves-shaped polysilicon wiring layer PL12 extends in the direction perpendicular to the second well boundary line and the end of the eaves is the second P well. It is formed to be located in well region PW2. In addition, as shown in FIG. 2, the two translation axes constituting the collar end portion of the polysilicon wiring layer PL12 coincide with the axes of the two polysilicon wiring layers PL31 and PL32, respectively. It is a shape like this. In FIG. 2, the main axis of the polysilicon wiring layer PL12 coincides with the polysilicon wiring layer PL31. On the other hand, the other end of the polysilicon wiring layer PL12 is located on the first well boundary line.

  Then, in the first P well region PW1, n + diffusion regions FL21 and FL22 are formed by N-type impurity implantation at positions sandwiching the polysilicon wiring layer PL21. As a result, an N-channel MOS transistor N3 having the polysilicon wiring layer PL21 as a gate electrode is formed. Further, n + diffusion regions FL22 and FL23 are formed at positions sandwiching polysilicon wiring layer PL22. As a result, an N-channel MOS transistor N5 using the polysilicon wiring layer PL22 as a gate electrode is formed.

  In particular, since the N-channel MOS transistors N3 and N5 have the polysilicon wiring layers PL21 and PL22 juxtaposed, the n + diffusion regions FL21 to 23 are arranged in a direction parallel to the first well boundary line and in a straight line. Thus, n + diffusion region FL22 can be shared by N-channel MOS transistors N3 and N5. This sharing of n + diffusion region FL22 serves to connect the sources of N-channel MOS transistors N3 and N5 according to the equivalent circuit of FIG. 1, and contributes to a reduction in the area occupied by N-channel MOS transistors N3 and N5. doing.

  In the first P well region PW1, n + diffusion regions FL24 and FL25 are formed by N-type impurity implantation at a position sandwiching the main axis of the end portion of the polysilicon wiring layer PL11. As a result, an N channel type MOS transistor N1 having the main axis of the polysilicon wiring layer PL11 as a gate electrode is formed. Further, the n + diffusion regions FL25 and FL26 are formed at positions sandwiching the folding axis of the end portion of the polysilicon wiring layer PL11, so that the N-channel MOS transistor N1 having the folding axis of the polysilicon wiring layer PL11 as a gate electrode is formed. 'Is formed. That is, the end of the polysilicon wiring layer PL11 connects the gates of the N-channel MOS transistors N1 and N1 'according to the equivalent circuit of FIG.

  As for the N channel type MOS transistors N1 and N1 ′, the main axis and the folding axis of the end portion of the polysilicon wiring layer PL11 are juxtaposed in the same manner as the N channel type MOS transistors N3 and N5 described above. The n + diffusion regions FL24 to 26 can be arranged in a straight line in a direction parallel to the first well boundary line, whereby the n + diffusion region FL25 is shared by the N-channel MOS transistors N1 and N1 ′. Is possible. This sharing of the n + diffusion region FL25 serves to connect the drains of the N-channel MOS transistors N1 and N1 ′ in accordance with the equivalent circuit of FIG. 1 and to reduce the occupied area of the N-channel MOS transistors N1 and N1 ′. It contributes to.

  Further, as shown in the figure, the main axes of the polysilicon wiring layer PL21 and the polysilicon wiring layer PL11 are located on the same straight line, and the folding axes of the polysilicon wiring layer PL22 and the polysilicon wiring layer PL11 are also located on the same straight line. Therefore, the arrangement interval between the N-channel MOS transistors N1 and N1 ′ and the N-channel MOS transistors N3 and N5 can be reduced. In the first P-well region PW1, these four N-channel MOS transistors A reduction in the area occupied by the transistor is realized.

  On the other hand, similarly in the second P well region PW2, n + diffusion regions FL31 and FL32 are formed by N-type impurity implantation at a position sandwiching the polysilicon wiring layer PL31, thereby forming the polysilicon wiring layer PL31. An N channel type MOS transistor N6 is formed as a gate electrode. Further, n + diffusion regions FL32 and FL33 are formed at positions sandwiching polysilicon wiring layer PL32, thereby forming N-channel MOS transistor N4 using polysilicon wiring layer PL32 as a gate electrode.

  Since these N channel type MOS transistors N4 and N6 also have the polysilicon wiring layers PL31 and PL32 juxtaposed, the n + diffusion regions FL31 to 33 are arranged in a direction parallel to the second well boundary line and on the same line. Thus, n + diffusion region FL32 can be shared by N-channel MOS transistors N4 and N6. This sharing of n + diffusion region FL32 serves to connect the sources of N-channel MOS transistors N4 and N6 in accordance with the equivalent circuit of FIG. 1, and contributes to a reduction in the area occupied by N-channel MOS transistors N4 and N6. doing.

  In the second P-well region PW2, n + diffusion regions FL34 and FL35 are formed by N-type impurity implantation at positions sandwiching the main axis of the end portion of the polysilicon wiring layer PL12. As a result, an N channel type MOS transistor N2 having the main axis of the polysilicon wiring layer PL12 as a gate electrode is formed. Further, n + diffusion regions FL35 and FL36 are formed at positions sandwiching the folding axis of the end portion of polysilicon wiring layer PL12, so that N-channel MOS transistor N2 having the folding axis of polysilicon wiring layer PL12 as a gate electrode is formed. 'Is formed. That is, the end of the polysilicon wiring layer PL12 connects the gates of the N-channel MOS transistors N2 and N2 'in accordance with the equivalent circuit of FIG.

  For these N channel type MOS transistors N2 and N2 ', the main axis and the folding axis of the end portion of the polysilicon wiring layer PL12 are juxtaposed in the same manner as the N channel type MOS transistors N4 and N6 described above. The n + diffusion regions FL34 to 36 can be arranged in a direction parallel to the second well boundary line and on the same straight line, whereby the n + diffusion region FL35 is shared by the N-channel MOS transistors N2 and N2 ′. It is possible. This sharing of the n + diffusion region FL35 serves to connect the drains of the N-channel MOS transistors N2 and N2 ′ in accordance with the equivalent circuit of FIG. 1, and reduces the occupied area of the N-channel MOS transistors N2 and N2 ′. It contributes to.

  Further, as shown, the polysilicon wiring layer PL31 and the main axis of the polysilicon wiring layer PL12 are located on the same straight line, and the folding axes of the polysilicon wiring layer PL32 and the polysilicon wiring layer PL12 are also on the same straight line. Therefore, the arrangement interval between the N-channel MOS transistors N2 and N2 ′ and the N-channel MOS transistors N4 and N6 can be reduced. In the second P-well region PW2, these four N-channels The area occupied by the MOS transistor has been reduced.

  In N well region NW, p + diffusion regions FL11 and FL12 are formed by implantation of P-type impurities at positions sandwiching the main axis of polysilicon wiring layer PL11. As a result, a P-channel MOS transistor P1 having the polysilicon wiring layer PL11 as a gate electrode is formed. Further, p + diffusion regions FL13 and FL14 are formed at positions sandwiching the main axis of polysilicon wiring layer PL12, thereby forming P channel type MOS transistor P2 using polysilicon wiring layer PL12 as a gate electrode.

  The arrangement positions of these P channel type MOS transistors P1 and P2 are determined according to the positions of the polysilicon wiring layers PL11 and PL12. The position interval between the polysilicon wiring layers PL11 and PL12 is p + diffusion as shown in FIG. It can be narrowed to the size of the regions FL12 and FL13 (minimum transistor pitch). In particular, the size of these p + diffusion regions FL12 and FL13 is made approximately the same as the n + diffusion regions FL22 and FL25 of the first P well region PW1 and the n + diffusion regions FL32 and FL35 of the second P well region PW2. The total occupied area necessary for the layout of the memory cell can be minimized.

  At the same time, the main axes of the polysilicon wiring layers PL21 and PL11, the folding axis of PL12 and PL32 are arranged on the same straight line, and the main axes of the polysilicon wiring layers PL22 and PL12, the folding axis of PL11 and PL31 are on the same straight line. It can be arranged in.

  As shown in FIG. 2, polysilicon wiring layers PL11, PL12, PL21, PL22, PL31 and PL32, p + diffusion regions FL11-14, n + diffusion regions FL21-26 and FL31-36 each have one. Each contact hole is provided for electrical connection with the upper layer.

  Next, a layer positioned above the layer shown in FIG. 2 will be described. FIG. 3 shows a layer including a first metal wiring layer formed on the layer shown in FIG. In the layer shown in FIG. 3, first metal wiring layer AL11 for electrically connecting lower n + diffusion regions FL22 and FL25, p + diffusion region FL12, and polysilicon wiring layer PL12 is formed. . By this first metal wiring layer AL11, in accordance with the equivalent circuit of FIG. 1, the sources of N-channel MOS transistors N3 and N5, the drains of N-channel MOS transistors N1 and N1 ′, and the output of the first CMOS inverter The connection between the terminal and the input terminal of the second CMOS inverter is achieved.

  Further, first metal wiring layer AL12 for electrically connecting lower n + diffusion regions FL32 and FL35, p + diffusion region FL13, and polysilicon wiring layer PL11 is formed. According to the second metal wiring layer AL12, according to the equivalent circuit of FIG. 1, the sources of N-channel MOS transistors N4 and N6, the drains of N-channel MOS transistors N2 and N2 ′, and the output of the second CMOS inverter The connection between the terminal and the input terminal of the first CMOS inverter is achieved.

  In particular, in the first metal wiring layer AL11, the contact portions between the n + diffusion regions FL32 and FL35 and the p + diffusion region FL13 are arranged on the same straight line as described above, and therefore connect these three points. The shape of the wiring can be made linear. The same applies to the first metal wiring layer AL12.

  Further, in the layer shown in FIG. 3, the first metal wiring layer AL15 for moving the connection point of the lower p + diffusion region FL11 and the first metal wiring for moving the connection point of the p + diffusion region FL14 are provided. And a first metal wiring layer AL17 for moving the connection point of the lower n + diffusion region FL23 and a first metal wiring layer AL18 for moving the connection point of the n + diffusion region FL33. And are formed.

  Next, a layer positioned above the layer shown in FIG. 3 will be described. FIG. 4 shows a layer including a second metal wiring layer formed on the layer shown in FIG. In the layer shown in FIG. 4, the power supply potential VDD is applied to the p + diffusion region FL11 via the first metal wiring layer AL15 shown in FIG. 3, and the p + diffusion region is supplied via the first metal wiring layer AL16. A second metal wiring layer AL21 for applying power supply potential VDD to FL14 is formed. That is, the second metal wiring layer AL21 functions as a power supply potential VDD line. In the equivalent circuit of FIG. 1, the connection between the source of the P-channel MOS transistor P1 and the power supply, and the source of the P-channel MOS transistor P2 And the connection with the power source.

  Further, second metal interconnection layer AL22 for applying ground potential GND to p + diffusion regions FL24 and FL26 and p + diffusion regions FL34 and FL36 via contact hole + first via hole shown in FIG. 3 and AL23 is formed. That is, these second metal wiring layers AL22 and AL23 function as a ground potential GND line, and in the equivalent circuit of FIG. 1, serve to ground each source of N-channel MOS transistors N1, N1 ′, N2 and N2 ′. Is.

  In particular, as shown in FIG. 2, since n + diffusion regions FL24 and FL26 are arranged on a straight line parallel to the first well boundary line, each contact hole on these n + diffusion regions also has both contact holes. Can be formed at a position such that a straight line connecting the two is parallel to the first well boundary line. That is, the second metal wiring layer AL22 shown in FIG. 4 can be formed in a linear shape parallel to the first well boundary line. The same applies to the second metal wiring layer AL23.

  Further, the layer shown in FIG. 4 includes a second metal that functions as the first positive-phase bit line BL00 connected to the lower p + diffusion region FL21 through the contact hole + first via hole shown in FIG. The wiring layer AL24, the second metal wiring layer AL25 connected to the p + diffusion region FL26 and functioning as the second positive phase bit line BL10, and the first negative phase bit line BL01 connected to the p + diffusion region FL36. A functioning second metal wiring layer AL26 and a second metal wiring layer AL27 connected to p + diffusion region FL31 and functioning as second antiphase bit line BL11 are formed.

  That is, these second metal wiring layers AL24 to AL27 are connected to the other (drain) of the semiconductor terminal of the N-channel MOS transistor N3 and the first positive-phase bit line BL00 in the equivalent circuit of FIG. Connection between the other (drain) of the semiconductor terminal of the channel MOS transistor N5 and the second positive-phase bit line BL10, and the other (drain) of the semiconductor terminal of the N-channel MOS transistor N4 and the first negative-phase bit line BL01. And the connection between the other (drain) of the semiconductor terminal of the N-channel MOS transistor N6 and the second antiphase bit line BL11.

  In particular, the second metal wiring layers AL24 to AL27 can be formed in a linear shape extending in a direction parallel to the first well boundary line. This is because the lengths of the first positive-phase bit line BL00, the second positive-phase bit line BL10, the first negative-phase bit line BL01, and the second negative-phase bit line BL11 are set in one memory cell. It means shorter.

  Next, a layer positioned above the layer shown in FIG. 4 will be described. FIG. 5 shows a layer including a third metal wiring layer formed on the layer shown in FIG. The layer shown in FIG. 5 includes a third metal wiring layer that electrically connects the polysilicon wiring layers PL21 and PL32 via the first via hole and the second via hole and functions as the first word line WL0. AL31 is formed. That is, the third metal wiring layer AL31 serves to connect the gates of the N-channel MOS transistors N3 and N4 and the first word line WL0 in the equivalent circuit of FIG.

  Further, a third metal wiring layer AL32 that functions as the second word line WL1 is formed while electrically connecting the polysilicon wiring layers PL22 and PL31 via the first via hole and the second via hole. That is, the third metal wiring layer AL32 serves to connect the gates of the N-channel MOS transistors N5 and N6 and the second word line WL1 in the equivalent circuit of FIG.

  In particular, as shown in FIG. 2, since the polysilicon wiring layers PL21 and PL32 are arranged on the same straight line extending in a direction perpendicular to the first well boundary line, the polysilicon wiring layers PL21 and PL32 are arranged on the polysilicon wiring layers. Each contact hole or the like can also be formed at a position where a straight line connecting both contact holes and the like is perpendicular to the first well boundary line. That is, the third metal wiring layer AL31 shown in FIG. 5 can be formed in a linear shape extending in the direction perpendicular to the first well boundary line. The same applies to the third metal wiring layer AL32. This means that the lengths of the first word line WL0 and the second word line WL1 are made shorter in one memory cell.

  As described above, according to the semiconductor memory device of the first embodiment, the N-channel MOS transistors N3 and N5 (N4 and N6) functioning as access gates are n + diffused at the connection point between the semiconductor terminals. Since the region FL22 (FL32) is shared, the n + diffusion regions FL21 to 23 (FL31 to 33) serving as semiconductor terminals are formed so as to be arranged in a straight line in a direction parallel to the first well boundary line. Thus, the area occupied by N channel type MOS transistors N3 and N5 (N4 and N6) can be reduced. As a result, the integration degree of the memory cell array can be increased.

  The second metal wiring layers AL24 to AL27 function in order as the first positive-phase bit line BL00, the second positive-phase bit line BL10, the first negative-phase bit line BL01, and the second negative-phase bit line BL11. Are formed so as to be juxtaposed in parallel with the boundary line between the first P well region PW1, the second P well region PW2 and the N well region NW, thereby reducing the length of these bit lines. Therefore, the wiring capacity of the bit line can be reduced, thereby enabling high speed access.

  The third metal wiring layers AL31 and AL32 that function in turn as the first word line WL0 and the second word line WL1 include the first P well region PW1, the second P well region PW2, and the N well region NW. Since the length of these word lines can be further shortened, the wiring capacity of the word lines can be reduced, thereby enabling high-speed access. It becomes.

  In addition, N-channel MOS transistors N1 and N2 (N1 ′ and N2 ′) are divided into two P-well regions, so that the width of each transistor can be increased, whereby the bit line can be pulled out quickly. Thus, faster access is possible.

  Further, by forming driver transistors N1 and N1 ′ (or N2 and N2 ′) functioning as drive transistors in parallel, the width W of the transistor can be increased, thereby increasing the bit line drawing speed. As a result, it is possible to increase the speed of read access.

  In addition, the above-described division can increase the transistor ratio between the N-channel MOS transistors N3 and N5 functioning as access gates and the N-channel MOS transistors N1 and N1 ′ functioning as drive transistors. Stability can be improved. The same applies to N-channel MOS transistors N4 and N6 and N-channel MOS transistors N2 and N2 '.

  In addition, since the drain region forming storage nodes MA and MB is a common n + diffusion region, the area can be reduced, and parasitic capacitance is reduced, resulting in higher access speed at the time of writing. Can do.

  Furthermore, since the polysilicon wiring layer can be formed in a straight line, it is possible to increase a process margin due to mask displacement or the like when forming a layout pattern in the semiconductor manufacturing process.

Embodiment 2. FIG.
Next, a semiconductor memory device according to the second embodiment will be described. FIG. 7 is a layout diagram of the memory cell of the semiconductor memory device according to the second embodiment, and corresponds to FIG. 2 described above.

  As shown in FIG. 7, in the semiconductor memory device according to the second embodiment, in the P well region PW1, the drain diffusion regions of the N channel type MOS transistors N3 and N5 and the N channel type MOS transistors N1 and N1 ′ The drain diffusion region is formed by a common n + diffusion region FL41. In the P well region PW2, the drain diffusion regions of the N-channel MOS transistors N4 and N6 and the drain diffusions of the N-channel MOS transistors N2 and N2 ′ The region is formed by a common n + diffusion region FL42.

  Accordingly, polysilicon wiring layers PL51 and PL52 having a shape as shown in FIG. 7 are formed instead of the polysilicon wiring layers PL11 and PL12 shown in FIG. Since the layout of other upper layer metal wirings and the like is the same as that shown in FIGS. 3 to 5, their description is omitted here.

  As described above, according to the semiconductor memory device according to the second embodiment, the effects of the first embodiment can be obtained also by forming the shared n + diffusion region as described above.

  In the first and second embodiments described above, N-channel MOS transistors N1 'and N2' can be omitted.

Embodiment 3 FIG.
Next, a semiconductor memory device according to Embodiment 3 will be described. In the third embodiment, a layout configuration for another equivalent circuit constituting a 2-port SRAM cell will be described. FIG. 8 is a diagram illustrating an equivalent circuit of the semiconductor memory device according to the third embodiment. In FIG. 8, a P-channel MOS transistor P1 and an N-channel MOS transistor N1 constitute a first CMOS inverter, and a P-channel MOS transistor P2 and an N-channel MOS transistor N2 constitute a second CMOS transistor. The input / output terminals are cross-connected between these CMOS inverters.

  That is, these MOS transistors P1, P2, N1 and N2 constitute a flip-flop circuit, and in FIG. 8, the storage node MA which is the output point of the first CMOS inverter and the input point of the second CMOS inverter. The logic state can be written to and read from the storage node MB which is the output point of the second CMOS inverter and the input point of the first CMOS inverter.

  N-channel MOS transistors N3 and N4 each function as an access gate. N-channel MOS transistor N3 has a gate connected to first word line WWL and a source connected to storage node MA described above. The drain is connected to the first positive phase bit line WBL1. The N-channel MOS transistor N4 has a gate connected to the first word line WWL, a source connected to the storage node MA, and a gate connected to the anti-phase bit line WBL2.

  The storage node MA is connected to the gate of an N-channel MOS transistor N8, and the source of the N-channel MOS transistor N8 is grounded. Further, the drain of the N-channel MOS transistor N8 is connected to the source of the N-channel MOS transistor N9, and the N-channel MOS transistor N9 has a gate connected to the second word line RWL and a drain connected to the second positive line. The phase bit line RBL is connected.

  That is, by selecting the word line WWL, the first positive-phase bit line WBL1 and the negative-phase bit line WBL2, the storage value can be read and written by the first port, and the second word line RWL and the second positive-phase bit line WBL2 are selected. By selecting the phase bit line RBL, the stored value can be read by the second port. In particular, the read operation by the second port has a feature that it can operate completely independently from the first port without destroying the data of the storage nodes MA and MB of the memory cell. Yes.

  Here, the equivalent circuit itself shown in FIG. 8 has a known configuration as a conventional 2-port SRAM cell circuit, but the structure of the semiconductor memory device according to the third embodiment is characteristic. 9 to 12 are layout diagrams of memory cells of the semiconductor memory device according to the third embodiment. In the figure, various symbols such as contact holes and via holes are as shown in FIG.

  First, FIG. 9 shows a layer including a well region formed in a semiconductor substrate, a diffusion region formed in the well region, and a polysilicon wiring layer formed on the upper surface thereof.

  In the memory cell of the semiconductor memory device according to the third embodiment, as shown in FIG. 9, the first P-well region is sandwiched between the N-well region NW in the planar direction on the semiconductor substrate as in the first embodiment. PW1 and second P well region PW2 are arranged, and these well regions are formed so that the first well boundary line and the second well boundary line are parallel to each other. Although not shown, isolation regions exist between the N well region NW and the first P well region PW1, and between the N well region NW and the second P well region PW2, respectively.

  9, N channel type MOS transistors N1 and N3 shown in FIG. 8 are formed in first P well region PW1, and P channel type MOS transistor P1 shown in FIG. P2 is formed, and N channel type MOS transistors N2, N4, N8 and N9 shown in FIG. 8 are formed in the second P well region PW2.

  Below, the structure of each layer shown in FIGS. First, in the layer shown in FIG. 9, the polysilicon wiring layer PL21 extending in the direction perpendicular to the first well boundary line and juxtaposed is formed in the first P well region PW1.

  Further, a polysilicon wiring layer PL11 extending in a straight line in a direction perpendicular to the first well boundary line is formed from the first P well region PW1 to the N well region NW. Note that one end of the polysilicon wiring layer PL11 is located on the second well boundary line as shown in FIG.

  Then, in the first P well region PW1, n + diffusion regions FL22 and FL23 are formed by N-type impurity implantation at positions sandwiching the polysilicon wiring layer PL21. As a result, an N-channel MOS transistor N3 having the polysilicon wiring layer PL21 as a gate electrode is formed. Further, n + diffusion regions FL21 and FL22 are formed at positions sandwiching polysilicon wiring layer PL11. As a result, an N-channel MOS transistor N1 using the polysilicon wiring layer PL11 as a gate electrode is formed.

  In particular, since the N-channel MOS transistors N1 and N3 have the polysilicon wiring layers PL11 and PL21 juxtaposed, the n + diffusion regions FL21 to 23 are arranged in a direction parallel to the first well boundary line and in a straight line. Thus, n + diffusion region FL22 can be shared between N-channel MOS transistors N1 and N3. This sharing of the n + diffusion region FL22 serves to connect the drain of the N-channel MOS transistor N1 and the source of the N-channel MOS transistor N3 and the N-channel MOS transistors N1 and N3 according to the equivalent circuit of FIG. This contributes to a reduction in the area occupied by

  On the other hand, in the second P well region PW2, two polysilicon wiring layers PL31 and PL33 extending in a direction perpendicular to the second well boundary line and juxtaposed in a straight line are formed. Further, a polysilicon wiring layer PL12 extending in a straight line in a direction perpendicular to the second well boundary line is formed from the second P well region PW2 to the N well region NW. Note that one end portion of the polysilicon wiring layer PL12 is located on the first well boundary line as shown in FIG.

  Then, n + diffusion regions FL36 and FL35 are formed by N-type impurity implantation at a position sandwiching the polysilicon wiring layer PL33, thereby forming an N-channel MOS transistor N4 having the polysilicon wiring layer PL33 as a gate electrode. The Further, n + diffusion regions FL34 and FL35 are formed at positions sandwiching polysilicon wiring layer PL12, thereby forming N channel type MOS transistor N2 using polysilicon wiring layer PL12 as a gate electrode.

  In these N channel type MOS transistors N2 and N4, since polysilicon wiring layers PL33 and PL12 are juxtaposed, n + diffusion regions FL34 to 36 are arranged in a direction parallel to the second well boundary line and on the same straight line. Thus, n + diffusion region FL35 can be shared by N-channel MOS transistors N2 and N4. This sharing of the n + diffusion region FL35 serves to connect the drain of the N-channel MOS transistor N2 and the source of the N-channel MOS transistor N4 according to the equivalent circuit of FIG. 8, and the N-channel MOS transistors N2 and N4. This contributes to the reduction of the occupied area.

  In FIG. 9, n + diffusion regions FL33 and FL32 are formed by implanting N-type impurities at a position sandwiching polysilicon wiring layer PL31, so that an N-channel MOS transistor having polysilicon wiring layer PL31 as a gate electrode is formed. N9 is formed. Further, n + diffusion regions FL32 and FL31 are formed at positions sandwiching polysilicon wiring layer PL12, thereby forming N-channel MOS transistor N8 using polysilicon wiring layer PL12 as a gate electrode.

  In these N-channel MOS transistors N8 and N9, since polysilicon wiring layers PL31 and PL12 are juxtaposed, n + diffusion regions FL31 to 33 are arranged in a direction parallel to the second well boundary line and on the same straight line. Thus, n + diffusion region FL32 can be shared by N-channel MOS transistors N8 and N9. This sharing of n + diffusion region FL32 serves to connect the drain of N-channel MOS transistor N8 and the source of N-channel MOS transistor N9 according to the equivalent circuit of FIG. This contributes to the reduction of the occupied area.

  In N well region NW, p + diffusion regions FL11 and FL12 are formed by implantation of P-type impurities at positions sandwiching polysilicon wiring layer PL11. As a result, a P-channel MOS transistor P1 having the polysilicon wiring layer PL11 as a gate electrode is formed. Further, p + diffusion regions FL13 and FL14 are formed at positions sandwiching the polysilicon wiring layer PL12, thereby forming a P-channel MOS transistor P2 having the polysilicon wiring layer PL12 as a gate electrode.

  The arrangement positions of these P-channel MOS transistors P1 and P2 are determined according to the positions of the polysilicon wiring layers PL11 and PL12. The position intervals of the polysilicon wiring layers PL11 and PL12 are as shown in FIG. As in the first embodiment, it can be narrowed to the size of the p + diffusion regions FL12 and FL13 (minimum transistor pitch). In particular, the size of these p + diffusion regions FL12 and FL13 is made approximately the same as the n + diffusion regions FL22 of the first P well region PW1 and the n + diffusion regions FL32 and FL35 of the second P well region PW2. The total occupied area required for the memory cell layout can be minimized.

  This means that at the same time, the polysilicon wiring layers PL11, PL33 and PL31 can be arranged on the same straight line, and the polysilicon wiring layers PL21 and PL12 can be arranged on the same straight line.

  As shown in FIG. 9, one each for polysilicon wiring layers PL11, PL12, PL21, PL31 and PL33, p + diffusion regions FL11-14, and n + diffusion regions FL21-23, FL33-36. In the n + diffusion region FL31, two contact holes are provided for electrical connection with the upper layer.

  Next, a layer positioned above the layer shown in FIG. 9 will be described. FIG. 10 shows a layer including a first metal wiring layer formed on the layer shown in FIG. In the layer shown in FIG. 10, first metal wiring layer AL11 for electrically connecting lower n + diffusion region FL22, p + diffusion region FL12, and polysilicon wiring layer PL12 is formed. According to the equivalent circuit of FIG. 8, by this first metal wiring layer AL11, the drain of the N-channel MOS transistor N1, the source of the N-channel MOS transistor N3, the drain of the P-channel MOS transistor P1, and the second Connection to the input terminal of the CMOS inverter is achieved.

  In addition, first metal wiring layer AL12 for electrically connecting lower n + diffusion region FL35, p + diffusion region FL13, and polysilicon wiring layer PL11 is formed. According to the second metal wiring layer AL12, according to the equivalent circuit of FIG. 8, the drain of the N-channel MOS transistor N2, the source of the N-channel MOS transistor N4, the drain of the P-channel MOS transistor P2, Connection to the input terminal of the CMOS inverter is achieved.

  In particular, in the first metal wiring layer AL11, the contact portion between the n + diffusion region FL22 and the p + diffusion region FL12 is arranged on the same straight line as described above. The shape can be linear. The same applies to the first metal wiring layer AL12.

  Further, in the layer shown in FIG. 10, the first metal wiring layer AL15 for moving the connection point of the lower p + diffusion region FL11 and the first metal wiring for moving the connection point of the p + diffusion region FL14 are provided. Layer AL16 is formed, and the first metal wiring layer AL13 for moving the connection point of the lower polysilicon wiring layer PL21 and the first metal wiring for moving the connection point of the polysilicon wiring layer PL31 are formed. Layer AL14 and first metal wiring layer AL19 for moving the connection point of polysilicon wiring layer PL33 are formed.

  Further, in the same layer, a first metal wiring layer AL18 for electrically connecting lower p + diffusion regions FL34 and FL31 and moving a connection point with the upper layer is formed. According to the equivalent circuit of FIG. 8, the first metal wiring layer AL18 connects the sources of the N-channel MOS transistors N2 and N8.

  In particular, as shown in FIG. 9, since n + diffusion regions FL34 and FL31 are arranged on the same straight line in a direction perpendicular to the second well boundary line, each contact hole on these n + diffusion regions also has The straight line connecting the contact holes can be formed on the same straight line perpendicular to the second well boundary line. That is, the second metal wiring layer AL18 shown in FIG. 10 can be formed in a linear shape perpendicular to the second well boundary line.

  Next, a layer positioned above the layer shown in FIG. 10 will be described. FIG. 11 shows a layer including a second metal wiring layer formed on the layer shown in FIG. In the layer shown in FIG. 11, the power supply potential VDD is applied to the p + diffusion region FL11 via the first metal wiring layer AL15 shown in FIG. 10, and the p + diffusion region is supplied via the first metal wiring layer AL16. A second metal wiring layer AL21 for applying power supply potential VDD to FL14 is formed. That is, the second metal wiring layer AL21 functions as a power supply potential VDD line. In the equivalent circuit of FIG. 8, the connection between the source of the P-channel MOS transistor P1 and the power supply, and the source of the P-channel MOS transistor P2 And the connection with the power source.

  Further, via the first metal wiring layer AL17 shown in FIG. 10, the second metal wiring layer AL22 for applying the ground potential GND to the p + diffusion region FL21 and the first metal wiring layer AL18 are used. Thus, second metal interconnection layer AL23 for applying ground potential GND to p + diffusion regions FL31 and FL34 is formed. That is, these second metal wiring layers AL22 and AL23 function as a ground potential GND line, and serve to ground the sources of N-channel MOS transistors N1, N2, and N8 in the equivalent circuit of FIG.

  Further, the layer shown in FIG. 11 includes a second metal that functions as the first positive-phase bit line WBL1 connected to the lower p + diffusion region FL23 via the contact hole + first via hole shown in FIG. A wiring layer AL24, a second metal wiring layer AL25 connected to the p + diffusion region FL36 and functioning as the reverse phase bit line WBL2, and a second metal wiring layer AL25 connected to the p + diffusion region FL33 and functioning as the second positive phase bit line RBL. 2 metal wiring layers AL26 are formed.

  That is, the second metal wiring layers AL24 to AL26 are connected to the other of the semiconductor terminals (drain) of the N-channel MOS transistor N3 and the first positive-phase bit line WBL1 in the equivalent circuit of FIG. Connection between the other (drain) of the semiconductor terminal of the channel-type MOS transistor N4 and the negative-phase bit line WBL2, and connection between the other (drain) of the semiconductor terminal of the N-channel MOS transistor N9 and the second positive-phase bit line RBL. And fulfills.

  In particular, the second metal wiring layers AL24 to AL26 can be formed in a linear shape extending in a direction parallel to the first well boundary line. This means that the lengths of the first positive-phase bit line WBL1, the negative-phase bit line WBL2, and the second positive-phase bit line RBL are shortened in one memory cell.

  Further, the layers shown in FIG. 11 include a second metal wiring layer AL27 for moving a connection point between the lower first metal wiring layer AL13 and the upper layer, a lower first metal wiring layer AL19, and an upper layer. And a second metal wiring layer AL29 for moving the connection point between the lower first metal wiring layer AL14 and the upper layer are formed. The

  Next, a layer positioned above the layer shown in FIG. 11 will be described. FIG. 12 shows a layer including a third metal wiring layer formed on the layer shown in FIG. In the layer shown in FIG. 12, the polysilicon wiring layers PL21 and PL33 are electrically connected through the first metal wiring layer AL13 and the second metal wiring layer AL27 and function as the word line WWL. 3 metal wiring layers AL31 are formed. That is, the third metal wiring layer AL31 serves to connect the gates of the N-channel MOS transistors N3 and N4 and the word line WWL in the equivalent circuit of FIG.

  Further, a third metal wiring layer AL32 that is electrically connected to the polysilicon wiring layer PL31 via the first metal wiring layer AL14 and the second metal wiring layer AL29 and functions as the word line RWL is provided. It is formed. That is, the third metal wiring layer AL32 serves to connect the gate of the N-channel MOS transistor N6 and the word line RWL in the equivalent circuit of FIG.

  In particular, as shown in FIG. 12, linear metal wirings extending between the metal wiring layers in a direction perpendicular to the first well boundary line due to the positional relationship between the second metal wiring layers AL27 and AL28. Can be connected in layers. That is, the third metal wiring layer AL31 shown in FIG. 12 can be formed in a linear shape extending in the direction perpendicular to the first well boundary line. On the other hand, the third metal wiring layer AL32 can be arranged extending in parallel with the third metal wiring layer AL31 because the connection with the lower layer is only the second metal wiring layer AL29. This means that the lengths of the first word line WWL and the second word line RWL are shortened in one memory cell.

  As described above, according to the semiconductor memory device according to the third embodiment, the N-channel MOS transistor N3 functioning as the access gate and the N-channel MOS transistor N1 constituting the flip-flop circuit are connected to one semiconductor terminal. N + diffusion region FL22 is shared at the connection points of n +, and n + diffusion regions FL21 to 23 serving as semiconductor terminals are formed so as to be arranged in a straight line in a direction parallel to the first well boundary line. The area occupied by channel type MOS transistors N1 and N3 can be reduced. As a result, the integration degree of the memory cell array can be increased.

  In addition, second metal wiring layers AL24 to AL26 that sequentially function as the first positive-phase bit line WBL1, the negative-phase bit line WBL2, and the first positive-phase bit line WBL2 serve as the first and second well boundary lines. By being formed so as to be juxtaposed in parallel, the lengths of these bit lines can be shortened, so that the wiring capacity of the bit lines can be reduced, thereby enabling high-speed access. In particular, these bit lines can be narrowed to twice the minimum pitch of the transistors by the above arrangement.

  Further, by forming the third metal wiring layers AL31 and AL32 that function in order as the first word line WWL and the second word line RWL so as to be orthogonal to the first and second well boundary lines, Since the length of these word lines can be further shortened, the wiring capacity of the word lines can also be reduced, thereby enabling high-speed access.

  In addition, since the drain region forming storage nodes MA and MB is a common n + diffusion region, the area can be reduced, and parasitic capacitance is reduced, resulting in higher access speed at the time of writing. Can do.

  Furthermore, since the polysilicon wiring layer can be formed in a straight line, it is possible to increase a process margin due to mask displacement or the like when forming a layout pattern in the semiconductor manufacturing process.

Embodiment 4 FIG.
Next, a semiconductor memory device according to Embodiment 4 will be described. In the fourth embodiment, a layout configuration of another equivalent circuit configuring a 3-port SRAM cell will be described. FIG. 13 is a diagram illustrating an equivalent circuit of the semiconductor memory device according to the fourth embodiment. In FIG. 13, the first word line WWL, the first positive phase bit line WBL1, the first negative phase bit line WBL2, the P channel type MOS transistors P1 and P2, and the N channel type MOS transistor N1. Since the configuration consisting of .about.N4 is as shown in FIG. 8, the description thereof is omitted here.

  In FIG. 13, in addition to the above configuration, the gate of an N-channel MOS transistor N8 is connected to the storage node MA, and the source of the N-channel MOS transistor N8 is grounded. Further, the drain of the N-channel MOS transistor N8 is connected to the source of the N-channel MOS transistor N9, and the N-channel MOS transistor N9 has a gate connected to the second word line RWL1 and a drain connected to the second positive line. It is connected to the phase bit line RBL1.

  Further, the gate of an N-channel MOS transistor N10 is connected to the storage node MB, and the source of the N-channel MOS transistor N10 is grounded. Further, the drain of the N-channel MOS transistor N10 is connected to the source of the N-channel MOS transistor N11, and the N-channel MOS transistor N11 has a gate connected to the third word line RWL2 and a drain connected to the second reverse polarity. It is connected to the phase bit line RBL2.

  That is, the selection of the word line WWL, the first positive-phase bit line WBL1 and the negative-phase bit line WBL2 enables reading and writing of the stored value by the first port, and the second word line RWL1 and the second positive-phase bit line WBL2. By selecting the phase bit line RBL1, the stored value can be read out by the second port. Further, the stored value can be read by the third port by selecting the third word line RWL2 and the second reverse-phase bit line RBL2. In particular, the read operation by these second and third ports has the feature that it can operate completely independently from the first port without destroying the data of storage nodes MA and MB of the memory cell. Have.

  Here, the equivalent circuit itself shown in FIG. 13 has a known configuration as a conventional 3-port SRAM cell circuit, but the semiconductor memory device according to the fourth embodiment is characterized in its structure. 14 to 17 are layout diagrams of the memory cells of the semiconductor memory device according to the fourth embodiment. In the figure, various symbols such as contact holes and via holes are as shown in FIG.

  First, FIG. 14 shows a layer including a well region formed in a semiconductor substrate, a diffusion region formed in the well region, and a polysilicon wiring layer formed on the upper surface thereof.

  Also in the memory cell of the semiconductor memory device according to the fourth embodiment, as shown in FIG. 14, the first P-well region is sandwiched between the N-well region NW in the planar direction on the semiconductor substrate as in the first embodiment. PW1 and second P well region PW2 are arranged, and these well regions are formed so that the first well boundary line and the second well boundary line are parallel to each other. Although not shown, isolation regions exist between the N well region NW and the first P well region PW1, and between the N well region NW and the second P well region PW2, respectively.

  In FIG. 14, the N channel type MOS transistors N1, N3, N10 and N11 shown in FIG. 13 are formed in the first P well region PW1, and the P channel type MOS transistors P1 and P2 are formed in the N well region NW. N channel MOS transistors N2, N4, N8 and N9 are formed in the second P well region PW2.

  Below, the structure of each layer shown in FIGS. First, in the layer shown in FIG. 14, two polysilicon wiring layers PL21 extending in a direction perpendicular to the first well boundary line and juxtaposed in a straight line to the first P well region PW1 and PL22 is formed.

  Further, a polysilicon wiring layer PL11 extending in a straight line in a direction perpendicular to the first well boundary line is formed from the first P well region PW1 to the N well region NW. Note that one end portion of the polysilicon wiring layer PL11 is located on the second well boundary line as shown in FIG.

  Then, n + diffusion regions FL22 and FL23 are formed by N-type impurity implantation at a position sandwiching the polysilicon wiring layer PL21, thereby forming an N-channel MOS transistor N3 having the polysilicon wiring layer PL21 as a gate electrode. The Further, n + diffusion regions FL21 and FL22 are formed at positions sandwiching polysilicon wiring layer PL11, thereby forming N channel type MOS transistor N1 having polysilicon wiring layer PL11 as a gate electrode.

  In particular, since the N-channel MOS transistors N1 and N3 have the polysilicon wiring layers PL11 and PL21 juxtaposed, the n + diffusion regions FL21 to 23 are arranged in a direction parallel to the first well boundary line and in a straight line. Thus, n + diffusion region FL22 can be shared between N-channel MOS transistors N1 and N3. This sharing of the n + diffusion region FL22 serves to connect the drain of the N-channel MOS transistor N1 and the source of the N-channel MOS transistor N3 and the N-channel MOS transistors N1 and N3 according to the equivalent circuit of FIG. This contributes to a reduction in the area occupied by

  In FIG. 14, n + diffusion regions FL25 and FL26 are formed by implanting N-type impurities at a position sandwiching polysilicon wiring layer PL22, so that an N-channel MOS having polysilicon wiring layer PL22 as a gate electrode is formed. Transistor N11 is formed. Further, n + diffusion regions FL24 and FL25 are formed at positions sandwiching polysilicon wiring layer PL11, thereby forming N channel type MOS transistor N10 having polysilicon wiring layer PL11 as a gate electrode.

  Since these N-channel MOS transistors N10 and N11 have the polysilicon wiring layers PL22 and PL11 juxtaposed, the n + diffusion regions FL24 to 26 are arranged in the direction parallel to the first well boundary line and on the same straight line. Thus, the n + diffusion region FL25 can be shared by the N-channel MOS transistors N10 and N11. This sharing of n + diffusion region FL25 serves as a connection between the drain of N-channel MOS transistor N10 and the source of N-channel MOS transistor N11 and the N-channel MOS transistors N10 and N11 according to the equivalent circuit of FIG. This contributes to a reduction in the area occupied by

  On the other hand, the formation of the diffusion region and the polysilicon wiring layer in the second P well region PW2 and the N well region NW is as described in the description of FIG. 9 in the third embodiment, so that the description thereof is omitted here.

  Therefore, as shown in FIG. 14, polysilicon wiring layers PL11, PL33 and PL31 are arranged on the same straight line, and polysilicon wiring layers PL21, PL22 and PL12 are arranged on the same straight line.

  As shown in FIG. 14, polysilicon wiring layers PL11, PL12, PL21, PL22, PL31 and PL33, p + diffusion regions FL11-14, and n + diffusion regions FL21-23, FL26, FL33-36 One contact hole is provided in each case, and two contact holes are provided in the n + diffusion regions FL24 and FL31 for electrical connection with the upper layer.

  Next, a layer positioned above the layer shown in FIG. 14 will be described. FIG. 15 shows a layer including a first metal wiring layer formed on the layer shown in FIG. In the layer shown in FIG. 15, the formation of the second metal wiring layer on second P well region PW2 and N well region NW is as described in the description of FIG. 10 in the third embodiment. Those descriptions are omitted.

  In the layer shown in FIG. 15, the first P well region PW1 has a first n + diffusion region FL22, a p + diffusion region FL12, and a polysilicon wiring layer PL12 for electrically connecting the first n well region PW1. Metal wiring layer AL11 is formed. According to the equivalent circuit of FIG. 13, by this first metal wiring layer AL11, the drain of the N-channel MOS transistor N1, the source of the N-channel MOS transistor N3, the drain of the P-channel MOS transistor P1, and the second Connection to the input terminal of the CMOS inverter is achieved.

  In particular, in the first metal wiring layer AL11, the contact portion between the n + diffusion region FL22 and the p + diffusion region FL12 is arranged on the same straight line as described above. The shape can be linear.

  Further, in the layer shown in FIG. 15, the first metal wiring layer AL13 for moving the connection point of the lower polysilicon wiring layer PL22 and the first point for moving the connection point of the polysilicon wiring layer PL21. A metal wiring layer AL10 is formed.

  Further, in the same layer, a first metal wiring layer AL17 for electrically connecting lower p + diffusion regions FL24 and FL21 and moving a connection point with the upper layer is formed. According to the equivalent circuit of FIG. 13, the first metal wiring layer AL17 connects the sources of the N-channel MOS transistors N1 and N10.

  In particular, as shown in FIG. 14, since n + diffusion regions FL24 and FL21 are arranged on the same straight line in a direction perpendicular to the first well boundary line, each contact hole on these n + diffusion regions also has The straight line connecting the contact holes can be formed on the same straight line perpendicular to the first well boundary line. That is, the second metal wiring layer AL17 shown in FIG. 15 can be formed in a linear shape perpendicular to the first well boundary line.

  Next, the layer located above the layer shown in FIG. 15 will be described. FIG. 16 shows a layer including a second metal wiring layer formed on the layer shown in FIG. In the layer shown in FIG. 16, the power supply potential VDD is applied to the p + diffusion region FL11 via the first metal wiring layer AL15 shown in FIG. 15, and the p + diffusion region is supplied via the first metal wiring layer AL16. A second metal wiring layer AL21 for applying power supply potential VDD to FL14 is formed. That is, the second metal wiring layer AL21 functions as a power supply potential VDD line. In the equivalent circuit of FIG. 13, the connection between the source of the P-channel MOS transistor P1 and the power supply, and the source of the P-channel MOS transistor P2 And the connection with the power source.

  Further, the second metal wiring layer AL22 for applying the ground potential GND to the p + diffusion regions FL21 and FL24 via the first metal wiring layer AL17 shown in FIG. 15 and the first metal wiring layer AL18 are provided. A second metal wiring layer AL23 for applying ground potential GND to p + diffusion regions FL31 and FL34 is formed through the via. That is, these second metal wiring layers AL22 and AL23 function as a ground potential GND line, and serve to ground the sources of N-channel MOS transistors N1, N2, N8 and N10 in the equivalent circuit of FIG. is there.

  Further, in the layer shown in FIG. 16, the second metal functioning as the first positive-phase bit line WBL1 connected to the lower p + diffusion region FL23 through the contact hole + first via hole shown in FIG. Wiring layer AL24, second metal wiring layer AL42 connected to lower p + diffusion region FL26 and functioning as second antiphase bit line RBL2, and p + diffusion region FL36 functioning as antiphase bit line WBL2 And a second metal wiring layer AL26 connected to the p + diffusion region FL33 and functioning as the second positive-phase bit line RBL1.

  That is, these second metal wiring layers AL24 to AL26 and AL42 are connected to the other (drain) of the semiconductor terminal of the N-channel MOS transistor N3 and the first positive-phase bit line WBL1 in the equivalent circuit of FIG. The other (drain) of the semiconductor terminal of the N-channel MOS transistor N4 and the negative-phase bit line WBL2 are connected, the other (drain) of the semiconductor terminal of the N-channel MOS transistor N9 and the second positive-phase bit line RBL1 And the connection between the other (drain) of the semiconductor terminal of the N-channel MOS transistor N11 and the second anti-phase bit line RBL2.

  In particular, the second metal wiring layers AL24 to 26 and AL42 can be formed in a linear shape extending in a direction parallel to the first well boundary line. This is because the lengths of the first positive-phase bit line WBL1, the negative-phase bit line WBL2, the second positive-phase bit line RBL1, and the second negative-phase bit line RBL2 are made shorter in one memory cell. Means that.

  Further, the layers shown in FIG. 16 include a second metal wiring layer AL41 for moving a connection point between the lower first metal wiring layer AL13 and the upper layer, a lower first metal wiring layer AL19, and an upper layer. And second metal wiring layer AL27 for moving the connection point between the lower first metal wiring layer AL10 and the upper layer are formed. The Further, a second metal wiring layer AL29 that connects the polysilicon wiring layer PL31 and the upper layer is formed via the lower first metal wiring layer AL14.

  Next, a layer located above the layer shown in FIG. 16 will be described. FIG. 17 shows a layer including a third metal wiring layer formed on the layer shown in FIG. In the layer shown in FIG. 17, the polysilicon wiring layers PL21 and PL33 are electrically connected via the first metal wiring layer AL10 and the second metal wiring layer AL27, and the first word line WWL is used. A functioning third metal wiring layer AL31 is formed. That is, the third metal wiring layer AL31 serves to connect the gates of the N-channel MOS transistors N3 and N4 and the first word line WWL in the equivalent circuit of FIG.

  The third metal wiring is electrically connected to the polysilicon wiring layer PL31 via the first metal wiring layer AL14 and the second metal wiring layer AL29 and functions as the second word line RWL1. Layer AL32 is formed. That is, the third metal wiring layer AL32 serves to connect the gate of the N-channel MOS transistor N6 and the second word line RWL1 in the equivalent circuit of FIG.

  Further, a third metal wiring that is electrically connected to the polysilicon wiring layer PL22 via the first metal wiring layer AL13 and the second metal wiring layer AL41 and functions as the third word line RWL2 Layer AL33 is formed. That is, the third metal wiring layer AL33 serves to connect the gate of the N-channel MOS transistor N11 and the third word line RWL2 in the equivalent circuit of FIG.

  In particular, as shown in FIG. 17, a linear metal wiring layer extending between the metal wiring layers in a direction perpendicular to the first well boundary line due to the positional relationship between the second metal wiring layers AL27 and AL28. Can be connected with. That is, the third metal wiring layer AL31 shown in FIG. 17 can be formed in a linear shape extending in the direction perpendicular to the first well boundary line. On the other hand, the third metal wiring layer AL32 is connected only to the second metal wiring layer AL29, and the third metal wiring layer AL33 is connected only to the second metal wiring layer AL41. For this reason, they can be extended and arranged in parallel with the third metal wiring layer AL31. This means that the lengths of the first word line WWL, the second word line RWL1, and the third word line RWL2 are made shorter in one memory cell.

  As described above, according to the semiconductor memory device according to the fourth embodiment, the effects of the third embodiment can be enjoyed even in the 3-port SRAM cell.

Embodiment 5 FIG.
Next, a semiconductor memory device according to Embodiment 5 will be described. In the fourth embodiment, a layout configuration of another equivalent circuit constituting the differential read type 2-port SRAM cell will be described. FIG. 18 is a diagram illustrating an equivalent circuit of the semiconductor memory device according to the fifth embodiment.

  The equivalent circuit shown in FIG. 18 is implemented only in that the gates of the N-channel MOS transistors N9 and N11 are connected to each other and the connection line is a common second word line RWL in the equivalent circuit shown in FIG. This is different from Form 4. The other configuration is as shown in FIG. 13, and the description thereof is omitted here.

  Therefore, the operation is the same as that of the equivalent circuit shown in FIG. 13 except that the read operation is performed by the difference between the potential of the second positive-phase bit line RBL1 and the potential of the second negative-phase bit line RBL2. is there.

  Also, regarding the layout structure, only the second metal wiring layer layer corresponding to FIG. 16 and the third metal wiring layer layer corresponding to FIG. 17 are different, and the other lower layers are shown in FIG. 14 and FIG. Therefore, the description thereof is omitted here.

  Therefore, the layer located in the upper layer of the layer shown in FIG. 15 will be described below. 19 and 20 are layout diagrams of the memory cells of the semiconductor memory device according to the fifth embodiment. In particular, FIG. 19 shows a layer including a second metal wiring layer corresponding to FIG. Shows a layer including a third metal wiring layer corresponding to FIG.

  First, in the layer shown in FIG. 19, the power supply potential VDD is applied to the p + diffusion region FL11 via the first metal wiring layer AL15 shown in FIG. 15, and the p + is supplied via the first metal wiring layer AL16. A second metal wiring layer AL21 for applying power supply potential VDD to diffusion region FL14 is formed. That is, the second metal wiring layer AL21 functions as a power supply potential VDD line. In the equivalent circuit of FIG. 18, the connection between the source of the P-channel MOS transistor P1 and the power supply, and the source of the P-channel MOS transistor P2 And the connection with the power source.

  Further, the second metal wiring layer AL22 for applying the ground potential GND to the p + diffusion regions FL21 and FL24 via the first metal wiring layer AL17 shown in FIG. 15 and the first metal wiring layer AL18 are provided. A second metal wiring layer AL23 for applying ground potential GND to p + diffusion regions FL31 and FL34 is formed through the via. That is, these second metal wiring layers AL22 and AL23 function as a ground potential GND line, and serve to ground the sources of N-channel MOS transistors N1, N2, N8 and N10 in the equivalent circuit of FIG. is there.

  Further, the layer shown in FIG. 19 includes a second metal functioning as the first positive-phase bit line WBL1 connected to the underlying p + diffusion region FL23 via the contact hole + first via hole shown in FIG. Wiring layer AL24, second metal wiring layer AL42 connected to lower p + diffusion region FL26 and functioning as second antiphase bit line RBL2, and p + diffusion region FL36 functioning as antiphase bit line WBL2 And a second metal wiring layer AL26 connected to the p + diffusion region FL33 and functioning as the second positive-phase bit line RBL1.

  In other words, these second metal wiring layers AL24 to AL26 and AL42 are connected to the other (drain) of the semiconductor terminal of the N-channel MOS transistor N3 and the first positive-phase bit line WBL1 in the equivalent circuit of FIG. The other (drain) of the semiconductor terminal of the N-channel MOS transistor N4 and the negative-phase bit line WBL2 are connected, the other (drain) of the semiconductor terminal of the N-channel MOS transistor N9 and the second positive-phase bit line RBL1 And the connection between the other (drain) of the semiconductor terminal of the N-channel MOS transistor N11 and the second anti-phase bit line RBL2.

  In particular, the second metal wiring layers AL24 to 26 and AL42 can be formed in a linear shape extending in a direction parallel to the first well boundary line. This is because the lengths of the first positive-phase bit line WBL1, the negative-phase bit line WBL2, the second positive-phase bit line RBL1, and the second negative-phase bit line RBL2 are made shorter in one memory cell. Means that.

  19 includes a second metal wiring layer AL41 for moving a connection point between the lower first metal wiring layer AL13 and the upper layer, and a lower first metal wiring layer AL19 and the upper layer. A second metal wiring layer AL28 for moving a connection point between the first metal wiring layer AL10 and a lower metal wiring layer AL27 for moving a connection point between the lower first metal wiring layer AL10 and the upper layer; A second metal wiring layer AL29 for moving a connection point between the polysilicon wiring layer PL31 and the upper layer is formed through the one metal wiring layer AL14.

  Next, a layer positioned above the layer shown in FIG. 19 will be described. FIG. 20 shows a layer including a third metal wiring layer formed on the layer shown in FIG. In the layer shown in FIG. 20, the polysilicon wiring layers PL21 and PL33 are electrically connected via the first metal wiring layer AL10 and the second metal wiring layer AL27, and the first word line WWL is used. A functioning third metal wiring layer AL31 is formed. That is, the third metal wiring layer AL31 serves to connect the gates of the N-channel MOS transistors N3 and N4 and the first word line WWL in the equivalent circuit of FIG.

  Further, a third metal that electrically connects the polysilicon wiring layers PL22 and PL31 via the first metal wiring layer AL14 and the second metal wiring layer AL29 and functions as the second word line RWL. The wiring layer AL32 is formed. That is, the third metal wiring layer AL32 serves to connect the gates of the N-channel MOS transistors N9 and N11 and the second word line RWL in the equivalent circuit of FIG.

  In particular, as shown in FIG. 20, due to the positional relationship between the second metal wiring layers AL27 and AL28, a linear metal wiring layer extending between both metal wiring layers in a direction perpendicular to the first well boundary line. Can be connected with. That is, the third metal wiring layer AL31 shown in FIG. 20 can be formed in a linear shape extending in the direction perpendicular to the first well boundary line. The same applies to the third metal wiring layer AL32. This means that the lengths of the first word line WWL and the second word line RWL are shortened in one memory cell.

  As described above, according to the semiconductor memory device according to the fifth embodiment, even in the differential read type two-port SRAM cell capable of a faster and more stable read operation, the effect of the third embodiment can be enjoyed. it can.

  NW N well region, PW1 first P well region, PW2 second P well region, FL11, FL12, FL21-26, FL31-36 n + diffusion region, FL11, FL12 p + diffusion region, AL11, AL12, AL15-18 1st metal wiring layer, AL21-29, AL41, AL42 2nd metal wiring layer, AL31-33 3rd metal wiring layer, N1-6, N8-11 N channel type MOS transistor, P1, P2 P channel type MOS transistor

This invention relates to semiconductive KaradaSo location, and more particularly to a multiport SRAM (Static Random Access Memory) cell layout of a CMOS configuration.

The present invention has been made to solve the above problems, and relates to a P-well region and an N-well region in which a pair of CMOS inverters constituting a multiport SRAM cell is formed. The P-well region is divided into two. Arranged on both sides of the N well region, the boundary thereof is located in parallel with the bit line, and a pair of access gates are formed in two divided P well regions, respectively, so that the length in the bit line direction is short. and to obtain a semiconductor KaradaSo location having memory cells.

Claims (27)

A first word line, a second word line, a first positive phase bit line, a first negative phase bit line, a second positive phase bit line, and a second negative phase bit line;
A first CMOS inverter comprising a first N-channel MOS transistor and a first P-channel MOS transistor to form a CMOS inverter;
A CMOS inverter is configured by including a second N-channel MOS transistor and a second P-channel MOS transistor, and an input terminal of the CMOS inverter is used as a first storage node as an output terminal of the first CMOS inverter. A second CMOS inverter connected to the input terminal of the first CMOS inverter as an output terminal of the CMOS inverter as a second storage node;
A third N-channel MOS transistor having a gate connected to the first word line, a drain connected to the first positive-phase bit line, and a source connected to the first storage node;
A fourth N-channel MOS transistor having a gate connected to the first word line, a drain connected to the first reversed-phase bit line, and a source connected to the second storage node;
A fifth N-channel MOS transistor having a gate connected to the second word line, a drain connected to the second positive-phase bit line, and a source connected to the first storage node;
A sixth N-channel MOS transistor having a gate connected to the second word line, a drain connected to the second reversed-phase bit line, and a source connected to the second storage node;
With
The first and second P-channel MOS transistors are formed in an N-well region, the first, third, and fifth N-channel MOS transistors are formed in a first P-well region, and the first 2. A semiconductor memory device, wherein the second, fourth and sixth N-channel MOS transistors are formed in a second P well region.   The semiconductor memory device according to claim 1, wherein the first and second P well regions are formed on both sides of the N well region.   The extending directions of the first positive-phase bit line, the first negative-phase bit line, the second positive-phase bit line, and the second negative-phase bit line, and the first and second P 3. The semiconductor memory device according to claim 1, wherein a boundary line between a well region and the N well region is parallel.   The boundary line between the first and second P-well regions and the N-well region is orthogonal to the extending direction of each of the first and second word lines. Semiconductor memory device. Each of the first P-channel MOS transistor and the first, third, and fourth N-channel MOS transistors has a gate region parallel to the extending direction of the first word line and Formed to be on the same straight line,
Each of the second P-channel MOS transistor and the second, fifth, and sixth N-channel MOS transistors has a gate region parallel to the extending direction of the second word line and 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed so as to be positioned on the same straight line. In the third and fifth N-channel MOS transistors, the source diffusion region and the drain diffusion region are positioned on the same straight line, and with respect to the extending direction of the first and second positive-phase bit lines. Formed in parallel,
In the fourth and sixth N-channel MOS transistors, the source diffusion region and the drain diffusion region are located on the same straight line, and with respect to the extending direction of the first and second antiphase bit lines. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed so as to be arranged in parallel. The drain diffusion regions of the third and fifth N-channel MOS transistors are formed by a common first n + diffusion region,
2. The semiconductor memory device according to claim 1, wherein drain diffusion regions of the fourth and sixth N-channel MOS transistors are formed by a common second n + diffusion region. The drain diffusion region of the first N-channel MOS transistor and the drain diffusion region of the third and fifth N-channel MOS transistors are connected by a first metal wiring in an upper layer through a contact hole,
The drain diffusion region of the second N-channel MOS transistor and the drain diffusion region of the fourth and sixth N-channel MOS transistors are connected by a second metal wiring in the upper layer through a contact hole. The semiconductor memory device according to claim 1.   9. The semiconductor memory device according to claim 8, wherein the extending direction of the first and second metal wirings is parallel to the extending direction of the first and second word lines.   The extending directions of the first and second positive-phase bit lines, the first and second negative-phase bit lines, the power supply line, and the GND line are in relation to the first and second word lines. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is vertical. The drain diffusion regions of the first, third and fifth N-channel MOS transistors are formed by a common first n + diffusion region,
2. The semiconductor memory device according to claim 1, wherein drain diffusion regions of the second, fourth and sixth N-channel MOS transistors are formed by a common second n + diffusion region. The first n + diffusion region and the drain diffusion region of the first P-channel MOS transistor are connected by an upper first metal wiring through a contact hole,
12. The second n + diffusion region and the drain diffusion region of the second P-channel MOS transistor are connected by an upper second metal wiring through a contact hole. The semiconductor memory device described. A first word line, a second word line, a first positive phase bit line, a first negative phase bit line, a second positive phase bit line,
A first CMOS inverter comprising a first N-channel MOS transistor and a first P-channel MOS transistor to form a CMOS inverter;
A CMOS inverter is configured by including a second N-channel MOS transistor and a second P-channel MOS transistor, and an input terminal of the CMOS inverter is used as a first storage node as an output terminal of the first CMOS inverter. A second CMOS inverter connected to the input terminal of the first CMOS inverter as an output terminal of the CMOS inverter as a second storage node;
A third N-channel MOS transistor having a gate connected to the first word line, a drain connected to the first positive-phase bit line, and a source connected to the first storage node;
A fourth N-channel MOS transistor having a gate connected to the first word line, a drain connected to the first reversed-phase bit line, and a source connected to the second storage node;
A fifth N-channel MOS transistor having a gate connected to the first storage node;
A sixth N-channel MOS transistor having a gate connected to the second word line, a drain connected to the second positive-phase bit line, and a source connected to the drain of the fifth N-channel MOS transistor When,
With
The first and second P-channel MOS transistors are formed in an N-well region, and the first and third N-channel MOS transistors are formed in a first P-well region, and the second and second 4. A semiconductor memory device characterized in that the fourth, fifth and sixth N-channel MOS transistors are formed in a second P well region. A third word line, a second anti-phase bit line,
A seventh N-channel MOS transistor having a gate connected to the second storage node;
An eighth N-channel MOS transistor having a gate connected to the third word line, a drain connected to the second reversed-phase bit line, and a source connected to the drain of the seventh N-channel MOS transistor When,
With
14. The semiconductor memory device according to claim 13, wherein the seventh and eighth N-channel MOS transistors are formed in the first P well region.   15. The semiconductor memory device according to claim 14, wherein the second and third word lines are a single common word line.   16. The semiconductor memory device according to claim 13, wherein the first and second P well regions are formed on both sides of the N well region.   The extending directions of the first positive-phase bit line, the first negative-phase bit line, and the second positive-phase bit line, and the first and second P-well regions and the N-well region 16. The semiconductor memory device according to claim 13, 14 or 15, wherein the boundary line is parallel.   The boundary line between the first and second P-well regions and the N-well region is perpendicular to the extending direction of each of the first and second word lines. The semiconductor memory device described in 1. In the first P-channel MOS transistor and the first, fourth and sixth N-channel MOS transistors, the gate regions are located on the same straight line, and the first word line extends. Formed parallel to the direction,
In the second P-channel MOS transistor and the second, third and fifth N-channel MOS transistors, the gate regions are located on the same straight line, and the second word line extends. 16. The semiconductor memory device according to claim 13, 14 or 15, wherein the semiconductor memory device is formed so as to be arranged in parallel to a direction. In the first and third N-channel MOS transistors, the drain diffusion region of the first N-channel MOS transistor and the source diffusion region of the third N-channel MOS transistor are located on the same straight line, And formed so as to be arranged parallel to the extending direction of the first positive-phase bit line,
In the second and fourth N-channel MOS transistors, the drain diffusion region of the second N-channel MOS transistor and the source diffusion region of the fourth N-channel MOS transistor are located on the same straight line, And formed so as to be arranged in parallel to the extending direction of the first reversed-phase bit line,
In the fifth and sixth N-channel MOS transistors, the drain diffusion region of the fifth N-channel MOS transistor and the source diffusion region of the sixth N-channel MOS transistor are located on the same straight line, 16. The semiconductor memory device according to claim 13, wherein the semiconductor memory device is formed so as to be arranged in parallel to the extending direction of the second positive-phase bit line. The drain diffusion region of the first N-channel MOS transistor and the source diffusion region of the third N-channel MOS transistor are formed by a common first n + diffusion region,
The drain diffusion region of the second N-channel MOS transistor and the source diffusion region of the fourth N-channel MOS transistor are formed by a common second n + diffusion region,
14. The drain diffusion region of the fifth N-channel MOS transistor and the source diffusion region of the sixth N-channel MOS transistor are formed by a common third n + diffusion region. The semiconductor memory device according to 14 or 15.   14. The second P-channel MOS transistor and the second and fifth N-channel MOS transistors have their gate regions connected by a linear common polysilicon wiring. , 14 or 15.   The extending directions of the first and second positive phase bit lines, the first negative phase bit line, the power supply line, and the GND line are perpendicular to the first and second word lines. The semiconductor memory device according to claim 13, 14 or 15. Each of the first P-channel MOS transistor and the first, fourth, sixth, and seventh N-channel MOS transistors has a gate region parallel to the extending direction of the first word line. And formed on the same straight line,
Each of the second P-channel MOS transistor and the second, third, fifth and eighth N-channel MOS transistors has a gate region parallel to the extending direction of the second word line. 16. The semiconductor memory device according to claim 14, wherein the semiconductor memory device is formed so as to be positioned on the same straight line. In the first and third N-channel MOS transistors, the drain diffusion region of the first N-channel MOS transistor and the source diffusion region of the third N-channel MOS transistor are the first positive-phase bit line. Are formed so as to be parallel to the extending direction of and located on the same straight line,
In the second and fourth N-channel MOS transistors, the drain diffusion region of the second N-channel MOS transistor and the source diffusion region of the fourth N-channel MOS transistor are the first antiphase bit line. Are formed so as to be parallel to the extending direction of and located on the same straight line,
In the fifth and sixth N-channel MOS transistors, the drain diffusion region of the fifth N-channel MOS transistor and the source diffusion region of the sixth N-channel MOS transistor are the second positive-phase bit line. Are formed so as to be parallel to the extending direction of and located on the same straight line,
In the seventh and eighth N-channel MOS transistors, the drain diffusion region of the seventh N-channel MOS transistor and the source diffusion region of the eighth N-channel MOS transistor are the second antiphase bit line. 16. The semiconductor memory device according to claim 14, wherein the semiconductor memory device is formed so as to be parallel to the extending direction of and located on the same straight line. The drain diffusion region of the first N-channel MOS transistor and the source diffusion region of the third N-channel MOS transistor are formed by a common first n + diffusion region,
The drain diffusion region of the second N-channel MOS transistor and the source diffusion region of the fourth N-channel MOS transistor are formed by a common second n + diffusion region,
The drain diffusion region of the fifth N-channel MOS transistor and the source diffusion region of the sixth N-channel MOS transistor are formed by a common third n + diffusion region,
15. The drain diffusion region of the seventh N channel type MOS transistor and the source diffusion region of the eighth N channel type MOS transistor are formed by a common fourth n + diffusion region. 15. The semiconductor memory device according to 15. The second P-channel MOS transistor and the second and fifth N-channel MOS transistors have their gate regions connected by a linear common first polysilicon wiring,
The first P-channel MOS transistor and the first and seventh N-channel MOS transistors have their gate regions connected by a linear common second polysilicon wiring. The semiconductor memory device according to claim 14 or 15.

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