JPH0897299A - Many-cell memory - Google Patents

Abstract

PURPOSE: To effectively reset a memory by using an auxiliary reset mechanism, which is separated from the memory itself and does not require changes in memory itself and by an additional auxiliary reset control circuit for decreased circuit capacity. CONSTITUTION: A reset link 21 is internally connected to the respective resettable cells of an array 11. Therefore, the single reset control signal effectively causes the reset of all cells of the array. The contents or the state of each reset state circuit (or reset-state memory cell) in the array 11 is used to mask the contents of the words related to a memory array 15 in the controlled state, every time the word is read out. When the reset memory cell is cleared, all the memory words addressed by the mask are outputted as zero, regardless of the bit state of the word related to the memory at that time.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to semiconductor memory circuits, and more particularly to a mechanism for effectively resetting a random access memory by coalescing an auxiliary reset control circuit array of reduced circuit capacity. The components of the auxiliary reset control circuit array are separate from, but associated with, each word of the random access memory.

[0002]

2. Description of the Related Art Resetting a random access memory
Clearing or "zeroing" the contents of all storage locations or cells of the memory, typically by addressing each storage location and writing a "0" to each cell in response to the generation of a reset control signal. Customarily means. Such a mechanism is undesired and slow, as the transient peak currents required to clear all memory arrays are extremely large and are likely to trail a few clock cycles of the memory access clock. There needs to be sufficient real estate of the semiconductor to form.

[0003]

One means of solving this problem is disclosed in U.S. Pat. No. 4,789,967, which divides the reset process into sub-portions or blocks of memory, It seeks to provide a slight reduction with respect to both reset current requirements (by resetting only that part of the memory or part of the memory of interest) and some improvement in reset speed. Unfortunately, the reset mechanism disclosed in the Liou et al. Patent further requires that the reset current be supplied directly to the memory itself, so that even if less than full memory is selectively accessed, the reset operation will not occur. It still means changing the contents of a plurality of memory cells in each block of memory to be reset.

[0004]

SUMMARY OF THE INVENTION According to the present invention, rather than changing or clearing the contents of each storage location of one or more segments or blocks of memory for a full or partial reset of the memory, An auxiliary reset mechanism is used that is separate from the memory itself and does not require modification of the contents of the memory itself. Generally, the memory in which the present invention is implemented can be any read / write device such as NMOS, PMOS, CMOS, bipolar, GaAs, and magnetic circuits.
Includes writing technology.

In a random access memory capable of storing M words of N bits, the auxiliary mechanism of the present invention preferably comprises a plurality of M reset state circuits, each associated with an M word of memory. This reset state circuit
Additional "resettable" for each word of memory
It includes memory cells and is formed of multi-cell units that are integrated or separate within the physical structure of the memory itself and are used for writing to or reading from the memory. This additional multi-reset circuit unit need not be formed exactly with memory cells, but can be formed with multiple reset logic circuits. In a preferred embodiment, the resettable memory of the present invention comprises "9 transistors (9
T) ”dual port CMOS.

To reset one or more words of memory, the associated reset state circuitry is placed in a state representative of a reset state. Here, the multi-reset state unit is formed by resettable memory cells, and the initialization of the reset state circuit means resetting of such resettable memory cells. The content or state of each reset state circuit is used to controllably mask the content of the associated word of memory as the word is read. This mask mechanism is AND,
It includes appropriate logical operations such as NAND, NOR, and OR functions.

[0007]

When the reset memory cell is cleared, the mask causes the addressed memory word to be output as all zeros, regardless of the contents of the word associated with it in memory. Whenever a new word value is written to memory, its associated reset state circuit is simultaneously accessed and a valid or non-reset bit of the "1" indication is stored in the reset state circuit. Then, when this word is read from memory, the value of the mask bit ("1") stored in its associated reset cell.
However, the word contents are output as they are.

Where the memory is implemented as a J column by K row array of dual port memory cells configured in CMOS to store J bit K words,
The reset mechanism includes AND, NAND, NOR, and OR
Memory array composed of MOSFETs as memory cells composed of resettable MOSFETs respectively associated with additional J-bit K words of logical operations in the (J + 1) th column of K Can be integrated with. Each memory cell made up of this additional column of MOSFETs preferably has essentially the same configuration as the respective cell of the memory body, and the resetting of the cell M
It includes a "reset" MOSFET formed of an additional length or strip of insulating polysilicon located along the rows of OSFETs. Multiple gate tabs
Each memory cell extends over a thin layer of oxide gate between the drain and source of adjacent MOSFETs.
The drain and source of the "reset" MOSFET are common to the drain and source regions of adjacent MOSFETs, so reorganization of the MOSFET region of the dual port CMOS memory cell pattern is not necessary.

An additional length of polysilicon is coupled to receive the reset control signal. When a reset signal is applied to a polysilicon reset link, it will propagate or "ripple" along the link.
Therefore, the reset MOSFETs are sequentially switched on, thereby sequentially resetting all resettable memory cells. The time required to reset a cell in a column of reset memory cells depends on the total effective RC time constant of the polysilicon line. The total effective RC time constant is the interconnect capacitance resistance of the polysilicon line and the reset M
It is dominated by the parasitic gate capacitance of the OSFET. In order to increase the speed at which the reset MOSFET is reset, the geometry and interconnect structure of the polysilicon links are spirally routed from strips extended between cells by multiple distribution and loopback coupling along the links. , Which causes the multiple groups of reset transistors to be "ripple-reset" in a parallel fashion. If the memory uses multiple columns of reset memory cells, one reset line is located between adjacent columns of reset memory cells with tabs extending on either side of the reset line.

Once the memory is reset, each time a data word is written to the memory, a "1" is written to the K × 1 associated resettable memory cell, thereby causing the associated resettable memory cell. Put it in a state where it is not reset.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the accompanying drawings by way of examples. Before describing in detail the particular improved memory reset mechanism according to the present invention, the present invention mainly belongs to a new structural combination of conventional signal processing circuits and components, which are specifically detailed. It should be noted that it does not belong to the structure Accordingly, the structure, control and organization of these conventional circuits and components is illustrated in the drawings by block diagrams, which show only those particular details corresponding to the invention and are readily understood, and which are described herein. It is intended to avoid obscuring the disclosure with structural details that will be readily apparent to those with ordinary skill in the art. Thus, the block diagrams in each figure do not necessarily represent the structural organization of the mechanics of a typical system, but are primarily represented by convenient functional groups that represent the major structural components of this system, The present invention can be more easily understood by the following.

As mentioned above, the conventional mechanism for resetting one or more words in a memory array has been to reset or clear (write a "0") to the actual storage location in the memory array. Therefore, conventionally, resetting the entire memory array requires write access to each storage location, which is time consuming and, at the same time, leads to high current demanding operations. According to the present invention, rather than modifying or clearing the contents of each storage location of the entire memory as suggested by the detailed illustration in the 1967 patent of Liou et al. The reset is performed except for the contents of the memory array body.

FIG. 1 schematically shows a first embodiment according to the present invention, which comprises a reset state circuit 11 and a mask circuit 13 coupled to a random access memory 15. The random access memory 15 can be configured in a conventional memory array configuration such as a memory cell array of J columns × K rows capable of storing M × N memory words. For the purposes of the example shown, memory 15 has (J = 24 columns) × (K = 1
024 rows), and M = 102.
It stores 4 words, each word is N = 24 bits.
That is, each row of the array stores a 24-bit word, while each column is associated with a respective bit.

The reset state circuit 11 includes a memory array 15
Acting as an auxiliary storage unit for storing reset state information for each word of the array, access to circuit 11 need not even access the memory array itself to reset one or more words of the array. . N = 2
102 for storing 4-bit M = 1024 words
In the displayed example of a 4 × 24 cell array, the auxiliary reset state storage circuit 11 has a 24-bit M = 1 in the memory 15.
Corresponding multiple M = 1, each associated with 024 words
024 reset state circuit. For this purpose, the reset state circuit 11 can be configured with an additional 1-bit long (1024 × 1) array of resettable memory cells separated from the memory 15. The respective address lines for the memory 15 are also coupled in parallel to the reset cell array 11, so that whenever one of the words of the memory 15 (one in 1024 rows in this example) is accessed, the 1-bit array 11 is accessed. Its associated reset state cell is also addressed.

To reset one or more words of memory, the reset state circuit or circuits associated with it of array 11 are placed in a state (reset or written as a "0") that represents a reset state. A multi-reset state unit can be reset directly without causing the cell to be written with a "0" (as provided by using the resettable memory cell shown in FIGS. 7, 8 and 9 described below). Placing a reset state circuit in a reset state means coupling the reset signal to the reset link 21, so that the reset signal is transmitted through the array and effectively the array. You can reset each cell in. Alternatively, one or more reset links are used to reset individual or groups of reset cells depending on the circuit configuration selected. The external array can be configured such that the reset line associated with each cell of the array is isolated or all words are written to the reset state in parallel.

For purposes of this disclosure, reset link 2
1 is internally coupled to each of the resettable cells of array 11, so that a single reset control signal effectively causes a reset of all cells of array 11. As pointed out above, the content or state of each reset state circuit (or reset state memory cell) within array 11 controllably masks the content of the associated word of memory array 15 each time the word is read. Used to When the reset memory cell is cleared, then the memory word addressed by the mask is output as all zeros, regardless of the state of the bits of the associated word of memory. This mask operation is performed by the memory 1
5 Read contents of each word and reset state array 1
This can be easily accomplished by logically ANDing with the associated reset state mask bit stored in 1. Therefore, in this example, the lines 23 of the 24 columns of the memory 15 are
Are 24 2-input AND gates 27-1, ... 27-
24 first inputs 25-1, ... 25-2
Connected to four. The mask input 28 of each AND gate 27 is commonly coupled from the reset state memory array 15 to a single column link 31. AND gate 27
, ..., 27-24 provide an N = 24 bit output link 33 from which the word accessed from memory 15 is extracted.

As pointed out above, 10 of memory 15
Each time one of the 24 rows is read, its associated reset state cell in the 1-bit long array 11 is also addressed. When each cell of array 11 is reset, its mask output link 31 will then be "0" for any address that is read, and therefore AND
The outputs of the gate 27 are all zero. Thereafter, each time a new word value is written to memory 15, its associated reset state circuit in array 11 is correspondingly accessed,
A valid or non-reset bit represented by "1" is stored in the reset state circuit. Then, when the word is read from the memory 15, the mask bit ("1") of the mask bit stored in the reset cell associated with the word is read.
Value) is ANDed with the contents of link 23 and the contents of the word are output on link 33.

Although the reset mask array 11 of the embodiment shown in FIG. 1 has been described as being formed of a multi-cell 1-bit long memory array, it does not need to be formed exactly by the memory cells and is generally used. Can be formed by a plurality of standard logic circuits 11 and respective address lines 35 coupled in parallel with the address lines of the rows for the array 15, which is shown diagrammatically in FIG.

In accordance with the preferred embodiment of the present invention illustrated diagrammatically in FIG. 3, an auxiliary 1-bit long reset mask array is provided for additional or (N + 1) th column 11 of M.
A single bit resettable memory cell of A is integrated with the memory array 41, and the single bit resettable memory cell is 1024 × 2 of memory.
It is associated with M = 1024 words of N = 24 bits in the storage portion A of the word of the 4-bit length. According to a preferred implementation of the cells of the word store A of the memory array 41, each cell is formed by a cross-coupled inverting circuit composed of a set of MOSFETs, an electrical schematic of which is shown in FIG. The type inversion circuits 51 and 53 have the semiconductor wafer patterns shown in FIGS. 5 and 6, and further, four memory cells 15-1 and 15 in the entire array are shown in FIGS.
The memory pattern layouts for the -2, 15-3, and 15-4 groups are shown. (In the circuit shown in FIG. 4 and the pattern layouts in FIGS. 5 and 6, the source, drain, and gate electrodes are denoted by the symbols S,
Marked D and G, respectively, the symbol P of MOSFET
0, P1, and N0-N5. ) Cross-coupled inverting circuits 51, 53 (consisting of N and P channel MOSFET sets N0 / P0 and N1 / P1 respectively) are complementary output links 61, 63, respectively.
And the output link has M channels for N-channel access.
Bit lines 71A, 71B and 71ABA through a commonly connected set of OSFETs N2, N4 and N3, N5
R and 71BBAR, respectively. The memory cells are addressed by address ports 81A and 81B, which are respectively access N-channel MO.
It is coupled to the gate electrodes (G) of SFETs N2, N4 and N3, N5.

The present invention is not limited to the use of the particular eight transistor memory cell structure shown in FIGS. 4 and 5, but other memory cell structures may have the auxiliary reset mask described herein. It can be used without deviating from its function and use. For example, single port memory cells can be used rather than dual port memory cells. In the latter case,
One of the sets of access MOSFETS and their associated bits and access lines are not used, so in the circuits shown in FIGS. 4 and 5, the single port version includes six MOSFETS rather than eight. The dual port version of FIGS. 4 and 5 has the advantage that a write operation to one cell of the memory can be performed simultaneously with a read operation of another memory cell. Also, simultaneous dual read of the same cell can be achieved through both A and B access ports.

In accordance with the present invention, the dual port CMOS memory cell configurations of FIGS. 4, 5 and 6 include a reset control transistor (MOSFET) N6 as in the embodiment shown in FIGS. 7, 8 and 9. It can be increased by including it. Beneficially, the reset MOSFET N
6 can be easily incorporated into the pattern layouts of FIGS. 5 and 6 by overlapping additional lengths of insulating polysilicon 91, as shown in the pattern layouts of FIGS. 8 and 9. The polysilicon runs along the length of the memory cell and includes a plurality of gate tabs 93, each of which includes a drain / source of each memory cell, a thin oxide gate between N4D / S and ground. It extends on layers. Reset MOS
The drain N6D and source N6S of the FET N6 are common to the adjacent drain / source regions of MOSFET N4 and ground, N4D / S and ground, respectively, and thus the dual port CMOSRA of FIGS. 5 and 6.
There is no need to reorganize the area of the MOSFET in the M cell pattern. A slight increase in the drain / source region of the MOSFET N4 and the common region of the ground is shown in FIGS. 8 and 9. However, this increase does not mean to increase the area occupied by the entire memory because the reset transistor N6 is introduced. If the memory array includes additional columns of reset memory cells to form the integrated structure of FIG. 3, the size of the memory is such that one additional bit provides the occupied area of polysilicon line 91. , Slightly compared to the standard column width (in the direction of the word line)
To increase. Adjacent columns of reset cells can share the same reset line 91 if the memory parameters dictate the use of multiple columns of reset memory cells.

An additional length of polysilicon 91 is coupled to the reset port 95 and is connected to the reset control input (2 in FIG. 3).
1A) is attached to it. The resistance imposed by the sequential portion of the polysilicon reset link 91 between the tabs 93 to the gate electrode N6G of the reset transistor N6 is marked by resistors R0 and R1. For example, when a reset signal is applied to the polysilicon reset link 91 to provide an "instantaneous" clear of memory, the reset signal is transmitted or "flows" along the link, each cell to which the reset line 91 is connected. Of each MOSFET N6 are sequentially switched on, thereby sequentially resetting all resettable memory cells. M in the (N + 1) th column (for example, 1024)
The time required to reset the cell of FIG. 2 depends on the total effective RC time constant of polysilicon line 91. The total effective RC time constant is dominated by the interconnect capacitance resistance of polysilicon line 91 and the parasitic gate capacitance of reset MOSFET N6. In order to increase the speed at which MOSFET N6 is reset, the geometric and interconnect structures of link 91 are extended from strip to spiral path between cells by multiple distribution and loopback coupling along the link. Modified so that multiple groups of reset transistors are "ripple reset" in a parallel fashion
Becomes The spiral resistance path increases total resistance and length, and is slower. Coupling of parallel paths reduces resistance and thereby increases speed. As mentioned earlier, if the memory uses multiple columns of reset memory cells,
One reset line is located between adjacent columns of reset memory cells with tabs extending on either side of the reset line. Therefore, the structure chosen is a trade-off between speed and peak power.

As will be appreciated from the above description, rather than changing or clearing the contents of each storage location of one or more portions or blocks of memory for a full or partial reset of the memory. The present invention provides an auxiliary reset mechanism, which is separate from the reset cell, where the data is bit and bit BAT.
There is no need to change the contents of the memory stored via the R input / output lines. For a random access memory capable of storing N-bit M words, the auxiliary mechanism of the present invention preferably includes a plurality of M reset state circuits, each associated with a M word of memory. It is possible to convert a column of memory cells into a column of reset cells by modifying an 8-transistor dual-port CMOS RAM cell relatively minor with essentially the addition of a layer of polysilicon. It is possible. Resetting the memory means simply supplying the reset signal to the added polysilicon line, thus causing the reset signal to "flow" along the poly line, sequentially resetting each reset cell. Direct access to the memory word cells is not required because the state of each reset cell is used on read to controllably mask the contents of the associated word of memory. As a result, the required reset current value and the length of time to reset the memory are reduced.

The reset mechanism of the random access memory array includes an auxiliary reset circuit, which does not require modification of the contents of the memory itself. For a random access memory that can store M words of N bits, the auxiliary mechanism includes a plurality of M reset state circuits, each associated with M words of memory. This reset state circuit preferably consists of an additional "resettable" memory cell for each word of the memory, integrated within the structure of the memory itself. To reset one or more words of memory, the associated reset state circuit is placed in a state representative of a reset state. The state of each reset state circuit is used to controllably (e.g., logically AND) the contents of the associated word of memory as the word is read.
When the reset memory cell is cleared, the mask causes the addressed word of memory to be output as all zeros, regardless of the contents of the associated word of memory.

[Brief description of drawings]

FIG. 1 illustrates an embodiment of a J × K memory array and associated K × 1 reset state circuit array according to the present invention.

FIG. 2 is a diagram showing a modification of the embodiment of FIG.
The reset state circuit is formed of a plurality of standard logic circuits, each address line being coupled in parallel with the address line of a row of the array.

FIG. 3 shows an auxiliary 1-bit long reset mask array integrated with a memory array as an additional column of M single-bit resettable memory cells.

4 is an electric circuit diagram of a memory cell used in a word storage unit of the memory array of FIG. 3 configured with dual port CMOS.

FIG. 5 illustrates a semiconductor wafer pattern for implementing an array of portions of the memory cell shown in FIG.

6 shows a semiconductor wafer pattern for implementing an array of parts of the memory cell shown in FIG.

7 is an electrical schematic diagram of an augmented memory cell configured with the dual port MOSFET of FIG. 4 to provide a reset MOSFET.

8 illustrates a semiconductor wafer pattern for implementing an array of portions of the reset memory cell of FIG.

9 illustrates a semiconductor wafer pattern for implementing an array of portions of the reset memory cell of FIG.

[Explanation of symbols]

11, 11A Reset state circuit 13 Mask circuit 15, 15A Random access memory 21, 21A Reset link 23, 23A 24 column line 25-1 to 25-24 First input of 2-input AND gate 27-1 to 27-24 Two-input AND gate 28-1 to 28-24 Second input of two-input AND gate 31, 31A Single column link 33 Output link 41 Memory array 51, 53 Cross-coupled inverting circuit 61, 63 Output link 71A, 71B Bit line 71ABAR, 71BBAR Complementary bit line 81A, 81B Address port 15-1, 15-2, 15-3, 15-4 Memory cell 91 Insulated polysilicon reset link 93 Tab 95 Reset port

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location G11C 11/401 G11C 11/34 371 E (72) Inventor Charles W Longway United States Florida 32907 Palm Bay NW Guillarda Circle 1214

Claims (10)

[Claims] 1. A multi-cell memory formed of an array of memory cells composed of MOSFETs, wherein each of the MOSFET-structured memory cells has normal and complementary bit line ports connected to a word line. A cross-coupled MOSFET inverter circuit coupled by a MOSFET switch circuit controlled by a select port that is selected, each of the selected ones of the MOSFET configuration memory cells corresponds to a reset memory cell configured of a MOSFET, A reset MOSFET coupled to the cross-coupled MOSFET inverter circuit of the reset memory cell and a reset link coupled to each reset MOSFET, wherein the reset link resets each reset memory cell so that the reset memory cells are sequentially reset. MOSFE Has the ability to sequentially transmit a reset signal to be supplied to, in yet said respective reset memory cell, the reset MOSFET, the said cross-coupled each reset memory cell MOSFE
A source / drain region corresponding to a source / drain region of one of the MOSFETs of the T inverter circuit and the MOSFET switch circuit, and the cross-coupled MOSFE of each reset memory cell.
Insulated gate conductive layer on a part of each reset memory cell formed by the MOSFET between the source / drain region of one of the MOSFETs of the T inverter circuit and the MOSFET switch circuit and a reference potential node. And the insulated gate conductive layer is connected to the reset link. 2. The reset link is made of a resistive material,
Alternatively, the multi-cell memory according to claim 1, which is made of a polysilicon material. 3. The memory is a dual port CMO.
3. The multi-cell memory according to claim 1, wherein the multi-cell memory is a random access memory formed of memory cells composed of S. 4. The source / drain regions of the reset MOSFET correspond to the source / drain regions of one of the MOSFETs of the MOSFET switch circuit of the reset memory cell, and the insulated gate conductive layer comprises: 7. A portion of each reset memory cell between the source / drain region of one of the MOSFETs of the MOSFET switch circuit and the reference potential node on a portion of each reset memory cell. 4. The multi-cell memory according to any one of 1 to 3. 5. The memory is a random access memory formed by a matrix of rows and columns of MOSFET-configured memory cells, a reset memory cell is located at a selected column of the matrix, and the reset link is 2. The multi-cell memory of claim 1, further comprising: a reset MOSFET of the memory cell of the selected column of the matrix. 6. The matrix has M rows × N columns of memory cells to form an array of M, N-bit memory cells, with N memory cells in each row coupled to an N-bit output link. Each row of memory cells provides an N-bit output word in response to reading the contents of each row of memory cells, the memory comprising M memory cells each associated with each of the M rows of memory cells of the matrix. Of the reset memory cells and one of each M rows of the matrix coupled to the matrix memory cells and the reset memory cells.
N accessed from the one of each M rows of the matrix according to the state of the reset memory cell associated with the one
7. A multi-cell memory according to claim 6 including a mask circuit operative to controllably output an output word of bits. 7. An array of dual port memory cells comprised of MOSFETs, each of said MOSFET configured dual port memory cells having a first normal and complementary bit line port coupled to a first word line. A second set of MOSFET switch circuits controlled by a first select port that is coupled to the second normal and complementary bit line ports to which a second word line is coupled. Set of cross-coupled MOSFETs coupled by a second set of MOSFET switch circuits controlled by select ports of
Each of the MOSFET-configured dual-port memory cells selected corresponds to a dual-port reset memory cell, and a pair of cross-coupled MOSFET inverter circuits of the dual-port reset memory cell is provided. And a reset link coupled to each reset MOSFET, wherein the reset link sequentially supplies a reset signal to each reset MOSFET so that the dual-port reset memory cells are sequentially reset. Further, in each of the dual-port reset memory cells, the reset MOSFET comprises: the pair of cross-coupled MOSFET inverter circuits of the dual-port reset memory cells; First
And a second set of MOSFET switch circuit MOSFETs
Each source / drain region corresponding to one source / drain region of T, the pair of cross-coupled MOSFET inverter circuits of the dual-port reset memory cell, and the first
And a second set of MOSFET switch circuit MOSFETs
Each of the dual port reset MO between the source / drain region of one of T and a reference potential node.
7. An insulated gate conductive layer overlying a part of a memory cell formed by an SFET, the insulated gate conductive layer being connected to the reset link. Or the multi-cell memory according to item 1. 8. The source / drain regions of the reset MOSFET are in the source / drain regions of one of the MOSFETs of the first and second sets of MOSFET switch circuits of the dual port reset memory cells. Correspondingly, the insulated gate conductive layer is provided in the first and second MOSFETs of the reset memory cell of each dual port.
8. The multi-cell memory according to claim 7, wherein the multi-cell memory is on the reset memory cell of each dual port between the source / drain region of one of the MOSFETs of the switch circuit and the reference potential node. 9. The memory is a random access memory formed by a matrix of rows and columns of MOSFET-configured dual-port memory cells, wherein the dual-port reset memory cells are located in selected columns of the matrix. The reset link is a reset MOSF of the dual port memory cell of the selected column of the matrix.
9. The ET is bound to ET.
The described multi-cell memory. 10. The matrix has M rows × N columns of dual-port memory cells to form an array of M, N-bit dual-port memory cells, each row having N dual-port memory cells. A memory cell is coupled to the N-bit output link such that each row of dual-port memory cells provides an N-bit output word in response to reading the contents of each row of dual-port memory cells, the memory respectively M dual port reset memory cells associated with each of the M rows of dual port memory cells of the matrix, coupled to the matrix dual port memory cells and the dual port reset memory cells, the matrix Of dual port reset memory cells associated with one of each M rows of 10. The multi-cell memory of claim 9, further comprising a mask circuit operative to controllably output an N-bit output word accessed from the one of each M rows of the matrix according to a state.