JPH07240477A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To stabilize the operation of a point symmetrical memory cell while reducing the size and the unnecessary current flowing through a ground line. CONSTITUTION:A pair of transfer MOS transistors Qt1, Qt2 are arranged point symmetrically while being spaced apart by 180 deg.. The gates of driving MOS transistors Qd1, Qd2 and the transfer MOS transistors Qd1, Qd2 are formed of a first layer polysilicon while a word line WL is formed of a second layer polysilicon and connected through a contact hole 8 with the gates 7A, 7B of the transfer MOS transistor. The word line WL is extended in one direction of the memory cell between the gates 6A, 6B of the driving MOS transistor while bit lines BL, *BL and a ground line Vss are formed of an Al layer and extended in the other direction of the memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a symmetrical type memory cell structure of a static RAM.

[0002]

2. Description of the Related Art A conventional semiconductor memory device is a generally known high resistance load type memory cell shown in FIGS. FIG. 14 shows an equivalent circuit of the memory cell.
This is a flip-flop circuit in which two inverter circuits are connected to each other for feedback, and a pair of cross-connected drive MOS transistors Qd ₁ and Qd ₂ , a pair of transfer MOS transistors Qt ₁ and Qt ₂ and a load resistor are connected. and R _1, R _2, from a storage node diffusion layer n ⁺ _1, n ⁺ _2, and one word line WL, and a pair of bit lines BL, * and BL 1
Bit memory cells are configured. This memory cell is manufactured by a three-layer poly / one-layer Al process and has driving MOS transistors Qd ₁ and Qd.
d ₂ , gate and transfer MOS transistors Qt ₁ , Qt
The word line WL which forms the gate of t ₂ is formed of the first-layer polysilicon, the ground line Vss is formed of the second-layer polysilicon layer, and the power supply line Vcc and the load resistors R ₁ and R ₂ are formed of the third-layer polysilicon. It is made of silicon, and the pair of bit lines is BL, * B
L is formed of an Al layer. The area surrounded by the alternate long and short dash line in FIG. 11 shows a memory cell area for 1 bit.

As can be seen from the figure, since the layout of this memory cell is asymmetric, there is a drawback that the margin for process variations such as mask shift is small.
On the other hand, as a 16 Mbit static RAM has been developed in recent years, the capacity and integration of semiconductor memory devices are steadily increasing. However, when the design rule changes from sub-micron to sub-half-micron, it is not possible to manufacture a semiconductor integrated circuit in a stable manner simply by suppressing the process variation. It tends to be adopted.

An example of this type of memory cell is shown in FIGS.
Shown in 17. Its equivalent circuit is similar to that shown in FIG.
is there. In this memory cell, the transfer MOS transistor
Qt ₁, Qt₂Separate the cells above and below the cell and
Different word lines WL₁, WL₂Made up of that word
Line WL₁, WL₂A pair of drive MOs that are cross-connected between
S transistor Qd₁, Qd₂By placing
A semiconductor with a 180 ° point symmetric layout when viewed from the center of the
A storage device is realized. This memory cell also has 3
Adopting the one-layer poly / one-layer Al process,
It is made of the same material as the moricell.

FIG. 18 shows an equivalent circuit diagram of a memory cell array in which conventional memory cells are arranged in a matrix. The operation of the conventional semiconductor memory device will be described with reference to FIGS. First, the write operation address decoder circuit (not shown) by, for example, word - When the selected word line WL ₂ is H level, the bit line BL _2, * BL data on ₂ a transfer MOS transistor Qt _1, Qt ₂ Through,
A pair of drive MOs cross-connected with the load resistors R ₁ and R ₂
It is stored and held by a flip-flop circuit composed of S transistors Qd ₁ and Qd ₂ . On the other hand, in the read operation, the voltage difference between the drains of the driving MOS transistors Qd ₁ and Qd ₂ is read onto the bit lines BL ₂ and * BL ₂ via the transfer MOS transistors Qt ₁ and Qt ₂ .

The above-mentioned technique is disclosed, for example, in Japanese Patent Laid-Open No. 4-1.
No. 27470.

[0007]

However, in the above-mentioned 180 ° point symmetry type memory cell, since two word lines WL ₁ and WL ₂ are provided in the memory cell for 1 bit, the memory for 1 bit is formed. There is a problem that the occupied area of the cell becomes larger than that of the conventional asymmetric memory cell. For example, when the 0.8 micron design rule is adopted, the occupied area of the asymmetrical memory cell is 42.6.
The area occupied by the 180 ° point symmetry type memory cell was 51 μm ² / bit, while the area was 51 μm ² / bit.
Furthermore, since the memory write and read operations are performed by the _two word lines WL ₁ and WL ₂ , there is a drawback that the configuration of peripheral circuits such as address circuits becomes complicated. Furthermore, in the conventional memory cell, since the extending directions of the word line and the ground line are the same, as shown in FIG. 18, for example, by selecting one word line WL, the transfer MOS transistor is simultaneously formed. Is turned on, the common ground line Vss
Is connected to the ground wire Vss, unnecessary large current flows,
It adversely affected the operation of the memory.

The present invention has been made in view of the above problems, and realizes a memory cell of 180 ° point symmetry type with a single word line per bit, and improves the margin for process variations and at the same time It is possible to reduce the size of the memory cell and to stabilize the operation of the memory cell.

[0009]

In order to solve the above problems, the present invention provides a pair of cross-connected driving MOSs.
A transistor and a pair of transfer MOS transistors,
A memory cell including a pair of load resistors, a word line that forms the gate of the transfer MOS transistor, and a pair of bit lines, and is 180 ° when viewed from the center of the memory cell.
In a semiconductor memory device arranged in point symmetry, the pair of transfer MOS transistors are spaced apart by 180 ° in point symmetry, and the gates of the driving MOS transistor and the transfer MOS transistor are made of first-layer polysilicon. And forming the word line from the second layer polysilicon, connecting the gate of the transfer MOS transistor and the word line by a contact, and connecting the word line between the gates of the pair of drive MOS transistors. The memory cell was extended in one direction so that the pair of bit lines and the ground line were formed of an Al layer and extended in the other direction of the memory cell.

In the memory cell array in which the memory cells are arranged in rows and columns, the ground lines of the memory cells commonly connected to each word line are separated.

[0011]

According to the above means, as shown in FIG. 9, a 180 ° point symmetry type memory cell can be realized with a single word line WL for each bit, so that the margin for process variation can be improved. It is possible to reduce the size of the memory cell. Furthermore, since the Al layer is used as the material of the ground wire, the resistance can be made lower than that of polysilicon.
There is an advantage that writing and reading operations of the memory cell are stabilized.

Furthermore, as shown in FIGS. 9 and 10, by extending the word line and the pair of bit lines and the ground line in different directions, each word line is commonly connected to one word line. The ground line of the memory cell is separated for each memory cell. As a result, the current flowing through the ground line connected to the accessed memory cell is significantly reduced, and the write and read operations of the memory cell can be stabilized.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. First, FIG. 9 shows a layout diagram of the semiconductor memory device of the present invention. In the figure, the transfer transistors Qt ₁ and Qt ₂ are separated by 1 above and below the memory cell.
The arrangement of 80 ° point symmetry is common to the arrangement of the conventional 180 ° point symmetry type memory cell, but the one of the present invention is
The gates 7A, 7 of the transfer transistors Qt ₁ , Qt ₂
B is formed of a first layer polysilicon, the word line WL is formed of a second layer polysilicon, the gates 7A and 7B thereof are connected to the word line WL by a contact 8, and the word line WL is formed of The difference is that the memory cells are extended in the vertical direction so as to pass between the gates 6A and 6B of a pair of drive MOS transistors. Also, the word line W
Since L is formed of the second-layer polysilicon, the pair of bit lines BL, * BL and the ground line Vss are formed of an Al layer and alternately extend in the left-right direction of the memory cell in the figure. There is. Load resistance R ₁ , R ₂ and power supply line
Vcc is formed of the third layer polysilicon as in the conventional case.
This memory cell has a point symmetry type of 180 ° when viewed from the center C of the cell (intersection of diagonal lines of parallelogram). The equivalent circuit of the above memory cell is similar to that shown in FIG.

As described above, according to the present invention, since only one word line WL is required to pass through the memory cell for 1 bit, the occupied area of the cell is smaller than that of the conventional 180 ° point symmetry type memory cell. Can be significantly reduced. For example, when employing a 0.8 micron design rule, the area occupied by the conventional point generic type of memory cell, whereas a 51 [mu] m ² / bit, the memory cell according to the present invention, 40.0 ² / A bit, and greatly reduced. This is about 6% smaller than the conventional asymmetric memory cell. further,
Since writing and reading operations of the memory can be performed with a single word line WL, there is also an advantage that the configuration of peripheral circuits such as an address circuit is simplified.

Further, since the Al layer is used as the material of the ground line Vss, the resistance can be made lower than that of polysilicon, and there is an advantage that the writing and reading operations of the memory cell are stabilized. FIG. 10 shows an equivalent circuit diagram of a memory cell array in which memory cells according to the present invention are arranged in a matrix. As can be seen from the figure, unlike the conventional memory cell array shown in FIG. 18, the memory cells MC to which the word lines WL _{1 to} WL ₃ are commonly connected are connected to different ground lines Vss.

Next, the operation of the semiconductor memory device according to the present invention will be described with reference to FIGS. First, the write operation address decoder circuit (not shown) by, for example, word - When the selected word line WL ₂ is H level, the bit line BL _2, * BL data on ₂ a transfer MOS transistor Qt _1, Qt ₂ Through a pair of drive MOS transistors Qd ₁ and Qd cross-connected to the load resistors R ₁ and R ₂
It is stored and held by the flip-flop circuit composed of d ₂ . At this time, the transfer MOS transistors Qt ₁ and Qt ₂
The current I flows through the ground line Vss through the word line WL
Since the ground line Vss of the other memory cells MC commonly connected to is separated, the current flowing through the ground line Vss of the accessed memory cell MC can be reduced as compared with the conventional case. On the other hand, in the read operation, the driving MOS transistor Qd ₁ ,
The voltage difference between the drains of Qd ₂ is read out onto the bit lines BL ₂ , * BL ₂ via the transfer MOS transistors Qt ₁ , Qt ₂ . Also at this time, similarly, the unnecessary current flowing through the ground line Vss can be reduced and the operation of the memory cell can be stabilized.

Next, a method of manufacturing the semiconductor memory device of the present invention will be described with reference to FIGS. First, a field oxide film region 2 and an activation region 3 are formed on the semiconductor substrate 1 by a selective oxidation method, and a gate oxide film is formed on the activation region 3 by thermal oxidation (FIG. 1). Then, a buried contact window 4 is formed in a part of the activation region 3 (FIG. 2). Then, as shown in FIG. 3, the gates 6A and 6B of the driving MOS transistors Qd ₁ and Qd ₂ and the gates 7A and 7B of the transfer MOS transistors Qt ₁ and Qt ₂ are formed by the first layer polysilicon, and these are formed. An n ⁺ diffusion layer to be a source / drain is formed by ion implantation as a mask. The gates 6A, 6 of the driving MOS transistor are
B and the n ⁺ diffusion layer for the storage node are connected through the buried contact window 4. Next, after forming the first interlayer insulating film on the entire surface, the gates 7 of the transfer MOS transistors Qt ₁ and Qt ₂ extended on the field oxide film region 2 are formed.
Contact hole 8 on A and 7B, and drive MOS
A contact hole 9 is simultaneously formed on the n ⁺ diffusion layer serving as the source of the transistors Qd ₁ and Qd ₂ (FIG. 4). Then, the word line WL and the polysilicon electrode 10 are formed by the second layer polysilicon. The word line WL is connected to the gates 7A and 7B of the transfer MOS transistors Qt ₁ and Qt ₂ through the contact hole 8 and extends in the vertical direction of the memory cell so as to pass between the gates 6A and 6B. Is present (Fig. 5). Next, after forming the second interlayer insulating film on the entire surface, as shown in FIG. 6, contact holes 11A and 11B are formed on the gates 6A and 6B of the driving MOS transistors Qd ₁ and Qd ₂ , respectively. 3rd as shown
Power supply line Vcc and load resistances R ₁ and R ₂ due to the polysilicon layer
To form. The load resistances R ₁ and R ₂ are formed in the high resistance portion drawn from the power supply line Vcc, and the contact hole 11
The gates 6A and 6B are connected via A and 11B. Then, after forming a third interlayer insulating film on the entire surface, transfer M
A contact hole 13 is formed on the drain diffusion layers of the OS transistors Qt ₁ and Qt ₂ and a contact hole 14 is formed on the polysilicon electrode 10 at the same time (FIG. 8). Then, as shown in FIG. 9, the bit lines BL, * BL and the ground line Vss are simultaneously formed by the Al layer. As described above, the semiconductor memory device of the present invention is completed.

[0018]

As described above, according to the semiconductor memory device of the present invention, a single word line is used for 18 bits per bit.
Since the 0 ° point symmetry type memory cell is realized, it is possible to reduce the size of the memory cell while improving the margin for process variations. For example, when employing a 0.8 micron design rule, the area occupied by the conventional point generic type of memory cell, whereas a 51 [mu] m ² / bit, the memory cell according to the present invention, 40.0 ² / A bit, and greatly reduced. This is about 6% smaller than the conventional symmetrical memory cell. in addition,
Since writing and reading operations of the memory can be performed with a single word line WL, there is an advantage that the configuration of peripheral circuits such as an address circuit is simplified.

Further, since the Al layer is used as the material of the ground line Vss, the resistance can be made lower than that of polysilicon, which has the advantage of stabilizing the writing and reading operations of the memory cell. Furthermore, by extending the word line and the pair of bit lines and the ground line in different directions, the ground line of each memory cell commonly connected to one word line is separated for each memory cell. There is. As a result, the current flowing through the ground line connected to the accessed memory cell is significantly reduced, and the write and read operations of the memory cell can be stabilized.

[Brief description of drawings]

FIG. 1 is a first semiconductor memory device according to an embodiment of the present invention.
FIG.

FIG. 2 is a second semiconductor memory device according to an embodiment of the present invention.
FIG.

FIG. 3 is a third semiconductor memory device according to an embodiment of the present invention.
FIG.

FIG. 4 is a fourth semiconductor memory device according to an embodiment of the present invention.
FIG.

FIG. 5 is a fifth semiconductor memory device according to an embodiment of the present invention.
FIG.

FIG. 6 is a sixth semiconductor memory device according to an embodiment of the present invention.
FIG.

FIG. 7 is a seventh semiconductor memory device according to an embodiment of the present invention.
FIG.

FIG. 8 is an eighth semiconductor memory device according to an embodiment of the present invention.
FIG.

FIG. 9 is a ninth semiconductor memory device according to an embodiment of the present invention.
FIG.

FIG. 10 is an equivalent circuit diagram of a memory cell array according to an embodiment of the present invention.

FIG. 11 is a first plan view of a conventional asymmetric memory cell.

FIG. 12 is a second plan view of a conventional asymmetric memory cell.

FIG. 13 is a third plan view of a conventional asymmetric memory cell.

FIG. 14 is an equivalent circuit diagram of a high resistance load type memory cell.

FIG. 15 is a first plan view of a conventional 180 ° point-symmetrical memory cell.

FIG. 16 is a second plan view of a conventional 180 ° point-symmetrical memory cell.

FIG. 17 is a third plan view of a conventional 180 ° point-symmetrical memory cell.

FIG. 18 is an equivalent circuit diagram of a conventional memory cell array.

Claims (2)

[Claims] 1. A pair of cross-connected driving MOS transistors, a pair of transfer MOS transistors, a pair of load resistors, a word line forming the gate of the transfer MOS transistor, and a pair of bit lines. And a pair of transfer MOS transistors spaced apart from each other by 180 ° point symmetry with respect to each other. MOS transistor and transfer M
The gate of the OS transistor is formed of first layer polysilicon, the word line is formed of second layer polysilicon, the gate of the transfer MOS transistor and the word line are connected by a contact, and the word line is formed. A memory cell is extended in one direction so as to pass between the gates of the pair of driving MOS transistors, and the pair of bit lines and ground lines are formed of an Al layer and extended in the other direction. A characteristic semiconductor memory device. 2. The semiconductor device according to claim 1, wherein in a memory cell array in which the memory cells are arranged in a matrix, the ground lines of the memory cells commonly connected to each word line are separated from each other. Storage device.