JPS6232638A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To decrease power consumption, by a constitution; wherein a voltage is simultaneously applied to a second polycrystalline silicon layer, which is formed on a polycrystalline silicon layer that is connected between word lines and a power source, and a well beneath a first polycrystalline silicon layer; and the resistance of the first polycrystalline silicon layer is increased by the application of the voltage. CONSTITUTION:When information is written in a memory cell M, a low level voltage is applied to an N-type well 2 and a second polycrystalline silicon layer 7. Therefore a first polycrystalline silicon layer 5 is kept at a relatively low resistance value. A specified voltage Vpp is applied to a selected word line WL, and the writing is executed as in a conventional device. At the time of reading, a specified voltage is applied to the N-type well 2 and the second polycrystalline silicon layer 7 through contact parts 2a and 7a. A depletion layer is expanded between the surface facing the lower N-type well 2 and the surface facing the upper second polycrystalline silicon layer 7 in the first polycrystalline silicon layer 5, and a very high resistance value is obtained. Therefore,the resistance value of an element Q1a in the word line WL, which is not selected, becomes large, and the power consumption can be decreased.

Description

[Detailed Description of the Invention] C Industrial Application Field] The present invention relates to a semiconductor memory device, and in particular to an EPROM (
Erasable Programmable R
The present invention relates to a semiconductor memory device that achieves low power consumption in (ead 0nly Mes+ory).

[Conventional technology]

Generally, in a semiconductor memory device such as an EPROM, different voltages are applied to the word line when writing information to a memory cell and when writing information. A lower voltage VCC is applied to the word line when successive outputs occur. FIG. 5 shows an example of a circuit for applying these voltages, and one end of the word line WL of the memory cell M is connected to a depression MO3FET.
(MO3 type field effect transistor) ■ via Ql,
A depletion MOS FET called a transfer is connected to the power supply VS of p and Vcc, and the other end is connected to a depletion MOS FET called a transfer.
Qz, and is connected to an X decoder XDEC via an inverter INV consisting of a P-type MOSFET Qs and an N-type MO3FETQ. It goes without saying that a plurality of such word lines (for example, eight) are provided in parallel, and that ycc is applied to the inverter INV.

Then, during writing, the X decoder XDEC selects one of the words vAWL and sets the inverter INV to the low
Input OW level, MOS FETQ is on, Q
4 is turned off, and MO3FETQ is also turned off. On the other hand, since the power supplies vS to vp are applied to this word line WL, the potential of the word line WL is 2. Then, writing to the memory cell M is executed. At this time, in the other word lines, MO8FETQt and Q4 are respectively turned on in the inverter INV, so the potential of the power supply VS flows to the ground, and no rise in potential occurs.

On the other hand, when it appears one after another, all MO3FETQ! is turned on, and Lo- is input to the inverter INV of the word line WL selected by the X decoder XDEC, so the MOS FET Qs is turned on and Q4 is turned off. Therefore, the potential ■cc from the power supply vS and the inverter INV is applied to the word line WL, and reading is executed by detecting this potential. At this time, in the other word line Wl, the MOS F E of the inverter INV
Since TQ4 is on, the ycc applied to each word line from the power supply S is MOS FETQ
It flows through z and Q4 to ground, and no reading is performed.

By the way, in the circuit configuration described above, in the word line that is not selected at the time of succession, Vcc from the power supply vS is MOSF
ETQ! Since the current flows through Q4 and ground, this causes extra power consumption. Therefore, in order to prevent this, the configurations shown in FIGS. 6(a) and 6(b) have been proposed.

That is, the MO3FE T connected to the power supply VS mentioned above
Let Q+ have the configuration shown in FIG. This configuration is
For example, an N-type well 42 is formed on a P-type silicon substrate 41, and a P-type polycrystalline silicon layer 44 is formed on this N-type well 42 with an insulating film 43 interposed therebetween. One end of this P-type polycrystalline silicon layer 44 is connected to the power supply VS, the other end is connected to the word line WL, and a contact 45 is connected to the N-type well 42.
The structure is such that a predetermined voltage can be applied by.

In reality, as shown in FIG.
An N-type well 42 is extended across the N-type well 42, and a polycrystalline silicon layer 44 for each word line is provided so as to intersect with the N-type well 42.

According to this configuration, when a predetermined voltage is applied to the N-type well 42 via the contact 45, especially when forming one after another, the portion of each polycrystalline silicon layer 44 facing the N-type well 42 via the insulating film 43 The depletion layer expands, and as a result, the electrical resistance of the polycrystalline silicon layer 44 increases, making it difficult for current to flow.

For this reason, the current flowing from the power supply VS to the ground in the unselected word line at the time of succession is reduced, and power consumption at this time can be reduced.

[Problem that the invention seeks to solve]

In the above-mentioned configuration, for example, the impurity concentration of the P-type polycrystalline silicon layer 44 is set to about IQ "cm-", and the N-type well 42
The voltage between the
In the case of approximately .about.8.times., it is considered that the depletion layer in the polycrystalline silicon layer 44 does not extend by about 1000 layers from the substrate side. For this reason, when polycrystalline silicon having a normal film thickness of 2000 Å or more is used as is, it is difficult to sufficiently reduce the current flowing in this polycrystalline silicon layer.

For this reason, when the number of word lines increases with the increase in the integration of memory cells, the power consumption of the entire cell array becomes extremely large, making it difficult to completely eliminate the above-mentioned problem.

In order to prevent this, it is possible to reduce the impurity -a degree in the portion of the polycrystalline silicon layer 44 facing the N-type well 42 or to reduce the thickness of the polycrystalline silicon layer, but the former The problem with this countermeasure is that the manufacturing process becomes complicated and is not compatible with conventional EPROM production systems.
In the latter case, the resistance of the polycrystalline silicon layer 44 in the conductive state becomes large, and there is a problem that a predetermined voltage cannot be applied to the word line during writing or reading.

[Means for solving problems]

In the semiconductor memory device of the present invention, in order to reduce power consumption by reducing the current in the word line during non-selection without causing the various problems described above, the semiconductor memory device connects a multi-layer power supply between the word line and the power supply. A second polycrystalline silicon layer is formed on the crystalline silicon layer, and this second polycrystalline silicon layer and the first
The structure is configured such that a voltage can be simultaneously applied to the well below the polycrystalline silicon layer 1, and by applying this voltage, a depletion layer expands in the vertical direction or laterally in the polycrystalline silicon layer 1, and the polycrystalline silicon layer 1 is The structure is such that the resistance of the crystalline silicon layer is significantly increased.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

1 to 3 show an embodiment in which the present invention is applied to an EPROM, and in FIG. 1, ■S is V, and ■
. MA is a memory cell array having memory cells M, XDEC is an X decoder, and one end of the word line WL of each memory cell M is connected to an element Q1. via the power supply VS
and the other end is connected to element Q2 and MO3FETQ3 and Q
It is connected to the X decoder XDEC via an inverter INV consisting of 4 and 4. The element Q1m provided on the power supply VS side is composed of a well and first and second polycrystalline silicon layers, as shown in FIGS. 2 and 3, respectively, showing cross-sectional structures in different directions. There is.

That is, a strip-shaped N-type well 2 is formed extending between the power source S and each memory cell array MA on a P-type silicon substrate 1, and an element isolation region 3 made of a thick silicon dioxide film is formed thereon. At the same time, a thin silicon dioxide film 4 is formed in a portion defined by the element isolation region 3.

Then, one polycrystalline silicon layer 5 is formed in a predetermined pattern on this silicon dioxide film 4 so as to intersect with the N-type well 2 and corresponding to the word line WL of each memory cell array MA. A P-type impurity is introduced into the layer to form a P-type child crystalline silicon layer. An insulating film 6 made of silicon dioxide is formed on approximately the center of this one polycrystalline silicon layer 5, and a band-shaped insulating film 6 is further formed on this insulating film 6 so as to cross each of the above-mentioned one polycrystalline silicon layer 5. A second polycrystalline silicon layer 7 is formed. After forming an insulating film 8 on this second polycrystalline silicon layer 7 and an interlayer insulating film 9 on the first and second polycrystalline silicon layers 57, Contacts 5a and 5b having metal electrodes i5A and 5B are formed at both ends of the silicon layer 5, and each word line WL, that is, the contact 5a is connected to the power supply vS, and the contact 5b is connected to the memory cell M. or,
In a part of the N-type well 2, a well contact portion 2a into which impurities are introduced at a high concentration is formed, and a metal electrode 2A is formed. Furthermore, a contact portion 7a is also formed in a portion of the second polycrystalline silicon layer 7. These contact portions 2 of the N-type well 2 and the second polycrystalline silicon layer 7
a,? A is connected to a voltage source to which a high level voltage is applied during reading.

According to this configuration, when writing information to the memory cell M, since Lo- level is applied to the N-type well 2 and the second polycrystalline silicon layer 7, the first polycrystalline silicon layer 5 is A predetermined voltage V□ is applied to the selected word line WL, and writing is executed in the same way as in the conventional method.

On the other hand, in the case of continuous formation, a predetermined voltage is applied to the N-type well 2 and the second polycrystalline silicon N7 through the contact parts 2a and 7a, respectively, so that in the polycrystalline silicon 715 of 1, the lower N-type well 2 The depletion layer expands on the surface facing the second polycrystalline silicon layer 7 and on the surface facing the upper second polycrystalline silicon layer 7, which significantly reduces the conductive area of the first polycrystalline silicon layer 5 as a whole and makes its resistance extremely high. . In this case, if the second polycrystalline silicon layer 7 is arranged to face the side surface of the first polycrystalline silicon layer 5 as shown in FIG. As the layer expands, the resistance becomes even larger.

Therefore, in the case of successive word lines, the resistance value of the element Q0 in the unselected word line WL becomes large, and it is possible to suppress the extra current flowing to the ground, thereby achieving a reduction in power consumption. In addition, being able to increase the resistance of the polycrystalline silicon layer 5 in this way means that it becomes possible to increase the film thickness of the polycrystalline silicon layer 5 in writing. It is also possible to improve the characteristics by suppressing the voltage drop during continuous application.

Note that the element Q1. The manufacturing method will be explained using FIGS. 4(a) to 4(g) in correspondence with the manufacturing process of the memory cell M.

First, as shown in the figure (a), after forming an N-type well 2 on a P-type silicon substrate 1, a silicon nitride film 10 is formed in the element formation region, and an oxidation process is performed using this as a mask to form a thick dioxide film. An element isolation region 3 made of a silicon film is formed. Then, as shown in FIG.
0 is removed and a thin silicon dioxide film 4 is formed in its place. Next, a polycrystalline silicon film 11 is formed on this silicon dioxide film 4 by a vapor phase growth method or the like, and a P-type impurity such as poron is introduced into this film.

Next, as shown in FIG. 2C, the polycrystalline silicon layer 11 is patterned, leaving a region that will become the floating gate 20 of the memory cell M and a region that will become the polycrystalline silicon layer 5 of 1, and is then heated. A silicon dioxide film 21.6 is formed by an oxidation method.

Next, as shown in FIG. 4(d), a polycrystalline silicon layer is grown thereon again and a silicon dioxide film is formed on the surface, and then buttering is performed using the photoresist 12 as a mask to form the floating gate 20. Patterns are formed to form a control gate 22, a second polycrystalline silicon layer 7, and insulating films 23 and 8 on the upper and l polycrystalline silicon layers 5, respectively. Thereafter, a light etching process is performed to remove the exposed portions of the silicon dioxide film 6 on the first polycrystalline silicon layer 5 and the silicon dioxide film 21 on the floating gate 20.

Then, as shown in FIG. 3(e), the portion corresponding to the element Q1□ is covered with a photoresist 13, etc., and the polycrystalline silicon is etched to change the floating gate 20 to the control gate 2.
2. Mold into approximately the same shape as 2.

Then, as shown in FIG. 2(f), an N-type impurity such as arsenic is introduced to form the contact portion 2a of the N-type well 2.
At the same time, source/drain regions 24 and 25 of the memory cell are formed. Then, after forming an interlayer insulating film 9 and forming contact holes, metal electrodes 26.27 and 28.2A are formed.
, 5A, and 5B, the element Q1m and the memory cell M can be completed as shown in FIG.

According to this manufacturing method, by simply using the conventional EPROM manufacturing method, element Q3. can be formed simultaneously.

〔Effect of the invention〕

As explained above, the present invention forms a second polycrystalline silicon layer on a polycrystalline silicon layer connected between a word line and a power supply, and connects this second polycrystalline silicon layer with the first polycrystalline silicon layer. The configuration is such that a voltage can be simultaneously applied to the well below the polycrystalline silicon layer, and by applying this voltage, a depletion layer expands in the vertical direction or sideways in the polycrystalline silicon layer 1, and the polycrystalline silicon layer 1 is expanded. Since it is configured to significantly increase the resistance of the silicon layer, it reduces the current flowing to the ground in unselected word lines in EPROMs, especially during successive readouts, thereby reducing power consumption even in highly integrated EFROMs. reduction can be achieved. Furthermore, it becomes possible to increase the thickness of the first polycrystalline silicon layer, and it is also possible to reduce the resistance of the polycrystalline silicon layer in a conductive state and improve write and read characteristics.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view showing the circuit configuration and the planar configuration of an element according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line AA in FIG. 1, and FIG. A cross-sectional view along the BB line,
Figures 4 (a) to (g) are cross-sectional views showing the manufacturing method in the order of steps, Figure 5 is a conventional circuit configuration diagram, and Figures 6 (a) and (b) are cross-sectional views and schematic diagrams of the conventional configuration, respectively. FIG. 1... P type silicon substrate, 2... N type well, 3...
...Element isolation region, 4...Silicon dioxide film, 5...
- 1 polycrystalline silicon layer, 6... insulating film, 7... second polycrystalline silicon layer, 8... insulating film, 9... interlayer insulating film, 10... silicon nitride film, 11... Polycrystalline silicon layer, 12.13... Photoresist, 20.
...Floating gate, 22...Control gate, 41...P
type silicon substrate, 42...N type well, 43...insulating film, 44...polycrystalline silicon layer, 45...contact, M...memory cell, MA...memory cell array, XDEC ...X decoder, VS...power supply, WL
...Word line, Ql, Qz, Qs, Q4
...Element (MOSFET), Q, ...Element. Figure 1 Figure 2 Figure 3 Figure 4 (a) 1° Figure 4 Figure 5

Claims (1)

[Claims] 1. A semiconductor formed by forming one polycrystalline silicon layer on a well provided in a semiconductor substrate, and connecting this one polycrystalline silicon layer between a word line of a memory array and a power supply. In the storage device, a second polycrystalline silicon layer is formed on the first polycrystalline silicon layer, and a voltage can be applied to the second polycrystalline silicon layer and the well at the same time,
A semiconductor memory device characterized in that a depletion layer is expanded in one polycrystalline silicon layer from above and below or from the sides by applying this voltage. 2. An insulating film is interposed between the well and the polycrystalline silicon layer 1 and between the polycrystalline silicon layer 1 and the second polycrystalline silicon layer, respectively. semiconductor storage device.