JPH08340243A - Bias circuit - Google Patents

Bias circuit

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Publication number
JPH08340243A
JPH08340243A JP7147133A JP14713395A JPH08340243A JP H08340243 A JPH08340243 A JP H08340243A JP 7147133 A JP7147133 A JP 7147133A JP 14713395 A JP14713395 A JP 14713395A JP H08340243 A JPH08340243 A JP H08340243A
Authority
JP
Japan
Prior art keywords
current
circuit
current mirror
supplied
mirror
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7147133A
Other languages
Japanese (ja)
Inventor
Nobuyuki Hirayama
Yasushi Matsuno
Katsuto Sakurai
Yoshihiro Shirai
信之 平山
靖司 松野
克仁 桜井
誉浩 白井
Original Assignee
Canon Inc
キヤノン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc, キヤノン株式会社 filed Critical Canon Inc
Priority to JP7147133A priority Critical patent/JPH08340243A/en
Publication of JPH08340243A publication Critical patent/JPH08340243A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To improve relative accuracy without being affected by wiring resistance or the like between plural circuit blocks by supplying an output of a current mirror circuit in a certain circuit block to other circuit blocks including current mirror circuits.
CONSTITUTION: A base current is supplied from a bipolar transistor(TR) 17 to bipolar TRs 8 to 10 in a circuit block 1 to constitute a current mirror. A current supplied from a current source 7 and mirrored by the block 1 is mirrored by other circuit blocks 2 to 4 and used for circuits in respective circuit blocks. For instance, a current supplied from the collector of the TR 8 to the circuit block 2 is converted into the bias voltage of the current mirror by a TR 11 and the bias voltage is supplied to the bases of other bipolar TRs 13 to 15 constituting a current mirror. The base current of the bipolar TRs constituting the current mirror is supplied from a MOS TR 12.
COPYRIGHT: (C)1996,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明はバイアス回路に係わり、 The present invention relates to relates to a bias circuit,
特にIC内の複数の回路ブロックにおいて相対精度の良いカレントミラーを実現するバイアス回路に関するものである。 In particular it relates to a bias circuit for realizing a good current mirror with relative accuracy in a plurality of circuit blocks the IC.

【0002】 [0002]

【従来の技術】従来、複数の回路ブロックにおいて同一の電流値のバイアスを供給するバイアス回路としては図2に示す構成がとられている。 Conventionally, the configuration shown in FIG. 2 is taken as a bias circuit for supplying a bias of the same current value in a plurality of circuit blocks. すなわち、図2に示すように、回路ブロック1の内に形成したバイアス回路のバイアス電圧を、他の回路ブロック2,3,4…に供給し、回路ブロック1と同様な構成のカレントミラーにより、各回路ブロック内でバイアス電流を発生させている。 That is, as shown in FIG. 2, the bias voltage of the bias circuit formed within the circuit block 1 is supplied to other circuit blocks 2, 3, 4, by a current mirror similar to the circuit block 1 configuration, It is generating a bias current in each circuit block.

【0003】 [0003]

【発明が解決しようとする課題】しかしながら、上記従来のバイアス回路ではバイアス電圧を供給する配線16 [SUMMARY OF THE INVENTION However, wiring for supplying the bias voltage in the conventional bias circuit 16
や電源配線6の配線抵抗と、配線を流れる電流とにより電圧降下が生じるため、IC上の各回路ブロックの配置や回路ブロック間の配線抵抗というレイアウト的要素で各回路ブロックのバイアス電流の相対精度が悪化するという問題があった。 And wiring resistance of and power wiring 6, a voltage drop by the current flowing through the wire occurs, the relative accuracy of the bias current of each circuit block layout elements that wiring resistance between the arrangement and the circuit block of the circuit blocks on the IC but there is a problem that worse.

【0004】本発明の目的は、回路ブロック間の配線抵抗と、回路ブロック内でミラーする電流値に影響されない、相対精度の高いバイアス回路を実現することにある。 An object of the present invention is the wiring resistance between the circuit blocks, not affected by the current value mirror in the circuit block, to realize a high bias circuit of relative accuracy.

【0005】 [0005]

【課題を解決するための手段】本発明のバイアス回路は、第1のカレントミラー回路を有する一の回路ブロックと、該第1のカレントミラー回路の出力電流が供給される第2のカレントミラー回路をそれぞれ有する複数の他の回路ブロックとを備えたものである。 Bias circuit of the present invention SUMMARY OF] includes a first circuit block having a first current mirror circuit, the second current mirror circuit output current of the current mirror circuit of the first is supplied the is that a plurality of other circuit blocks each having.

【0006】 [0006]

【作用】本発明では一の回路ブロック内のカレントミラー回路の出力を他の回路ブロックに供給するため、回路ブロック間の配線抵抗の値に依存しない電流を供給出来る。 The output of the current mirror circuit in the first circuit block is [action] The present invention to be supplied to other circuit blocks, it can supply a current which does not depend on the value of the wiring resistance between the circuit blocks.

【0007】また、カレントミラー回路を他の複数の回路ブロック内のそれぞれに構成することにより、カレントミラーを構成する素子をバイアスするバイアスラインの配線抵抗の影響を極力小さくすることが可能となり、 Further, by constituting a current mirror circuit in each of the other plurality of circuit blocks, it is possible to minimize the influence of the wiring resistance of the bias line for biasing the elements constituting the current mirror,
相対精度の良いカレントミラーを実現出来る。 Relative accurate current mirror can be realized.

【0008】なお、本発明において、他の回路ブロックのカレントミラー回路にバイポーラトランジスタを使用すれば、絶縁ゲート型トランジスタを使用した場合に比べ、出力インピーダンスの高いカレントミラー回路を構成することができる。 [0008] In the present invention, the use of bipolar transistors in the current mirror circuit of the other circuit blocks, compared with the case of using the insulated gate transistor, it is possible to construct a high output impedance current mirror circuit. また、カレントミラーを構成するバイポーラトランジスタのベース電流を絶縁ゲート型トランジスタで供給すれば、各回路ブロックでのミラーする電流値に影響されない相対精度の高いバイアスを実現出来る。 Further, if supplied in a base current to the insulated gate transistor of a bipolar transistor constituting a current mirror, the mirror to the current value high bias of the relative accuracy that is not affected by in each circuit block can be realized.

【0009】 [0009]

【実施例】以下、本発明の実施例について図面を用いて詳細に説明する。 EXAMPLES The following examples of the present invention will be described in detail with reference to the accompanying drawings.

【0010】図1は本発明のバイアス回路の一実施例を示す回路構成図であり、1は他の回路ブロックに電流を供給するカレントミラー回路を内蔵する回路ブロック、 [0010] Figure 1 is a circuit diagram showing one embodiment of a bias circuit of the present invention, 1 is the circuit blocks provided in the current mirror circuit for supplying current to other circuit blocks,
2,3,4は回路ブロック1により電流が供給される他の回路ブロック、5は第1の電源ライン、6は第2の電源ライン、7はミラーする電流の元となる電流源、8, 2,3,4 Other circuit blocks current is supplied by the circuit block 1, the first power supply line 5, the second power supply line 6, 7 current sources as a source of current mirror, 8,
9,10は他の回路ブロック2,3,4へ電流を供給するカレントミラーを構成するバイポーラトランジスタ、 9 and 10 constitute a current mirror for supplying a current to other circuit blocks 2,3,4 bipolar transistor,
11は回路ブロックに供給された電流をミラーするためのバイアスを発生させるためのバイポーラトランジスタ、13,14,15は回路ブロック内の回路にミラーした電流を供給するためのバイポーラトランジスタ、1 11 bipolar transistor for generating a bias to mirror the current supplied to the circuit blocks, bipolar transistors for supplying a current that mirrors the circuit in the circuit block 13, 14, 15, 1
2はカレントミラーを構成するバイポーラトランジスタのベース電流を供給する絶縁ゲート型トランジスタたるMOSトランジスタである。 2 is an insulated gate type transistor serving MOS transistor supplies the base current of the bipolar transistors forming the current mirror.

【0011】電流源7より供給された電流は回路ブロック1内のカレントミラー回路により、他の回路ブロック2,3,4に供給される。 [0011] the current supplied from the current source 7 by the current mirror circuit in the circuit block 1 is supplied to the other circuit blocks 2, 3 and 4. ここでは、カレントミラーを構成するバイポーラトランジスタ8,9,10のベース電流をバイポーラトランジスタ17により供給しているがこのベース電流供給トランジスタにMOSトランジスタを使用しても良い。 Here, although the supply of the bipolar transistor 17 the base current of the bipolar transistor 8, 9 and 10 constituting a current mirror may be used MOS transistor to the base current supply transistor. その場合、回路ブロック1のカレントミラー回路の出力電流はベース電流を供給するトランジスタのベース電流の影響を受けなくなる。 In that case, the output current of the current mirror circuit of the circuit block 1 is no longer affected by the base current of the transistor for supplying a base current. また、電流源7は、ある電圧との間に抵抗を挿入しただけの簡単なものから、外部での調整を可能とする可変電流源など、複雑な形式のものまで使用可能であり、その構成を答わない。 The current source 7, from as simple simply by inserting a resistor between a certain voltage, such as a variable current source capable of adjusting the externally may be used to those of complex forms, the configuration no it answers the.

【0012】回路ブロック1でミラーされた電流は他の回路ブロック2,3,4…へ供給される。 [0012] current that is mirrored in the circuit block 1 is supplied to the other circuit blocks 2, 3, 4. 各回路ブロック2,3,4…へ供給された電流は、それぞれの回路ブロックでミラーされ、各回路ブロック内の回路に使用される。 Supplied current to each circuit block 2, 3, 4 are mirrored in each circuit block, it is used in circuits in each circuit block. 例えば、トランジスタ8のコレクタから回路ブロック2へ供給された電流はトランジスタ11によりカレントミラーのバイアス電圧へと変換され、カレントミラーを構成する他のバイポーラトランジスタ13,14, For example, current supplied to the circuit block 2 from the collector of the transistor 8 is converted into the bias voltage of the current mirror by transistors 11, other bipolar transistors 13 and 14 constituting a current mirror,
15…のベースに電圧供給される。 15 ... is the voltage supplied to the base of the. また、このカレントミラーを構成するバイポーラトランジスタのベース電流はMOSトランジスタ12により供給される。 The base current of the bipolar transistor constituting the current mirror is fed by the MOS transistor 12. 回路ブロック1及び2に示したカレントミラーを構成するトランジスタをバイポーラトランジスタで構成しているのはM M What constitutes a transistor constituting a current mirror shown in the circuit blocks 1 and 2 in a bipolar transistor
OSトランジスタを使用するのに比べ、出力インピーダンスを大きくすることが出来るここと、一般的に同一面積を占めるMOSトランジスタより相対精度を良くすることが出来るためである。 Compared to using an OS transistor, and wherein it is possible to increase the output impedance, because generally it is possible to improve the relative accuracy than MOS transistors occupying the same area. また、カレントミラーを構成するバイポーラトランジスタのエミッタと電源との間に抵抗を挿入しているのは、カレントミラーの出力インピーダンスをさらに高め、また相対精度をさらに良くするためであるが、抵抗を挿入するかどうか、また、抵抗の値をいくらにするかは、電流の精度やミラーを構成するバイポーラトランジスタのコレクタ電位の取りうる範囲や、電流のノイズスペックなどにより決定される。 Moreover, what was inserted a resistor between the emitter and the power supply of the bipolar transistors constituting the current mirror, further increases the output impedance of the current mirror, Although in order to further improve the relative accuracy, a resistor whether, Moreover, either the value of resistance to much, and a range that can be taken in the collector potential of the bipolar transistor constituting the accuracy and mirror current is determined by the noise or the like specification of current. カレントミラーを構成するトランジスタ11,13,14, Transistors 11, 13 and 14 to form a current mirror,
15…のベース電流はMOSトランジスタ12により供給される。 15 ... base current is supplied by the MOS transistor 12. このため、複数の回路ブロック2,3,4… Therefore, a plurality of circuit blocks 2, 3, 4
のそれぞれでカレントミラーされる電流値はそれぞれの回路ブロックのカレントミラー回路のミラーするトランジスタの数の影響を受けない。 The current value the current mirror is not subject to the influence of the number of transistors for mirroring the current mirror circuits of the respective circuit blocks, respectively. たとえば、回路ブロック2,3,4が、g mアンプを用いたフィルターであり、 For example, the circuit block 2, 3 and 4, a filter using the g m amplifier,
カレントミラーの出力電流が、g mアンプのg mを決定する電流源に使われている場合を考えてみる。 Output current of the current mirror, consider the case being used in the current source for determining the g m amplifier g m. この場合、各フィルターに求められる特性が異なれば、当然、 In this case, different characteristics required for each filter, of course,
カレントミラーでミラーされる電流値も異なる場合が多い。 Current that is mirrored by the current mirror often vary. この時カレントミラーを構成するバイポーラトランジスタのベース電流をバイポーラトランジスタで供給しようとすると、そのトランジスタのベース電流により、 When the base current of the bipolar transistors constituting this case the current mirror to be supplied by the bipolar transistor, the base current of the transistor,
ミラーされる電流に誤差が発生する。 Error is generated in the current mirror. したがって、電流源7の値を調整してフィルターのf cを調整しようとした時、回路ブロック2,3,4…の特性がまったく同調しては調整されなくなってしまう。 Therefore, when trying to adjust the f c of the filter by adjusting the value of the current source 7, the circuit block 2, 3, 4 characteristic of no longer being adjusted synchronously at all.

【0013】本発明によれば、カレントミラーを構成するバイポーラトランジスタのベース電流をMOSトランジスタにより供給しているため、各回路ブロック2, According to the present invention, because it is providing a MOS transistor the base current of the bipolar transistors constituting a current mirror, each circuit block 2,
3,4…でのカレントミラーのミラー数によらず、各回路ブロックのカレントミラーの電流値の相対精度を高くすることが可能となっている。 3,4 ... regardless of the number of mirror current mirror in, it is possible to increase the relative accuracy of the current value of the current mirror of each circuit block.

【0014】 [0014]

【発明の効果】以上説明したように、本発明によれば、 As described in the foregoing, according to the present invention,
複数の回路ブロックのカレントミラーの値の相対精度を高くすることが可能となる。 It is possible to increase the relative precision of the current mirror of the plurality of circuit blocks. これにより、たとえばg m Thus, for example, g m
アンプを用いたフィルターに使用した場合、各フィルターの特性の相対精度を高くすることが可能となり、フィルターのf cをg mアンプのバイアス電流により調整しようとした場合、各フィルターの特性を精度よく調整することが可能となる。 When used filter using the amplifier, it is possible to increase the relative accuracy of the characteristics of each filter, if the f c of the filter attempts to adjust the bias current of the g m amplifier accurately the characteristics of each filter it is possible to adjust. また、この回路を用いたICをレイアウトする場合、回路ブロック間の配線抵抗の影響を受けないことから、レイアウト時の自由度が増し、レイアウト時間の短縮、及び性能の向上が可能となる。 Further, when laying the IC using this circuit, since it is not affected by the wiring resistance between the circuit blocks, it increases the degree of freedom in layout, enables reduced layout time, and performance improvement of.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明のバイアス回路の一実施例を示す回路構成図である。 1 is a circuit diagram showing one embodiment of a bias circuit of the present invention.

【図2】従来のバイアス回路の回路構成図である。 2 is a circuit diagram of a conventional bias circuit.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 第1の回路ブロック 2〜4 第2〜第4の回路ブロック 5 第1の電源ライン 6 第2の電源ライン 7 電流源 8〜10 第1のカレントミラーを構成するトランジスタ 11,13〜15 第2のカレントミラーを構成するバイポーラトランジスタ 12 第2のカレントミラーを構成するMOSトランジスタ 16 バイアス電圧配線 1 transistor 11,13~15 constituting the first circuit block 2-4 second to fourth circuit block 5 the first power supply line 6 and the second power supply line 7 current source 8-10 a first current mirror of the MOS transistor 16 bias voltage wiring constituting the bipolar transistor 12 and the second current mirror constituting the second current mirror

フロントページの続き (72)発明者 松野 靖司 東京都大田区下丸子3丁目30番2号 キヤ ノン株式会社内 Of the front page Continued (72) inventor Yasushi Matsuno Ota-ku, Tokyo Shimomaruko 3-chome No. 30 No. 2 Canon within Co., Ltd.

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 第1のカレントミラー回路を有する一の回路ブロックと、該第1のカレントミラー回路の出力電流が供給される第2のカレントミラー回路をそれぞれ有する複数の他の回路ブロックとを備えたバイアス回路。 And 1. A first circuit block having a first current mirror circuit, and a plurality of other circuit blocks having a second current mirror circuit respectively output current of the current mirror circuit of the first is supplied bias circuit with.
  2. 【請求項2】 請求項1記載のバイアス回路において、 2. A bias circuit according to claim 1,
    前記第2のカレントミラー回路は、電流をミラーするバイポーラトランジスタと、該バイポーラトランジスタのベース電流を供給する絶縁ゲート型トランジスタとを備えてなるバイアス回路。 Said second current mirror circuit, a bipolar transistor and a bias circuit comprising an insulating gate type transistor for supplying a base current of the bipolar transistor to mirror current.
JP7147133A 1995-06-14 1995-06-14 Bias circuit Pending JPH08340243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7147133A JPH08340243A (en) 1995-06-14 1995-06-14 Bias circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7147133A JPH08340243A (en) 1995-06-14 1995-06-14 Bias circuit

Publications (1)

Publication Number Publication Date
JPH08340243A true JPH08340243A (en) 1996-12-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP7147133A Pending JPH08340243A (en) 1995-06-14 1995-06-14 Bias circuit

Country Status (1)

Country Link
JP (1) JPH08340243A (en)

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