JPH0422026B2 - - Google Patents
Info
- Publication number
- JPH0422026B2 JPH0422026B2 JP57114241A JP11424182A JPH0422026B2 JP H0422026 B2 JPH0422026 B2 JP H0422026B2 JP 57114241 A JP57114241 A JP 57114241A JP 11424182 A JP11424182 A JP 11424182A JP H0422026 B2 JPH0422026 B2 JP H0422026B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- resistors
- diffused
- collector
- emitter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 3
- 238000003491 array Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11801—Masterslice integrated circuits using bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Description
【発明の詳細な説明】
発明の技術分野
本発明は、マスタースライス方式のゲートアレ
イ半導体集積回路に関し、特に内部ゲートのパワ
ー変更を容易に行えるようにするものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a master slice type gate array semiconductor integrated circuit, and particularly to a device that allows power changes of internal gates to be easily performed.
従来技術と問題点
最終の配線工程だけを残した予め多数のゲート
に必要な素子を半導体基板に形成しておくマスタ
ースライスLSIでは、内部ゲートのパワーを最終
配線工程で選択する余地はない。このため回路動
作上スピードの速い部分に使用するゲートのパワ
ーは大きくし、またスピードの遅くともよい部分
のゲートパワーは小さくする等ということを最終
配線工程で選択することはできない。第１図はこ
の種の内部ゲートの一例で、定電流型のECL（エ
ミツタ結合型ロジツク）を示すものである。Q1，
Q2はカレントスイツチを構成するトランジスタ、
Q3は定電流源用のトランジスタ、Q4，Q5はエミ
ツタホロワ接続された出力段のトランジスタであ
る。このゲートのパワーはトランジスタQ4，Q5，
Q3のエミツタ抵抗REF，REに流れる電流IEF，IE、
特にトランジスタQ3のエミツタ抵抗REに流れる
定電流IEにより決定される。電流IEFは抵抗REFの
値により決定され、電流IEはコレクタ側の抵抗RC
およびエミツタ側の抵抗REの値で決定されるが、
抵抗比RC／REが出力振幅VOLに影響するので通常
はRC／REが変化しないようにRC，REを変えてIE
を決定する。ところが従来のマスタースライス方
式ではこれらの抵抗（拡散抵抗）REF，RC，REの
値は拡散プロセスで一義的に決定されてしまうの
で、個々のゲートのパワーを最終配線で変更する
ことはできない。Prior Art and Problems In a master slice LSI in which elements necessary for a large number of gates are formed on a semiconductor substrate in advance, leaving only the final wiring process, there is no room to select the power of the internal gates in the final wiring process. For this reason, it is not possible to select in the final wiring process, such as increasing the gate power used in parts where the circuit operation speed is high and reducing the gate power used in parts where the speed can be slow. Figure 1 shows an example of this type of internal gate, which is a constant current type ECL (emitter-coupled logic). Q1 ,
Q 2 is the transistor that constitutes the current switch,
Q 3 is a constant current source transistor, and Q 4 and Q 5 are emitter follower-connected output stage transistors. The power of this gate is the transistor Q 4 , Q 5 ,
The current flowing through the emitter resistance R EF , R E of Q 3 I EF , I E ,
In particular, it is determined by the constant current I E flowing through the emitter resistor R E of the transistor Q 3 . The current I EF is determined by the value of the resistor R EF , and the current I E is determined by the value of the resistor R C on the collector side.
It is determined by the value of the resistor R E on the emitter side,
Since the resistance ratio R C /R E affects the output amplitude V OL , normally R C and R E are changed to prevent I E from changing so that R C /R E does not change.
Determine. However, in the conventional master slicing method, the values of these resistances (diffused resistances) R EF , R C , and R E are uniquely determined by the diffusion process, so it is impossible to change the power of each individual gate in the final wiring. Can not.
発明の目的
本発明は予め複数の抵抗パターンを拡散工程で
形成しておくことにより、個々のゲートパワーを
選択可能としようとするものである。OBJECTS OF THE INVENTION The present invention attempts to make it possible to select individual gate powers by forming a plurality of resistance patterns in advance through a diffusion process.
発明の構成
本発明は、多数の外部内部各ゲートのアレイに
必要な素子を予め半導体基板に形成しておき、そ
して最終配線工程で該素子間を接続して所要とす
る回路を構成するマスタースライス方式の半導体
集積回路において、該ゲートが第１の電源と、第
２の電源と、エミツタが共通に接続され、一方の
ベースに入力信号が印加される１対のトランジス
タと、コレクタが該１対のトランジスタのエミツ
タに接続された定電流源用のトランジスタと、該
第１の電源と１対のトランジスタのコレクタとの
間に接続されるコレクタ側抵抗と、該第２の電源
と該定電流源用のトランジスタとの間に接続され
るエミツタ側抵抗とを有し、該コレクタ側抵抗と
エミツタ側抵抗の素子として、複数の抵抗値を選
択できるように、該コレクタ側抵抗値は１本の拡
散抵抗に中間タツプ用のコンタクト用窓を設けた
もの、該エミツタ側抵抗は、前記１本の拡散抵抗
に中間タツプ用のコンタクト窓を設けたものもし
くは相互接続用コンタクト窓を設けた２本以上の
独立した拡散抵抗を形成しておき、該ゲートに必
要なパワーに応じて前記複数の抵抗値のうちいず
れかを選択し、且つ、該コレクタ側抵抗と該エミ
ツタ側抵抗の比がほぼ一定になるよう両抵抗の組
合を選択するよう該抵抗が接続されていることを
特徴とするが、以下図示の実施例を参照しながら
これを詳細に説明する。Structure of the Invention The present invention provides a master slice in which elements necessary for an array of a large number of external and internal gates are formed in advance on a semiconductor substrate, and the elements are connected in the final wiring process to form a required circuit. In the semiconductor integrated circuit of the above-mentioned method, a pair of transistors whose gates are commonly connected to a first power supply, a second power supply, and an emitter, and an input signal is applied to one base; a transistor for a constant current source connected to the emitter of the transistor; a collector side resistor connected between the first power source and the collectors of the pair of transistors; and the second power source and the constant current source. The collector side resistor has an emitter side resistor connected between the transistor and the emitter side resistor. A resistor with a contact window for an intermediate tap is provided in the resistor, and the emitter side resistor is a resistor with a contact window for an intermediate tap in the single diffused resistor, or two or more resistors provided with a contact window for interconnection. An independent diffused resistance is formed, one of the plurality of resistance values is selected depending on the power required for the gate, and the ratio of the collector side resistance to the emitter side resistance is approximately constant. This feature is characterized in that the resistors are connected so as to select a combination of both resistors, which will be described in detail below with reference to the illustrated embodiment.
発明の実施例
第２図および第３図は本発明の一実施例を示す
平面パターンであ。第２図は第１図のコレクタ抵
抗RCに関するもので、１は全長が２・RCの抵抗
値を持つように形成された拡散抵抗、２〜４は該
抵抗の両端および中央部に設けられたコンタクト
用の窓、５はアースGND側のアルミニウム
（Al）配線、６はコレクタ側のAl配線である。ａ
の例は配線５を窓２にコンタクトし、且つ配線６
を窓３にコンタクトしているので、得られる抵抗
値は拡散抵抗１そのものの２・RCである。これ
に対しｂは配線５を窓４まで延長しているので、
得られる抵抗値は拡散抵抗１の半分、つまりRC
である。ｃは配線６を中央部の窓４にコンタクト
し、且つ配線５は両端の窓２，３にコンタクトし
ているため、拡散抵抗１が中央部で折り返された
並列抵抗として機能し、得られる抵抗値はRC／
２となる。Embodiment of the Invention FIGS. 2 and 3 are planar patterns showing an embodiment of the invention. Figure 2 relates to the collector resistor R C in Figure 1, where 1 is a diffused resistor formed so that the total length has a resistance value of 2 R C , and 2 to 4 are provided at both ends and the center of the resistor. 5 is an aluminum (Al) wiring on the earth GND side, and 6 is an Al wiring on the collector side. a
In this example, the wiring 5 is in contact with the window 2, and the wiring 6 is in contact with the window 2.
Since it is in contact with the window 3, the resistance value obtained is 2·R C of the diffused resistor 1 itself. On the other hand, in b, the wiring 5 is extended to the window 4, so
The resulting resistance value is half of the diffused resistance 1, that is, R C
It is. Since the wire 6 is in contact with the window 4 in the center and the wire 5 is in contact with the windows 2 and 3 at both ends, the diffused resistor 1 functions as a parallel resistor folded back in the center, and the resulting resistance is The value is R C /
It becomes 2.
第３図はエミツタ抵抗REに関するもので、１
１〜１３，２２はそれぞれ２・REの抵抗値を持
つ４本の拡散抵抗、１４〜１６，２３および１７
〜１９，２４は両端のコンタクト用窓、２０はト
ランジスタQ3のエミツタ側に接続するAl配線、
２１は負電源VEE側のAl配線である。全てのケー
スで配線２１は窓１７〜１９，２４に接続されて
いるが、ａでは配線２０が窓１４にしか接続され
ていないので、得られる抵抗値は拡散抵抗１１の
みによる２・REである。これに対しｂは配線２
０を窓１４，１５に接続して拡散抵抗１１，１２
を並列に用いているので、得られる抵抗値はRE
である。さらにｃは拡散抵抗１１〜１３，２２を
並列に用いているので、得られる抵抗値はRE／
２となる。 Figure 3 is about the emitter resistance R E , 1
1 to 13, 22 are four diffused resistors each having a resistance value of 2・R E , 14 to 16, 23, and 17
~19, 24 are contact windows at both ends, 20 is Al wiring connected to the emitter side of transistor Q3 ,
21 is an Al wiring on the negative power supply V EE side. In all cases, the wiring 21 is connected to the windows 17 to 19 and 24, but in case a, the wiring 20 is connected only to the window 14, so the obtained resistance value is 2・R E due only to the diffused resistance 11. be. On the other hand, b is wiring 2
0 to the windows 14 and 15 and the diffused resistors 11 and 12
are used in parallel, the resulting resistance value is R E
It is. Furthermore, since the diffused resistors 11 to 13 and 22 are used in parallel for c, the obtained resistance value is R E /
It becomes 2.
第２図ｂと第３図ｂの組合せを標準的なものと
考えると、第２図ａのようにコレクタ抵抗を増加
してゲートパワーを減ずるときはエミツタ側を第
３図ａのようにすることで抵抗比RC／REを一定
に保つことができる。また第２図ｃのようにコレ
クタ抵抗を減らしてゲートパワーを増すときはエ
ミツタ側を第３図ｃのようにすることで抵抗比
RC／REを一定に保つことができる。このように
エミツタ側の抵抗幅（値）の変更は、電流IEの変
化に伴なうトランジスタQ3のVEE変動を補正する
上で不可欠である。これによりパワー変更をして
も出力レベルを変動させずに済む。 Considering the combination of Figures 2b and 3b as standard, when increasing the collector resistance and reducing the gate power as in Figure 2a, the emitter side should be as shown in Figure 3a. This allows the resistance ratio R C /R E to be kept constant. Also, when increasing the gate power by reducing the collector resistance as shown in Figure 2c, the resistance ratio can be increased by changing the emitter side as shown in Figure 3c.
R C /R E can be kept constant. In this way, changing the resistance width (value) on the emitter side is essential to correcting the V EE fluctuation of transistor Q 3 due to changes in current I E. This allows the output level to remain unchanged even if the power is changed.
発明の効果
以上述べたように本発明によれば、ゲートアレ
イ方式のマスタースライスLSIで最終配線工程に
よる内部ゲートパワーに選択性を持たせることが
できるので、最適なパワー配分が可能となる利点
がある。Effects of the Invention As described above, according to the present invention, selectivity can be given to the internal gate power in the final wiring process in a gate array type master slice LSI, which has the advantage of enabling optimal power distribution. be.
またコレクタ側抵抗RCとエミツタ側抵抗REと
の比RC／REを一定に保つて抵抗値調整をするの
で、パワー変更しても出力レベルを変動させずに
済む利点が得られる。 Furthermore, since the resistance value is adjusted while keeping the ratio R C /R E between the collector side resistance R C and the emitter side resistance R E constant, there is an advantage that the output level does not fluctuate even if the power is changed.
第１図はゲートアレイの内部ゲートとして用い
られるECLゲートの等価回路図、第２図および
第３図は本発明の一実施例を示す平面パターン図
である。
図中、１，１１〜１３は拡散抵抗、２〜４はコ
ンタクト用窓、５，６，２０，２１はAl配線で
ある。
FIG. 1 is an equivalent circuit diagram of an ECL gate used as an internal gate of a gate array, and FIGS. 2 and 3 are planar pattern diagrams showing an embodiment of the present invention. In the figure, 1, 11 to 13 are diffused resistors, 2 to 4 are contact windows, and 5, 6, 20, and 21 are Al wirings.
Claims (1)
子を予め半導体基板に形成しておき、そして最終
配線工程で該素子間を接続して所要とする回路を
構成するマスタースライス方式の半導体集積回路
において、 該ゲートが、 第１の電源GNDと、 第２の電源VEEと、 エミツタが共通に接続され、一方のベースに入
力信号が印加される１対のトランジスタQ1，Q2
と、 コレクタが該１対のトランジスタのエミツタに
接続された定電流源用のトランジスタQ3と、 該第１の電源と１対のトランジスタのコレクタ
との間に接続されるコレクタ側抵抗RCと、 該第２の電源と該定電流源用のトランジスタと
の間に接続されるエミツタ側抵抗REとを有し、 該コレクタ側抵抗とエミツタ側抵抗の素子とし
て、複数の抵抗値を選択できるように、該コレク
タ側抵抗値は１本の拡散抵抗に中間タツプ用のコ
ンタクト用窓を設けたもの、該エミツタ側抵抗
は、前記１本の拡散抵抗に中間タツプ用のコンタ
クト窓を設けたものもしくは相互接続用コンタク
ト窓を設けた２本以上の独立した拡散抵抗を形成
しておき、 該ゲートに必要なパワーに応じて前記複数の抵
抗値のうちいずれかを選択し、且つ、該コレクタ
側抵抗と該エミツタ側抵抗の比がほぼ一定になる
よう両抵抗の組合を選択するよう該抵抗が接続さ
れていることを特徴とするマスタースライス方式
の半導体集積回路。[Claims] 1. A master slice in which elements necessary for arrays of a large number of external and internal gates are formed in advance on a semiconductor substrate, and the elements are connected in the final wiring process to form a required circuit. In this type of semiconductor integrated circuit, a pair of transistors Q 1 , whose gates are commonly connected to a first power supply GND, a second power supply V EE , and whose emitters are connected in common, and whose base is applied with an input signal, Q 2
, a constant current source transistor Q 3 whose collector is connected to the emitters of the pair of transistors, and a collector side resistor R C connected between the first power source and the collectors of the pair of transistors. , has an emitter side resistor R E connected between the second power supply and the constant current source transistor, and a plurality of resistance values can be selected as elements of the collector side resistor and the emitter side resistor. As shown, the collector side resistance value is one diffused resistor with a contact window for the intermediate tap, and the emitter side resistor is one diffused resistor with a contact window for the intermediate tap. Alternatively, two or more independent diffused resistors provided with contact windows for interconnection are formed, one of the plurality of resistance values is selected depending on the power required for the gate, and the collector side 1. A master slice type semiconductor integrated circuit, characterized in that the resistors are connected so that a combination of the resistors is selected so that the ratio of the resistors to the emitter side resistors is approximately constant.
Priority Applications (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11424182A JPS595657A (en) | 1982-07-01 | 1982-07-01 | Master slice system semiconductor integrated circuit |
| DE8383303805T DE3381460D1 (en) | 1982-06-30 | 1983-06-30 | INTEGRATED SEMICONDUCTOR CIRCUIT ARRANGEMENT. |
| DE89202021T DE3382726D1 (en) | 1982-06-30 | 1983-06-30 | Integrated semiconductor circuit arrangement. |
| EP89202020A EP0348017B1 (en) | 1982-06-30 | 1983-06-30 | Semiconductor integrated-circuit apparatus |
| EP89202021A EP0344873B1 (en) | 1982-06-30 | 1983-06-30 | Semiconductor integrated-circuit apparatus |
| EP83303805A EP0098173B1 (en) | 1982-06-30 | 1983-06-30 | Semiconductor integrated-circuit apparatus |
| DE89202020T DE3382727D1 (en) | 1982-06-30 | 1983-06-30 | Integrated semiconductor circuit arrangement. |
| US07/229,724 US4904887A (en) | 1982-06-30 | 1988-08-04 | Semiconductor integrated circuit apparatus |
| US07/325,913 US4891729A (en) | 1982-06-30 | 1989-03-20 | Semiconductor integrated-circuit apparatus |
| US07/325,914 US4952997A (en) | 1982-06-30 | 1989-03-20 | Semiconductor integrated-circuit apparatus with internal and external bonding pads |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11424182A JPS595657A (en) | 1982-07-01 | 1982-07-01 | Master slice system semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS595657A JPS595657A (en) | 1984-01-12 |
| JPH0422026B2 true JPH0422026B2 (en) | 1992-04-15 |
Family
ID=14632802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11424182A Granted JPS595657A (en) | 1982-06-30 | 1982-07-01 | Master slice system semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS595657A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59172249A (en) * | 1983-03-18 | 1984-09-28 | Nec Corp | Monolithic integrated circuit |
| JPH02172257A (en) * | 1988-12-25 | 1990-07-03 | Nec Corp | Master-slice method integrated circuit device |
| US9595169B2 (en) | 2006-08-31 | 2017-03-14 | Cfph, Llc | Game of chance systems and methods |
| US8758111B2 (en) | 2008-08-20 | 2014-06-24 | Cfph, Llc | Game of chance systems and methods |
| US8142283B2 (en) | 2008-08-20 | 2012-03-27 | Cfph, Llc | Game of chance processing apparatus |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56158465A (en) * | 1980-05-09 | 1981-12-07 | Hitachi Ltd | Formation of resistance for integrated circuit |
-
1982
- 1982-07-01 JP JP11424182A patent/JPS595657A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56158465A (en) * | 1980-05-09 | 1981-12-07 | Hitachi Ltd | Formation of resistance for integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS595657A (en) | 1984-01-12 |
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