JPH0419810Y2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to a TTL integrated circuit, and more particularly to a shot clamp type TTL logic gate.

Prior Art and Problems As shown in Figure 1, a TTL (transistor-transistor logic) logic gate consists of an input transistor Q ₁ , a phase division transistor Q ₂ , output transistors Q ₃ and Q ₄ , resistors R ₁ to _{R 3} , and a potential It consists of a diode D for adjustment, and when the input IN is at H (high) level, the base current flows to Q ₂ through the path of R ₁ and the collector of Q ₁ , turning on the transistor Q ₂ , which turns on Q ₃ . , _Q4 off, output OUT is L (low)
On the other hand, if the input IN is at L level, the base current of transistor Q ₂ is bypassed to the emitter side of Q ₁ , and Q ₂ is turned off.
An inverter operation is performed in which _Q3 is off, _Q4 is on, and the output OUT becomes H.

Transistors Q ₁ to _{Q 3} are of the shot clamp type, and their equivalent circuit is as shown in FIG. Although the output transistor Q ₃ is taken as an example in FIG. 2, the same applies to the other transistors Q ₁ and Q ₂ . As shown in the figure, a shot clamp type transistor has an SBD (shot bottle barrier diode) connected between the base and collector with the polarity shown, which regulates the collector potential to prevent saturation of the transistor and speed up operation. etc. are aimed at. Regarding the latter, when transistor Q ₃ is turned on, a base current I _B flows through it, but this current is greater than necessary, and the excess current flows through the path between SBD, the collector of Q ₃ , and the emitter. Therefore, the base potential that flows I _B is V _BE , which is normally 0.8V, but the forward voltage V _F of SBD is
Since it is about 0.4V, the collector potential of _Q3 and therefore the L level of output OUT ( _VOL ) is 0.8-0.4=0.4 [V]
stipulated in

By the way, some TTL logic gates have high power consumption, which is unavoidable, but high speed is desirable, while others do not require high speed, so low power consumption is desirable. In order to achieve low speed and low power, the resistance values of resistors R ₁ to _{R 3} are increased without changing their ratios. When the resistance value is increased, the current flowing becomes smaller and power consumption can be reduced, but since the rise and fall of the potential at each part becomes slower, a reduction in operation speed is unavoidable. However, even this is sufficient if operating speed is not so required. However, I realized that there was a problem here.
It is the aforementioned _VOL . The forward voltage V _F of SBD changes depending on the current I, and if I is large, V _F is also large, and I
If is small, V _F is also small. Therefore, if you aim for low power and increase the resistance, the aforementioned I _B will become smaller, which will reduce the current flowing through SBD and lower V _F.
VOL goes up. For example, if V _F = 0.4V when I _B = 2 mA, then V _F = 0.35 V when I _B = 1 mA, and V _OL is 0.4 V.
rises from to 0.45V.

This type of logic gate is usually constructed from an integrated circuit, and in order to reduce costs and shorten delivery times, integrated circuits are prefabricated to a semi-finished state (known as master slicing), and once an order is received, specifications are Once this is determined, a method is adopted in which a completed product is produced by performing as few steps as possible, such as wiring steps. In this case, the connection relationship between transistors and the like can be easily dealt with by changing the pattern of the wiring mask, but it becomes troublesome when power and the like are also affected. In particular, the L level output of short clamp type transistors as the power becomes lower.
Conventionally, no special consideration has been given to fluctuations in V _OL , and no appropriate countermeasures have been found.

Purpose of the invention This invention uses a master slice method that can easily avoid fluctuations in the L-level output of short-clamp transistors due to power changes.
It attempts to provide a TTL logic gate.

Structure of the invention The present invention is a TTL integrated circuit manufactured using the master slicing method and having a ground-side output transistor that is shot-clamped. The electrode wiring is extended to the required number of window openings, and the required number of shot barrier diodes are connected between the base and the collector. explain.

Example of implementation of the invention This invention is shown in an equivalent circuit as shown in Figure 2.
A plurality of SBDs can be configured in advance, and if the power is high, 2, 3, etc. are used, and if the power is low, the number is reduced to 2, 1, etc. In this way, fluctuations in _VOL can be prevented. For example, in the above example, if the base current I _B is 2 mA, two SBDs are used, and when the base current is 1 mA, one SBD is used (assuming all the SBDs are the same size), then V _F is
0.4V, _VOL can be set to 0.8−0.4=0.4V.

An SBD that shot-clamps the collector of a transistor is generally constructed as shown in FIG. In Figure 3a, C is the collector region, CC is its contact region, B is the base region, E is the emitter region formed therein, AL is the aluminum layer that becomes the base electrode wiring, and the collector region is within the dotted line frame C'. The shot barrier is in contact with the base area in the shaded area B', and these B', A, L,
The aforementioned SBD is formed at C′. FIG. 3b shows an example of an SBD formed in a rather large transistor such as an output transistor, and C, B, . . . similarly indicate the collector region, base region, . Third
Figure c is a longitudinal cross-sectional view of Figure 3b;
N ⁺ b is a buried layer, S is a substrate, EP is an epi layer, IS is an isolation layer, and SI is a surface insulating layer. Third
In Figures b and c, two emitter regions E are formed (these are used in parallel), and the same is true of the collector contact region CC, and between these E and E, the base region B is punched out and C' is formed. As shown, the collector region is exposed to the surface. If aluminum base electrode wiring is applied to this state, C′, AL, and B′ will be formed.
SBD is formed. The surface of the master slice is covered with an insulating layer such as an oxide film (SiO ₂ ), and windows are opened in areas where electrode wiring is to be applied, so the window opening area C', which determines the size of the SBD, is when the master slice is completed. It is fixed at this stage and cannot be changed later.

FIG. 4 shows an example of the present invention, in which the same parts as in FIG. 3 are given the same reference numerals. In the present invention, a plurality of windows are opened in the surface insulating layer of the collector region C to create a plurality of regions C' where the surface is exposed. This is the state of the master slice. And in the wiring process,
If the number of SBDs is one, the base electrode wiring AL is extended to the first region C', and if the number of SBDs is two, the base electrode wiring AL is extended to the next region C' as shown in the figure. If you do it like this
B', AL, the first C', and the next C' form one or two SBDs connected between the base and the collector.

The regions C' may be formed anywhere in the collector region, and their sizes may be the same or different. The unused area C' should be closed because if left exposed, it may cause adverse effects such as element deterioration. It is easy to deposit aluminum on this in the same wiring process, but to leave the aluminum layer isolated. It is possible to connect multiple regions C' without isolating them, that is, to create long or large regions C' and adjust the area covered by the aluminum electrode wiring, but the above surface protection Considering this, the isolated method is better.

Effects of the invention As explained above, in this invention, the size of SBD can be selected according to the power, and it can be applied to a master slice type shot clamp type TTL logic gate to prevent fluctuations in V _OL . This has the effect of not causing a particular increase in costs.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of the TTL logic gate, and Figure 2 is a circuit diagram of its shot clamp section, showing the main parts of the present invention. FIG. 3 is a plan view and a cross-sectional view showing the structure of a conventional shot clamp type transistor;
FIG. 4 is a plan view and a sectional view showing an embodiment of the present invention. In the drawing, _Q3 is a ground-side output transistor that is shot-clamped, C', C', and C' are multiple window openings, and AL is an aluminum base electrode wiring.

Claims (1)

[Claim for Utility Model Registration] In a TTL integrated circuit manufactured by the master slicing method and having a shot-clamped output transistor, a plurality of windows are formed in the surface insulating layer of the collector region of the transistor, and the base electrode TTL characterized in that the wiring is extended to the required number of window openings and the required number of shot barrier diodes are connected between the base and the collector.
Logic integrated circuit.