JP2840150B2 - Semiconductor integrated circuit and interlayer connection method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated structure of a plurality of layers, such as a wiring layer made of polycrystalline silicon or a metal, for electrically connecting different layers, and having a longer dimension than a width dimension. More particularly, the present invention relates to a semiconductor integrated circuit using a contact hole longer than that of the semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which the electric resistance is reduced by the contact hole and a method of connecting the layers.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor integrated circuits has been increasingly improved, and accordingly, the dimensions of contact holes for electrically connecting different layers inside the semiconductor integrated circuit have been increasingly reduced. I have.

However, such small contact holes have a problem that it is difficult to process them with high accuracy.

For example, in the case of a long and thin contact hole , the amount of light wrap around during exposure becomes large,
The photoresist sagging at the time of development or during baking may differ long and short sides of the contact hole, there is a problem that the contact hole width becomes uneven. For example, when a positive resist is used, the width of the central portion of the elongated contact hole may be wide. As described above, if the width of the central portion of the contact hole is increased, a problem arises in that a portion that should not be etched is also etched at the time of etching.

In Japanese Patent Publication No. Sho 62-33746, a contact hole in an elongated contact region is constituted by a plurality of square contact holes arranged at intervals from each other, whereby a contact hole in such an elongated contact region is processed. Improves accuracy.

FIG. 11 is an integrated circuit pattern diagram of a semiconductor integrated circuit using a conventional contact hole .

In the integrated circuit pattern diagram of FIG. 11, a NAND logic gate as shown in the circuit diagram of FIG. 12 is formed by using the contact hole disclosed in the above-mentioned Japanese Patent Publication No. 62-33746. .

That is, in FIG. 11, the power supply line VDD
Between the P-channel MOS transistors TP1 and TP2 and the sources of the P-channel MOS transistors TP1 and TP2.
1 and the drain of the P-channel MOS transistor TP2 and the drain of the N-channel MOS transistor TN1;
In the connection between the source and the ground line GND of N2, it has been used contact hole which is composed of a plurality of square contact holes that are arranged at intervals from each other.

As described above, by applying the technique disclosed in Japanese Patent Publication No. 62-33746, the size of the integrated circuit pattern of a logic gate such as a NAND logic gate is increased in order to improve the degree of integration of a semiconductor integrated circuit. It is possible to improve the processing accuracy of the contact hole used in this semiconductor integrated circuit even when the size of the contact hole is reduced.

[0010]

However, the contact hole disclosed in the above-mentioned Japanese Patent Publication No. 62-33746 is disclosed.
When a contact hole is used, a portion between the plurality of contact holes in the integrated circuit pattern is not used for electrical connection, so that the area of the contact region where the contact hole can be arranged is provided. Cannot be used effectively. Therefore, there is a problem that the electric resistance due to the contact hole is increased, and the electric characteristics are deteriorated.

That is, in FIG. 11, an output current output from the output terminal Y flows through a predetermined contact hole when supplied from the power supply line VDD or the ground line GND. At this time, if the electrical resistance of each contact hole increases, the output characteristics and the like of the logic gate deteriorate.

The present invention has been made to solve the above-mentioned conventional problems, and electrically connects different layers of a multilayer structure of a plurality of layers such as a wiring layer made of polycrystalline silicon or metal. in the semiconductor integrated circuit and the interlayer connection towards than the dimension in the width direction of the longitudinal dimension with long contact hole in comparison, with even fine pore contact hole, thereby improving the processing accuracy, the contact E
Hesi low electrical resistance due Lumpur, an object of Figure <br/> Rukoto improvement of electrical characteristics.

[0013]

According to the present invention, there is provided a multilayer structure of a plurality of layers such as a wiring layer made of polycrystalline silicon or metal, which electrically connects different layers to each other in a longitudinal direction rather than a width direction. In a semiconductor integrated circuit provided with a contact hole having a dimension longer than that of the first figure, the contact hole has a first figure whose dimension W1 in the width direction and a dimension L1 of the dimension in the longitudinal direction are substantially equal to each other. The object has been achieved by including a shape in which an outer dimension W2 is shorter than the outer dimension W1 in the width direction of the first graphic and is linearly connected with the center line substantially aligned. It is.

Further, according to the present invention, a multilayer structure of a plurality of layers such as a wiring layer made of polycrystalline silicon or metal is provided between different layers.
In the interlayer connection method of a semiconductor integrated circuit for electrically connecting using a contact hole having a longer dimension in the longitudinal direction than the dimension in the width direction, the dimension W1 of the external dimension in the width direction and the dimension of the external dimension in the longitudinal direction are different. A first having substantially the same dimension L1
The center line between the figure and the second figure whose dimension W2 in the width direction is shorter than the dimension W1 in the width direction of the first figure.
A contact hole including a shape that is substantially matched and linearly connected is used.

[0015]

According to the present invention, the degree of integration of a semiconductor integrated circuit is improved,
The size of the contact hole used in the semiconductor integrated circuit is reduced, and the amount of light wrap around during exposure is increased during processing of the contact hole , and photoresist dripping during development or baking occurs. In such a case, the present inventors have found a shape of a contact hole that can reduce such a problem and effectively use the area of a contact region where a contact hole can be arranged.

FIG. 1 is an integrated circuit pattern diagram showing the gist of the present invention.

In FIG. 1, contact holes 30
Is a total of three first figures 10 and a total of two second figures 2
0. That is, contact hole 3
0 has a shape in which the first figure 10 and the second figure 20 are alternately connected.

In FIG. 1, the dimension W1 of the outer shape of the first figure 10 in the width direction is substantially equal to the dimension L1 of the outer shape of the first figure 10 in the longitudinal direction.

The outer dimension W2 of the second figure 20 in the width direction is smaller than the outer dimension W1 of the first figure 10 in the width direction.
Is getting narrower.

The ratio of the dimension W1 to the dimension W2 is determined according to the following equation according to the dimension of W1 in consideration of processing techniques (accuracy) such as photoresist shaping and etching.
Can be determined.

[0021]

(Equation 2)

The inventor has made such a first figure 10 and a second figure
By using the shape in which the figures 20 are connected, it is possible to reduce the amount of light wraparound during exposure and to reduce unevenness between the long side and the short side of the contact hole due to photoresist dripping during development or baking. Heading.

According to the shape of the contact hole of the present invention, the area of the contact region in which the contact hole can be arranged is effectively used, and the electric resistance of the contact hole is improved. And electrical characteristics of the logic gates and the like can be improved.

In the present invention, the shape of the first graphic and the shape of the second graphic 20 are not limited to a square or a rectangle as shown in FIG. 1, but may be a polygon such as a pentagon or a hexagon. , A shape including a part of a curve, such as a circle or an ellipse.

That is, the dimension W1 of the outer shape in the width direction of the first figure 10 is substantially equal to the dimension L1 of the outer shape in the longitudinal direction of the first figure 10, and the dimension W of the outer shape in the width direction of the second figure 20 is set.
2 may be smaller than the dimension W1 of the outer shape of the first figure 10 in the width direction.

For example, as shown in FIG.
0 may be a polygon such as an octagon.

Also, as shown in FIG.
The shape of the contact hole may be a shape including a shape obtained by connecting the second figure 20 and the other figure 40. That is, 1
In one of the contact holes , the shape of the contact hole of the present invention may be used only in a portion for improving the processing accuracy.

Further, as shown in FIG. 4, three or more types of figures (in FIG. 4, three types of first figure 10, second figure 20, and third figure 50) are regularly repeated. The shape of the contact hole including the connected shape may be used. In FIG. 4, the first figure 1 having substantially the same dimensions but different shapes is shown.
Zero or third figures 50 are alternately arranged between the second figures 20 which are narrower than these.

Further, as shown in FIG. 5, three or more types of figures (in FIG. 5, three types of figures, a first figure 10, a second figure 20, and a third figure 50) are arranged in another order (FIG. 5). 5, two first figures 10 and one third figure 50 may be arranged in sequence between the second figures 20 arranged alternately.

Further, as shown in FIG. 6, three or more types of figures (in FIG. 6, first figure 10, second figure 20,
The shape of the contact hole may be a shape including a shape in which three types of figures 50) are randomly arranged. In FIG.
The first figure 10 or the third figure 50 and the second figure 20 are arranged alternately, but the first figure 10 and the third figure 50 are arbitrarily arranged.

As described above, according to the present invention, a contact hole used in a semiconductor integrated circuit has a fine contact hole.
Even in the case of a hole , the processing accuracy can be improved, the electrical resistance of the contact hole can be reduced, and the electrical characteristics can be improved.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 7 is an integrated circuit pattern diagram of the first embodiment of the present invention.

The circuit of FIG. 7 corresponds to the NAN of FIG.
The circuit is the same as the integrated circuit pattern diagram of the D logic gate.

In FIG. 7, the present invention is applied to a total of five contact holes out of a total of nine contact holes . That is, the power lines VDD and P
Connection between the source of the channel MOS transistor TP1, the power supply line VDD and the P-channel MOS transistor T
Connection between the source of P2, the drain of P-channel MOS transistor TP1, the drain of P-channel MOS transistor TP2, and the N-channel MOS transistor T
The present invention is applied to the connection between the drain of N1 and the contact hole used for the connection between the source of the N-channel MOS transistor TN2 and the ground line GND.

The contact housing to which the present invention is applied
In this case, the area of the contact hole is increased by about 40% as compared with the corresponding contact hole of the related art shown in FIG. Accordingly, in the contact holes to which the present invention shown in FIG. 7 is applied, the electric resistance is reduced as compared with the related art. Therefore, in the NAND logic gate shown in FIG.
That is, the improvement that the output current that can be supplied from the output terminal Y can be increased is achieved.

Next, referring to FIG.
In order to prevent cracking of the Al layer (for example, Al ₂ ) in the corner portion 60A, a contact horn for connection with another Al layer (for example, Al ₁ ) disposed in the corner portion 60A.
A second embodiment of the present invention will be described in which the present invention is applied to a contact hole 66 for fixing the Al _{1 to} the semiconductor substrate 62 and a hole 64.

[0038] In this embodiment, the connection contact hole
In each of the rule 64 and the fixing contact hole 66, the first square figure 10 is arranged in a two-dimensional matrix, and the first figure 10 is connected by the rectangular second figure 20 therebetween.

In FIG. 8, 68 is a diffusion layer, and 70 is I
The / 0 cell 72 is a bonding pad.

FIG. 9 is a sectional view taken along line AA of FIG.

In FIG. 9, 72A and 72B are LOCOs.
The S layer, 74 and 76 are interlayer insulating films, and 78 is a passivation film.

[0042] The Contact smaller spacing of the first graphic 10, when between the photoresist is likely to peel, for example as in the modification shown in FIG. 10, around I <br/> by the contact hole The first figure 10 and the second figure 20 can also be connected in a zigzag manner so that an area completely separated from the first figure does not occur.

[0043]

According to the present invention, a fine contact hole
With such a structure, it is possible to obtain an excellent effect that the processing accuracy can be improved, the electrical resistance due to the contact hole can be reduced, and the electrical characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a first integrated circuit pattern diagram showing the gist of the present invention.

FIG. 2 is a second integrated circuit pattern diagram showing the gist of the present invention;

FIG. 3 is a third integrated circuit pattern diagram showing the gist of the present invention;

FIG. 4 is a fourth integrated circuit pattern diagram showing the gist of the present invention;

FIG. 5 is a fifth integrated circuit pattern diagram showing the gist of the present invention.

FIG. 6 is a sixth integrated circuit pattern diagram showing the gist of the present invention;

FIG. 7 is an integrated circuit pattern diagram of the first embodiment of the present invention.

FIG. 8 is an integrated circuit pattern diagram according to a second embodiment of the present invention.

FIG. 9 is a sectional view taken along line AA of FIG. 8;

FIG. 10 is an integrated circuit pattern diagram of a modification of the second embodiment.

FIG. 11 is an integrated circuit pattern diagram of a conventional NAND logic gate.

FIG. 12 is a circuit diagram of a NAND logic gate;

[Explanation of symbols]

10: first figure 20: second figure 30, 64, 66 ... contact hole 40 ... other figure 50: third figure W1: width dimension of first figure in width direction W2: width dimension of second figure in width direction L1: Dimension of the external shape in the longitudinal direction of the first graphic L2: Dimension of the external shape in the longitudinal direction of the second graphic VDD: Power supply (power supply line) GND: Ground (ground line) A, B: Input Y: Output TP1, TP2 ... P-channel MOS transistor TN1, TN2 ... N-channel MOS transistor

Claims (5)

(57) [Claims] In a laminated structure of a plurality of layers such as a wiring layer made of polycrystalline silicon or metal, a length in a longitudinal direction is longer than a dimension in a width direction for electrically connecting different layers. In a semiconductor integrated circuit having a contact hole, the contact hole has a first figure in which a width-direction outer dimension W1 and a length-direction outer dimension L1 are substantially equal to each other; the semiconductor integrated circuit which comprises a shorter than the dimension W1 of the first figure the width direction of the outer shape of the second figure, the linearly linked shape substantially aligned with the center line. 2. The semiconductor integrated circuit according to claim 1, wherein
A semiconductor integrated circuit, wherein the dimension W1 of the outer shape in the width direction of the first figure and the dimension W2 of the outer shape in the width direction of the second figure satisfy the following expression. (Equation 1) 3. The semiconductor integrated circuit according to claim 2,
2. The semiconductor integrated circuit according to claim 1, wherein the first graphic and the second graphic are alternately arranged. 4. The semiconductor integrated circuit according to claim 2, wherein
2. The semiconductor integrated circuit according to claim 1, wherein the contact hole includes another graphic in addition to the first graphic and the second graphic. 5. A laminated structure of a plurality of layers, such as a wiring layer made of polycrystalline silicon or metal, using a contact hole whose length in the longitudinal direction is longer than that in the width direction between different layers. In the method for interlayer connection of a semiconductor integrated circuit for electrical connection, the first figure in which the dimension W1 in the width direction and the dimension L1 in the longitudinal direction are substantially equal to each other, and the dimension W2 in the width direction, and a short second graphic than the dimension W1 in the width direction of the outer shape of the first figure, the interlayer connection method of a semiconductor integrated circuit, which comprises using a contact hole comprising linearly linked shape substantially aligned with the center line .