GB1564784A

GB1564784A - Device

Info

Publication number: GB1564784A
Application number: GB1208877A
Authority: GB
Original assignee: Tokyo Shibaura Electric Co Ltd
Current assignee: Toshiba Corp
Priority date: 1976-04-27
Filing date: 1977-03-22
Publication date: 1980-04-16
Also published as: JPS52130580A

Description

(54) IC DEVICE (71) We, TOKYO SHIBAURA ELECTRIC COMPANY LIMITED, a Japanese company, of 72, Horikawa-cho, Saiwai-ku, Kawasakishi, Kanagawa-ken, Japan, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- This invention relates to a semi-conductor integrated circuit device, and is particularly, but not exclusively, concerned with a high density integrated circuit device consisting of silicon gate MOS FET's (Metal Oxide Semi-conductor Field Effect Transistors).

A semi-conductor integrated circuit device having silicon gate MOS FET's is well known, in which, in each MOS FET the gate electrode is constituted by a conductive polycrystalline silicon layer. Such an IC device has advantages compared with the known aluminium gate MOS IC device, in that multi-layer wiring can be easily employed; during its manufacture, the wiring layer and the functional elements of the IC device are formed simultaneously, by what is known as the direct contact method.

In the above-mentioned silicon gate MOS FET IC device, the transmission time of the signal to the gate electrode is important.

That signal is delayed, because of the high resistance of the wiring connecting the gate electrodes of the transistors. It is not possible to reduce the resistance, i.e. to increase the conductivity of the polycrystalline layer, by increasing the content of the impurity diffused into the polycrystalline layer, because the proportion of impurity that can be so diffused is limited.

If the thickness of the polycrystalline layer forming the gate electrode and the interconnecting wiring is increased, in order to increase the conductivity, the problem of "side etch phenomenon" illustrated in Figure 1 of the accompanying drawings arises. That figure shows a substrate 12 having therein a source and drain regions 13, 14 and overlaid by an insulating film 15. A gate electrode layer 10, which bridges the regions 13, 14 is applied by using an etching technique, e.g. the application of a fluorine plasma with a photoresist film 11 as a mask.

When etching is effected, a side etch C occurs, removing the gate electrode layer 10 from beneath the edges of the photoresist film 11; the amount of the side etch is approximately equal to the etch B, the thickness of the layer 10. Consequently, the width of the polycrystalline silicon layer 10 becomes less than the mask width by about twice the thickness of the film 10 (2B=2C).

Furthermore, in a manufacturing line, variations occur, e.g. in the thickness of the polycrystalline layer and in the etching rate, and therefore the finished dimensions of the gate electrode layer vary greatly, causing variations in the mutual conductance and the threshold voltage characteristics of the MOS transistors. For those reasons, it is clearly desirable to make the gate electrode layer thin, which, using the known direct contact method, necessarily entails that the interconnecting wiring layer is made equally thin, as the gate electrode layer and the wiring are formed integrally. It is thus not possible simultaneously to reduce the resistance of the wiring and to minimise the side etch of the gate electrode layer.

Broadly, in the present invention the gate electrode layer and the interconnecting wiring layer are formed separately, and the latter has a thickness substantially greater than the former. Thus, in accordance with the present invention, a semi-conductor integrated circuit device comprises a semiconductor substrate of one conductivity type, spaced source and drain regions formed in the substrate, of another conductivity type, an insulating oxide film formed on the substrate and bridging the source and drain regions, a first polycrystalline silicon film on the insulating oxide film and forming a gate electrode layer, and a second polycrystalline silicon film which is thicker than the first film, which is connected to the gate electrode layer, and which forms an interconnecting wiring layer. It is preferred to have the thickness of the gate electrode layer less than 0.2 EL and the thickness of the interconnecting wiring layer greater than 0.3 ,a.

The invention will be more readily understood by way of example from the following description of a MOS FET IC, reference being made to Figures 2 to 4 of the accompanying drawings, in which: Figure 2 is a perspective view illustrating a part of the IC; Figure 3 is a transverse section through the IC of Figure 2; and Figure 4 is a longitudinal section through the IC.

Although Figures 2 to 4 illustrate only one transistor, it is to be understood that the IC incorporates many transistors identical with that shown, and formed simultaneously.

Figures 2 to 4 show a semi-conductor substrate 12 of one conductivity type, in which are formed spaced source and drain regions 13, 14 of another conductivity type.

A gate insulating layer 15 bridges the regions 13, 14 and is overlaid by a first polycrystalline silicon film 16 constituting the gate electrode layer of the MOS FET. The gate electrode film 16 extends longitudinally to a contact portion 17, where it is connected to a second polycrystalline silicon film 18 constituting an interconnecting wiring layer. The second polycrystalline film 18 is substantially thicker than the first gate electrode film 16. For example, the film 16 has a thickness of less than 0.2,u and the film 18 a thickness of 0.3 u or greater. If the gate electrode film 16 has a thickness less than 0.2 , the side etch is insignificant, while the grgeater thickness of the wiring film 18 is such that its conductivity is high. The gate electrode film 16 plays a small part in signal delay, so that the enlarged thickness of the wiring film 18 results in the avoidance of substantial signal delay. Furthermore, as the gate electrode film and the interconnecting wiring film are made of the same material, they have good mutual affinity and electrical connection between them is made without difficulty.

In the manufacture of the IC, a thick silicon oxide film 19, called the field insulating layer, is first applied to the substrate 12 to separate the elements from each other, and is selectively removed by the photoetching method to form an aperture where each MOS transistor is to be formed. Next an oxide film is applied to form the gate insulating layer 15, and on top of that film, the first polycrystalline silicon film 16 is formed to constitute the gate electrode. The film 16 should be made as thin as possible in order to prevent excessive variation in gate length by the side etch phenomenon, as already explained. For example, where the gate length of the MOS transistor is 2 ,u, a length demanded in present integrated circuit devices, the error variation in gate length is not more than + 3%, which presents no problem in practice. In order to ensure that tolerance, i.e. to minimise the side etch, the thickness of film 16 is preferably made not greater than 0.15 p. The thinness of film 16 increases the electrical resistance, but provided that only the gate electrode has that thinness, its resistance can be increased by a factor of 2 and 3 without giving rise to difficulty, because the length of the gate electrode film is made far shorter than the length of the interconnecting wiring film and therefore the signal delay due to the resistance of the former is not significant.

The next stage of the manufacturing process is to form the source region 13 and the drain region 14, using the gate electrode film 16 as a mask; diffusion of impurity into the film 16 occurs at the same time. Then, another silicon oxide film 20 is formed over the entire surface of the semi-conductor substrate and, by any suitable etching technique, that film is removed not only at the contact portion 17, but at other locations where connections are to be made, e.g. at the contacts for the drain and source (not shown). The second polycrystalline silicon film is deposited over the entire area of the substrate, and by etching, is caused to form the interconnecting wiring layer 18 and the source and drain electrodes in a predetermined pattern. The resistance of the interconnecting wiring layer 18 depends on its width, length and thickness and the impurity quantity. Those factors, apart from the width, are determined by the degree of integration required, but the thickness can be increased from the values at present employed, to achieve a reduction in resistance, and should not be less than 0.3 Fc, when the delay in signal transmission is substantially reduced.

It will be appreciated that the above-mentioned reduction in signal delay is achieved with insignificant side etch of the gate electrodes. Consequently, although the MOS transistors formed in the integrated circuit are miniaturised, each such transistor has the same mutual conductance and threshold voltage characteristics as in the past.

WHAT WE CLAIM IS: 1. A semi-conductor integrated circuit device comprising a semi-condupctor substrate of one conductivity type, spaced source and drain regions formed in the substrate,

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. regions, a first polycrystalline silicon film on the insulating oxide film and forming a gate electrode layer, and a second polycrystalline silicon film which is thicker than the first film, which is connected to the gate electrode layer, and which forms an interconnecting wiring layer. It is preferred to have the thickness of the gate electrode layer less than 0.2 EL and the thickness of the interconnecting wiring layer greater than 0.3 ,a. The invention will be more readily understood by way of example from the following description of a MOS FET IC, reference being made to Figures 2 to 4 of the accompanying drawings, in which: Figure 2 is a perspective view illustrating a part of the IC; Figure 3 is a transverse section through the IC of Figure 2; and Figure 4 is a longitudinal section through the IC. Although Figures 2 to 4 illustrate only one transistor, it is to be understood that the IC incorporates many transistors identical with that shown, and formed simultaneously. Figures 2 to 4 show a semi-conductor substrate 12 of one conductivity type, in which are formed spaced source and drain regions 13, 14 of another conductivity type. A gate insulating layer 15 bridges the regions 13, 14 and is overlaid by a first polycrystalline silicon film 16 constituting the gate electrode layer of the MOS FET. The gate electrode film 16 extends longitudinally to a contact portion 17, where it is connected to a second polycrystalline silicon film 18 constituting an interconnecting wiring layer. The second polycrystalline film 18 is substantially thicker than the first gate electrode film 16. For example, the film 16 has a thickness of less than 0.2,u and the film 18 a thickness of 0.3 u or greater. If the gate electrode film 16 has a thickness less than 0.2 , the side etch is insignificant, while the grgeater thickness of the wiring film 18 is such that its conductivity is high. The gate electrode film 16 plays a small part in signal delay, so that the enlarged thickness of the wiring film 18 results in the avoidance of substantial signal delay. Furthermore, as the gate electrode film and the interconnecting wiring film are made of the same material, they have good mutual affinity and electrical connection between them is made without difficulty. In the manufacture of the IC, a thick silicon oxide film 19, called the field insulating layer, is first applied to the substrate 12 to separate the elements from each other, and is selectively removed by the photoetching method to form an aperture where each MOS transistor is to be formed. Next an oxide film is applied to form the gate insulating layer 15, and on top of that film, the first polycrystalline silicon film 16 is formed to constitute the gate electrode. The film 16 should be made as thin as possible in order to prevent excessive variation in gate length by the side etch phenomenon, as already explained. For example, where the gate length of the MOS transistor is 2 ,u, a length demanded in present integrated circuit devices, the error variation in gate length is not more than + 3%, which presents no problem in practice. In order to ensure that tolerance, i.e. to minimise the side etch, the thickness of film 16 is preferably made not greater than 0.15 p. The thinness of film 16 increases the electrical resistance, but provided that only the gate electrode has that thinness, its resistance can be increased by a factor of 2 and 3 without giving rise to difficulty, because the length of the gate electrode film is made far shorter than the length of the interconnecting wiring film and therefore the signal delay due to the resistance of the former is not significant. The next stage of the manufacturing process is to form the source region 13 and the drain region 14, using the gate electrode film 16 as a mask; diffusion of impurity into the film 16 occurs at the same time. Then, another silicon oxide film 20 is formed over the entire surface of the semi-conductor substrate and, by any suitable etching technique, that film is removed not only at the contact portion 17, but at other locations where connections are to be made, e.g. at the contacts for the drain and source (not shown). The second polycrystalline silicon film is deposited over the entire area of the substrate, and by etching, is caused to form the interconnecting wiring layer 18 and the source and drain electrodes in a predetermined pattern. The resistance of the interconnecting wiring layer 18 depends on its width, length and thickness and the impurity quantity. Those factors, apart from the width, are determined by the degree of integration required, but the thickness can be increased from the values at present employed, to achieve a reduction in resistance, and should not be less than 0.3 Fc, when the delay in signal transmission is substantially reduced. It will be appreciated that the above-mentioned reduction in signal delay is achieved with insignificant side etch of the gate electrodes. Consequently, although the MOS transistors formed in the integrated circuit are miniaturised, each such transistor has the same mutual conductance and threshold voltage characteristics as in the past. WHAT WE CLAIM IS:

1. A semi-conductor integrated circuit device comprising a semi-condupctor substrate of one conductivity type, spaced source and drain regions formed in the substrate,

of another conductivity type, an insulating oxide film formed on the substrate and bridging the source and drain regions, a first polycrystalline silicon film on the insulating oxide film and forming a gate electrode layer, and a second polycrystalline silicon film which is thicker than the first film, which is connected to the gate electrode layer, and which forms an interconnecting wiring layer.

2. A semi-conductor integrated circuit comprising a semi-conductor substrate of one conductivity type, an apertured oxide field insulating layer formed on the substrate, source and drain regions of another conductivity type formed in the substrate at an aperture in the field insulating layer, an insulating oxide film formed on the substrate and bridging the source and drain regions, a first polycrystalline silicon film on the insulating oxide film and forming a gate electrode, the first polycrystalline film extending to a contact portion on the field insulating layer, and a second polycrystalline silicon film which is thicker than the first polycrystalline film, which is connected to the first polycrystalline film at the contact portion, and which forms an interconnecting wiring layer.

3. A semi-conductor integrated circuit according to Claim 1 or Claim 2, in which the thickness of the first polycrystalline film is less than 0.2 u and the thickness of the second polycrystalline film is greater than 0.3 ,u.

4. A semi-conductor integrated circuit device, substantially as herein described with reference to Figures 2 to 4 of the accompanying drawings.