USRE32207E - Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide - Google Patents

Method for making integrated semiconductor circuit structure with formation of Ti or Ta silicide Download PDF

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USRE32207E
USRE32207E US06/429,299 US42929982A USRE32207E US RE32207 E USRE32207 E US RE32207E US 42929982 A US42929982 A US 42929982A US RE32207 E USRE32207 E US RE32207E
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layer
polysilicon
sio
degrees
overlay
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Hyman J. Levinstein
Shyam P. Murarka
Ashok K. Sinha
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Nokia Bell Labs
Agere Systems LLC
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AT&T Bell Laboratories Inc
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Priority claimed from US05/974,378 external-priority patent/US4276557A/en
Priority claimed from US06/227,133 external-priority patent/US4332839A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to semiconductor integrated circuits.
  • polysilicon In the large scale integration (LSI)-MOS-FET technology, polysilicon has become the standard material for the conducting layer closest to the epitaxial film. Typically, the polysilicon layer is a first layer separated from a second electrically conducting overlay by an insulating layer typically of silicon dioxide. But polysilicon exhibits relatively high resistivity and the lengths of polysilicon paths is limited as a consequence. For example, various functional areas in an integrated circuit chip cannot be interconnected together directly by polysilicon. Rather, the connection from each area are brought out to aluminum bus bars formed from the second overlay. Similarly, LSI high speed circuits require high conductivity input-output lines. The requirement results in the exclusion of polysilicon as a material for such use. Aluminum power lines are needed and this often requires aluminum bonding pads within the chip. The additional aluminum areas are, essentially, wasted space and parallel aluminum conductors create yield problems.
  • a relatively high conductivity material leading to the elimination of aluminum from use in the above-mentioned applications in integrated circuits would lead to, for example, a semiconductor memory cell size reduction of from 30 to 50%.
  • the invention thus comprises a semiconductor integrated circuit including a single crystal semiconductor layer coated by an SiO 2 layer and including a lamelate overlay comprising first and second electrically conducting layers separated by an electrically insulating layer.
  • the structure is characterized in that the overlay comprises a substrate of a polysilicon layer and a layer of a material taken from a class consisting of TiSi 2 and TaSi 2 .
  • FIG. 1 is a projection view of a semiconductor integrated circuit chip
  • FIGS. 2 and 3 are cross-section views of portions of the chip shown packaged in FIG. 1;
  • FIG. 4 is a block diagram of a process for making the chips of FIG. 1.
  • FIG. 1 shows a projection view of a semiconductor chip assembly.
  • the assembly includes a substrate 11.
  • the substrate comprises layers 12 and 13 sandwiching a sunburst pattern 15 of electrical conductors therebetween.
  • Layer 12 includes a centrally disposed square aperture 16 which exposes the inner ends of the conductors of the sunburst pattern.
  • a semiconductor integrated circuit chip 20 is mounted on the portion of layer 13 exposed by the aperture 16.
  • chip 20 includes electrical lands 22 at its periphery for external connection to the exposed inner ends of the electrical conductors of the sunburst.
  • An integrated circuit chip has multiple functional areas defined therein. These areas are interconnected with one another and to lands 22 by conductors defined by patterned layers of electrically conducting material formed on the surfaces of chip 20. These layers are electrically insulated from one another and from the epitaxial layer of the chip typically by silicon dioxide layers. Of course, contact between portions of the conducting layers and various regions of opposite conductivity in the epitaxial layer require through connections.
  • the term "through connection” herein refers to an electrically conducting path from one layer of conducting material through other layers separating it from the epitaxial layer. When through connections are made, electrical continuity is achieved between the areas of the chip and the externally exposed ends of the conductors of the sunburst pattern. The design permits external connection even with an enclosure (not shown) over opening 16 secured in place.
  • Freeform area 30 of FIG. 1 is a representative area of chip 20 and it is to this area that we now turn our attention.
  • FIGS. 2 and 3 show area 30 partially in cross section to expose the plurality of layers from which the chip is constituted.
  • the bottom layer 40 as shown, illustratively, comprises silicon on which an electrically insulating layer of silicon dioxide is formed typically by growing the layer by heating in an oxidizing atmosphere. This step is represented by the top block in FIG. 4.
  • Layer 40 conveniently comprises an epitaxially grown layer 10-20 microns thick and the oxide layer has a thickness of 500-9000 Angstroms.
  • the insulating layer is designated 41 in FIG. 1.
  • the next layer 42 comprises polysilicon formed by chemical vapor deposition (CVD) and has a thickness of about 5000 Angstroms.
  • a layer of titanium of about 1000 Angstroms is deposited on the polysilicon and is then sintered at a temperature of about 900 degrees C. as indicated by the next block in FIG. 4. This step forms approximately 2500 Angstroms of titanium silicide (TiSi 2 ) which is represented at 43 in each of FIGS. 2 and 3.
  • the titanium silicide layer next is heated in an oxygen atmosphere at 1000 degrees C. for 40 minutes to form an SiO 2 layer 44 as indicated by the fourth block from the top in FIG. 4.
  • the next step is to etch a pattern in SiO 2 layer as indicated by the fifth block in FIG. 4.
  • Etching is carried out through a mask by exposure to, for example, a glow-discharge plasma containing C 2 F 6 (55%) and CHF 3 (45%) now a commonly used etchant for SiO 2 to form apertures in the layer as represented at 45 in FIG. 3.
  • a layer of aluminum 0.5% Cu, 2% Si alloy, 1 ⁇ thick is deposited by sputter gun deposition and etched, for example, in a plasma of CCl 4 , Bcl 3 and He.
  • the polysilicon layer provides the silicon source for the reaction of Ti to TiSi 2 .
  • Another purpose is as a source of silicon for subsequent oxidation of the composite TiSi 2 and polysilicon to form SiO 2 .
  • it is necessary therefore to retain the high conductivity through subsequent device processing steps which involve exposure to oxidizing ambients and high temperature to ensure the presence of "excess" polysilicon where "excess" is defined as a layer greater than 1000 Angstroms.
  • a layer of less than 1000 Angstroms results in undesirable defects in the polysilicon.
  • For a 1000 Angstrom layer of titanium a TiSi 2 layer of over 2000 Angstroms is formed with 1 ohm/square resistivity.
  • the TiSi 2 layer has a thickness of less than 5000 Angstroms to avoid stress cracking.
  • Embodiments employing TaSi 2 instead of TiSi 2 are similar in that TaSi 2 is formed by sintering at 900 or 1000 degrees C. or above in H 2 or A r . But the attainable resistivity decreases as the temperature of formation increases above 900 degrees C. Moreover, oxidation is carried out in steam rather than in dry oxygen as is the case with TiSi 2 . These differences related to the use of TaSi 2 are shown in the appropriate blocks of FIG. 4. TaSi 2 on polysilicon does not oxidize in dry ambient at temperature up to 1100 degrees C.
  • molybdenum and Tungsten silicides cannot be used because they form MoO 3 and WO 3 which are volatile at high temperatures commonly used for processing integrated circuits.
  • the following is a specific example of an IGFET fabricated with the above-described TaSi 2 system.
  • the starting material is a substrate of single crystal Si, having a (100) orientation and doped with boron to a resistivity of 7 ohm cm.
  • the Si-substrate is thermally oxidized at 1000 degrees C. for 30 minutes in a dry oxygen ambient to grow an oxide, 350 Angstroms thick. Over this oxide, a thin film of Si 3 N 4 is deposited by chemical vapor deposition from a mixture of silane and ammonia at 680 degrees C.
  • a layer of photoresist is defined into a pattern using standard photolithographic techniques so as to leave the resist over active device areas of the wafer.
  • the Si 3 N 4 is etched from the nonactive "field" areas thus defined, using an rf-glow discharge in a mixture of CF 4 and O 2 .
  • the etched areas are implanted with boron ions accelerated to a voltage of 30 kV and up to a total dose of 1.5 ⁇ 10 13 ions/cm 2 .
  • This step leads to the formation of a heavily p-doped channel stop with a high threshold voltage in the nonactive field areas.
  • the resist is then stripped in an oxygen plasma and the exposed areas of thin oxide in the field region are etched in a solution of buffered HF down to bare Si. With the active areas masked by the Si 3 N 4 film, the wafer is subjected to a mixture of 10 percent O 2 +90 percent N 2 at 1100 degrees C. for 20 minutes, to drive in the implanted B ions and then to a steam ambient at 1000 degrees C.
  • a field oxide 10,000 Angstroms thick.
  • the masked areas are cleaned by successively etching in buffered HF, hot H 3 PO 4 (180 degrees C.) and buffered HF down to Si in the active gate area.
  • a thickness of 550 Angstroms of gate oxide is then grown at 1000 degrees C. in a mixture of O 2 +3% HCl for 42 min.
  • the oxide is annealed, insitu, for 1/2 hour in Ar also at 1000 degrees C. to provide optimum electrical characteristics of the Si/Si--O 2 interface.
  • the Si in the gate areas is implanted with B at 3 keV to a dose of 5 ⁇ 10 11 cm -2 .
  • a layer of poly-Si, 5000 Angstroms thick is deposited by low pressure CVD from SiH 4 at 650 degrees C., after which the poly-Si is diffused with phosphorous at 1000 degrees C. for 60 min. using PBr 3 as the diffusion source. During this step, a thin layer of SiO 2 containing phosphorus forms over the poly-Si; this oxide is removed by etching in a mixture of 50 parts H 2 O and 1 part HF for 10 min.
  • a thin film of Ta, 1000 Angstroms thick is deposited over the poly-Si using a magnetron sputter source. The film is then annealed at 1000 degrees C. for 30 min. in pure Ar or H 2 to form approximately 2500 Angstroms of TaSi 2 .
  • the sheet resistance of this composite structure is less than 2 ohms per sq. It is important that the annealing ambient be free of oxygen or moisture; otherwise an oxide of Ta is formed and the sintering reaction does not go to completion.
  • a desired pattern of a masking layer consisting of photoresist is formed over the TaSi 2 by using standard lithographic techniques.
  • the TaSi 2 and poly-Si layers are next etched in a plasma of CF 4 +8% O 2 at a pressure of 150 millitorr, and at a power of 200 watts.
  • the etch-rate of the TaSi 2 layer is about 500 Angstroms/min and that of the poly-Si layer is approximately 1000 Angstroms/min. The etching, the photoresist is removed and then the water is cleaned.
  • Source and drain areas of the MOSFET are formed by Ion-implanting Arsenic at 30 kV and a dose of 7 ⁇ 10 15 cm -2 through the thin oxide layers.
  • the previously defined areas of TaSi 2 /poly-Si and thick oxide in the field region act as a mask against Arsenic implantation.
  • a thin layer of oxide is grown over the silicide areas in steam at 1000 degrees C. for 10 min.
  • the top of the wafer is coated with photoresist and various layers are etched off the back of the wafer in the following sequence: SiO 2 (buffered HF, 2 min.), poly-Si (1% Cr O 3 in 25:1 H 2 O:HF 5 min.) and SiO 2 (buffered HF, 10 min).
  • a layer of 1 ⁇ thick phosphorus doped SiO 2 (7% P-glass) is deposited using a reaction of SiH 4 , O 2 and PH 3 at 480 degrees C. This oxide is flowed at 1100 degrees C. for 15 min. in nitrogen to achieve a smooth topology.
  • Windows (apertures) are opened in the P-glass down to the diffused Si in the source and drain areas and to the TaSi 2 gate.
  • the wafers are gettered at 1000 degrees C. in PB 3 for 30 min. This step helps remove unwanted heavy metal impurities from the active surface regions of the wafer to the back of the wafer.
  • the windows are cleaned in 30:1 H 2 O:BHF for 1 to 3 min., after which the wafers are annealed at 700 C. in H 2 for 30 min. to reduce the slow-trapping instability in the gate oxide.
  • a top metallization layer consisting of Al 0.5% Cu, 0.7 ⁇ thick, is deposited using the sputter gun.
  • the metal is defined using photolithography and standard chemical etching to form contacts, interconnections, and bonding pads.
  • the top of the wafer is coated with photoresist, and then the phosphorus-doped Si-layer, which formed in the back of the wafer during gettering, is removed by plasma etching in a mixture of CF 4 +8%O 2 at 50 watts for 20 min., following which the resist is stripped in an O 2 plasma at 100 watts for 10 min.
  • the wafers are annealed in H 2 at 450 degrees C. for 1/2 hour to assure ohmic contacts and to anneal out surface states in the gate oxide.
  • a final passivation layer of 1 ⁇ thick Si-N is deposited by plasma enhanced chemical vapor deposition from a mixture of SiH 4 , NH 3 and Ar at 330 degrees C. Bonding pad areas are opened up by etching Si-N in a CF 4 /O 2 plasma.
  • the back of the wafer is cleaned and a film of Ti followed by Au is deposited by sequential evaporation.
  • the devices are tested, separated into chips and packaged by bonding the back of the chip to a metallized mini ceramic with a Au, Si eutectic alloy, and by bonding Au-wires to the Al bonding pads and to metallized interconnections on the package leading to dual-in-line pins.
  • the hermetic packaging is completed by soldering a top cover plate (not shown in the Figures in a dry N 2 ambient.
  • the polysilicon layer is doped N or P depending on the desired threshold voltage of the gate to be formed. Undoped polysilicon cannot be so used because it adds effectively to the thickness (capacitance) of the gate oxide due to its high resistivity.

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Abstract

The compounds TiSi2 and TaSi2 have been found to be suitable substitutes for polysilicon layers in semiconductor integrated circuits. Suitable conducting properties of the compounds are ensured by providing a relatively thin substrate of polysilicon.

Description

This application is a .Iadd.Reissue of Ser. No. 227,133 filed Jan. 22, 1981, now U.S. Pat. No. 4,332,839 which was a .Iaddend.division of application Ser. No. 974,378, filed Dec. 24, 1978, now U.S. Pat. No. 4,276,557.
FIELD OF THE INVENTION
This invention relates to semiconductor integrated circuits.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuits, as well as the design, manufacture, and operation of such circuits, are well known in the art. Common to such circuits is an epitaxially grown single crystal film in which various regions of different conductivity type are interconnected by multiple layers of patterned electrically conducting material.
A variety of electrically conducting material is available for implementing the layers. Gold, copper, aluminum, polysilicon, and various metal alloys, for example, are all suitable to some extent. On the other hand, each has its drawbacks as is well known in the art.
In the large scale integration (LSI)-MOS-FET technology, polysilicon has become the standard material for the conducting layer closest to the epitaxial film. Typically, the polysilicon layer is a first layer separated from a second electrically conducting overlay by an insulating layer typically of silicon dioxide. But polysilicon exhibits relatively high resistivity and the lengths of polysilicon paths is limited as a consequence. For example, various functional areas in an integrated circuit chip cannot be interconnected together directly by polysilicon. Rather, the connection from each area are brought out to aluminum bus bars formed from the second overlay. Similarly, LSI high speed circuits require high conductivity input-output lines. The requirement results in the exclusion of polysilicon as a material for such use. Aluminum power lines are needed and this often requires aluminum bonding pads within the chip. The additional aluminum areas are, essentially, wasted space and parallel aluminum conductors create yield problems.
A relatively high conductivity material leading to the elimination of aluminum from use in the above-mentioned applications in integrated circuits would lead to, for example, a semiconductor memory cell size reduction of from 30 to 50%.
BRIEF DESCRIPTION OF THE INVENTION
The solution to the foregoing problem is based on the recognition that TiSi2 and TaSi2 uniquely retain high conductivity properties when used with a relatively thin layer of polysilicon. The use of these materials is considered particularly contrary to prior art thinking which indicated that these and like materials cannot be oxidized properly to form a suitable deposition surface for an electrically conducting overlay. If polysilicon is absent, an oxide of titanium may be formed which cannot be etched. Consequently, no connections can be made between an electrically conducting overlay and ones of the conductivity type regions in the epitaxial film therewith. A sintering process is used herein where, for example, TiSi2 is formed in situ at about 900 degrees C. or less in a hydrogen atmosphere on a thin layer of polysilicon. The presence of a layer of polysilicon to which titanium is sintered allows a later oxidation to SiO2 to occur so long as excess polysilicon is present.
The invention thus comprises a semiconductor integrated circuit including a single crystal semiconductor layer coated by an SiO2 layer and including a lamelate overlay comprising first and second electrically conducting layers separated by an electrically insulating layer. The structure is characterized in that the overlay comprises a substrate of a polysilicon layer and a layer of a material taken from a class consisting of TiSi2 and TaSi2.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is a projection view of a semiconductor integrated circuit chip,
FIGS. 2 and 3 are cross-section views of portions of the chip shown packaged in FIG. 1; and
FIG. 4 is a block diagram of a process for making the chips of FIG. 1.
DETAILED DESCRIPTION
FIG. 1 shows a projection view of a semiconductor chip assembly. The assembly includes a substrate 11. The substrate comprises layers 12 and 13 sandwiching a sunburst pattern 15 of electrical conductors therebetween. Layer 12 includes a centrally disposed square aperture 16 which exposes the inner ends of the conductors of the sunburst pattern.
A semiconductor integrated circuit chip 20 is mounted on the portion of layer 13 exposed by the aperture 16. Typically chip 20 includes electrical lands 22 at its periphery for external connection to the exposed inner ends of the electrical conductors of the sunburst.
An integrated circuit chip has multiple functional areas defined therein. These areas are interconnected with one another and to lands 22 by conductors defined by patterned layers of electrically conducting material formed on the surfaces of chip 20. These layers are electrically insulated from one another and from the epitaxial layer of the chip typically by silicon dioxide layers. Of course, contact between portions of the conducting layers and various regions of opposite conductivity in the epitaxial layer require through connections. The term "through connection" herein refers to an electrically conducting path from one layer of conducting material through other layers separating it from the epitaxial layer. When through connections are made, electrical continuity is achieved between the areas of the chip and the externally exposed ends of the conductors of the sunburst pattern. The design permits external connection even with an enclosure (not shown) over opening 16 secured in place.
Freeform area 30 of FIG. 1 is a representative area of chip 20 and it is to this area that we now turn our attention. FIGS. 2 and 3 show area 30 partially in cross section to expose the plurality of layers from which the chip is constituted. The bottom layer 40 as shown, illustratively, comprises silicon on which an electrically insulating layer of silicon dioxide is formed typically by growing the layer by heating in an oxidizing atmosphere. This step is represented by the top block in FIG. 4. Layer 40 conveniently comprises an epitaxially grown layer 10-20 microns thick and the oxide layer has a thickness of 500-9000 Angstroms. The insulating layer is designated 41 in FIG. 1.
The next layer 42 comprises polysilicon formed by chemical vapor deposition (CVD) and has a thickness of about 5000 Angstroms. A layer of titanium of about 1000 Angstroms is deposited on the polysilicon and is then sintered at a temperature of about 900 degrees C. as indicated by the next block in FIG. 4. This step forms approximately 2500 Angstroms of titanium silicide (TiSi2) which is represented at 43 in each of FIGS. 2 and 3.
The titanium silicide layer next is heated in an oxygen atmosphere at 1000 degrees C. for 40 minutes to form an SiO2 layer 44 as indicated by the fourth block from the top in FIG. 4.
The next step is to etch a pattern in SiO2 layer as indicated by the fifth block in FIG. 4. Etching is carried out through a mask by exposure to, for example, a glow-discharge plasma containing C2 F6 (55%) and CHF3 (45%) now a commonly used etchant for SiO2 to form apertures in the layer as represented at 45 in FIG. 3. As indicated in the last two blocks of FIG. 4 a layer of aluminum 0.5% Cu, 2% Si alloy, 1μ thick is deposited by sputter gun deposition and etched, for example, in a plasma of CCl4, Bcl3 and He. The structure of FIG. 3 cannot be realized by prior art techniques in which TiSi2 is formed in the absence of a layer of polysilicon therebeneath. It is characteristic of these materials that, in the absence of polysilicon, they form impenetrable poorly insulating, and undesirable oxide overlays which preclude realization of the structure of FIG. 3. Further, oxidation of the materials in the absence of an underlying polysilicon layer results in a loss of the desirable high conductivity properties.
One purpose of the polysilicon layer is to provide the silicon source for the reaction of Ti to TiSi2. Another purpose is as a source of silicon for subsequent oxidation of the composite TiSi2 and polysilicon to form SiO2. To this end, it is necessary therefore to retain the high conductivity through subsequent device processing steps which involve exposure to oxidizing ambients and high temperature to ensure the presence of "excess" polysilicon where "excess" is defined as a layer greater than 1000 Angstroms. A layer of less than 1000 Angstroms results in undesirable defects in the polysilicon. For a 1000 Angstrom layer of titanium a TiSi2 layer of over 2000 Angstroms is formed with 1 ohm/square resistivity. The TiSi2 layer has a thickness of less than 5000 Angstroms to avoid stress cracking.
Embodiments employing TaSi2 instead of TiSi2 are similar in that TaSi2 is formed by sintering at 900 or 1000 degrees C. or above in H2 or Ar. But the attainable resistivity decreases as the temperature of formation increases above 900 degrees C. Moreover, oxidation is carried out in steam rather than in dry oxygen as is the case with TiSi2. These differences related to the use of TaSi2 are shown in the appropriate blocks of FIG. 4. TaSi2 on polysilicon does not oxidize in dry ambient at temperature up to 1100 degrees C.
Other related silicides such as molybdenum and Tungsten silicides cannot be used because they form MoO3 and WO3 which are volatile at high temperatures commonly used for processing integrated circuits.
The following is a specific example of an IGFET fabricated with the above-described TaSi2 system.
The starting material is a substrate of single crystal Si, having a (100) orientation and doped with boron to a resistivity of 7 ohm cm. The Si-substrate is thermally oxidized at 1000 degrees C. for 30 minutes in a dry oxygen ambient to grow an oxide, 350 Angstroms thick. Over this oxide, a thin film of Si3 N4 is deposited by chemical vapor deposition from a mixture of silane and ammonia at 680 degrees C. A layer of photoresist is defined into a pattern using standard photolithographic techniques so as to leave the resist over active device areas of the wafer. The Si3 N4 is etched from the nonactive "field" areas thus defined, using an rf-glow discharge in a mixture of CF4 and O2. The etched areas are implanted with boron ions accelerated to a voltage of 30 kV and up to a total dose of 1.5×1013 ions/cm2. This step leads to the formation of a heavily p-doped channel stop with a high threshold voltage in the nonactive field areas. The resist is then stripped in an oxygen plasma and the exposed areas of thin oxide in the field region are etched in a solution of buffered HF down to bare Si. With the active areas masked by the Si3 N4 film, the wafer is subjected to a mixture of 10 percent O2 +90 percent N2 at 1100 degrees C. for 20 minutes, to drive in the implanted B ions and then to a steam ambient at 1000 degrees C. for 430 minutes to form a field oxide, 10,000 Angstroms thick. The masked areas are cleaned by successively etching in buffered HF, hot H3 PO4 (180 degrees C.) and buffered HF down to Si in the active gate area. A thickness of 550 Angstroms of gate oxide is then grown at 1000 degrees C. in a mixture of O2 +3% HCl for 42 min. The oxide is annealed, insitu, for 1/2 hour in Ar also at 1000 degrees C. to provide optimum electrical characteristics of the Si/Si--O2 interface. In order to adjust the threshold voltage of MOSFETs, the Si in the gate areas is implanted with B at 3 keV to a dose of 5×1011 cm-2.
A layer of poly-Si, 5000 Angstroms thick is deposited by low pressure CVD from SiH4 at 650 degrees C., after which the poly-Si is diffused with phosphorous at 1000 degrees C. for 60 min. using PBr3 as the diffusion source. During this step, a thin layer of SiO2 containing phosphorus forms over the poly-Si; this oxide is removed by etching in a mixture of 50 parts H2 O and 1 part HF for 10 min. A thin film of Ta, 1000 Angstroms thick, is deposited over the poly-Si using a magnetron sputter source. The film is then annealed at 1000 degrees C. for 30 min. in pure Ar or H2 to form approximately 2500 Angstroms of TaSi2. About 2000 Angstroms of poly-Si is consumed and 3000 Angstroms of poly-Si remains underneath the TaSi2. The sheet resistance of this composite structure is less than 2 ohms per sq. It is important that the annealing ambient be free of oxygen or moisture; otherwise an oxide of Ta is formed and the sintering reaction does not go to completion.
A desired pattern of a masking layer consisting of photoresist is formed over the TaSi2 by using standard lithographic techniques. The TaSi2 and poly-Si layers are next etched in a plasma of CF4 +8% O2 at a pressure of 150 millitorr, and at a power of 200 watts. In this mixture, the etch-rate of the TaSi2 layer is about 500 Angstroms/min and that of the poly-Si layer is approximately 1000 Angstroms/min. The etching, the photoresist is removed and then the water is cleaned.
Source and drain areas of the MOSFET are formed by Ion-implanting Arsenic at 30 kV and a dose of 7×1015 cm-2 through the thin oxide layers. The previously defined areas of TaSi2 /poly-Si and thick oxide in the field region act as a mask against Arsenic implantation. A thin layer of oxide is grown over the silicide areas in steam at 1000 degrees C. for 10 min. The top of the wafer is coated with photoresist and various layers are etched off the back of the wafer in the following sequence: SiO2 (buffered HF, 2 min.), poly-Si (1% Cr O3 in 25:1 H2 O:HF 5 min.) and SiO2 (buffered HF, 10 min).
A layer of 1μ thick phosphorus doped SiO2 (7% P-glass) is deposited using a reaction of SiH4, O2 and PH3 at 480 degrees C. This oxide is flowed at 1100 degrees C. for 15 min. in nitrogen to achieve a smooth topology. Windows (apertures) are opened in the P-glass down to the diffused Si in the source and drain areas and to the TaSi2 gate. The wafers are gettered at 1000 degrees C. in PB3 for 30 min. This step helps remove unwanted heavy metal impurities from the active surface regions of the wafer to the back of the wafer. The windows are cleaned in 30:1 H2 O:BHF for 1 to 3 min., after which the wafers are annealed at 700 C. in H2 for 30 min. to reduce the slow-trapping instability in the gate oxide.
A top metallization layer consisting of Al 0.5% Cu, 0.7μ thick, is deposited using the sputter gun. The metal is defined using photolithography and standard chemical etching to form contacts, interconnections, and bonding pads. The top of the wafer is coated with photoresist, and then the phosphorus-doped Si-layer, which formed in the back of the wafer during gettering, is removed by plasma etching in a mixture of CF4 +8%O2 at 50 watts for 20 min., following which the resist is stripped in an O2 plasma at 100 watts for 10 min. The wafers are annealed in H2 at 450 degrees C. for 1/2 hour to assure ohmic contacts and to anneal out surface states in the gate oxide. A final passivation layer of 1μ thick Si-N is deposited by plasma enhanced chemical vapor deposition from a mixture of SiH4, NH3 and Ar at 330 degrees C. Bonding pad areas are opened up by etching Si-N in a CF4 /O2 plasma.
The back of the wafer is cleaned and a film of Ti followed by Au is deposited by sequential evaporation. The devices are tested, separated into chips and packaged by bonding the back of the chip to a metallized mini ceramic with a Au, Si eutectic alloy, and by bonding Au-wires to the Al bonding pads and to metallized interconnections on the package leading to dual-in-line pins. The hermetic packaging is completed by soldering a top cover plate (not shown in the Figures in a dry N2 ambient. For device fabrication, the polysilicon layer is doped N or P depending on the desired threshold voltage of the gate to be formed. Undoped polysilicon cannot be so used because it adds effectively to the thickness (capacitance) of the gate oxide due to its high resistivity.

Claims (3)

We claim:
1. A method for making a semiconductor device from a wafer including a silicon .[.epitaxial surface.]. layer, said method comprising the steps of heating the wafer in an oxidizing atmosphere for a time and at a temperature for forming a first SiO2 overlay, forming a first layer of doped polysilicon over said SiO2 layer, .[.depositing.]. .Iadd.forming .Iaddend.on said polysilicon layer .Iadd.in a sintering step .Iaddend.a second layer of a .[.material.]. .Iadd.silicide .Iaddend.selected from the group consisting of .[.Ti and Ta sintering the material of said second layer at a temperature and for a time to form a silicide.]. TiSi2 and TaSi2 .[.of the material, respectively,.]. .Iadd.in a manner to avoid the formation of an oxide layer thereover, .Iaddend.heating the wafer for a time and at a temperature to form a second SiO2 overlay while leaving a layer of polysilicon in excess of 1000 Angstroms therebeneath, etching a pattern in said second SiO2 overlay, depositing an electrically-conducting material over said second SiO2 overlay, and etching a pattern in said electrically-conducting material.
2. A method in accordance with claim 1 in which said second layer comprises Ti and is sintered at about 900 degrees C. and heated in an oxygen atmosphere.
3. A method in accordance with claim 1 in which said second layer comprises Ta and is sintered at at least about 1000 degrees C. and is heated in steam.
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US5288666A (en) * 1990-03-21 1994-02-22 Ncr Corporation Process for forming self-aligned titanium silicide by heating in an oxygen rich environment
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
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US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
US5298110A (en) * 1991-06-06 1994-03-29 Lsi Logic Corporation Trench planarization techniques
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US5441094A (en) 1991-06-06 1995-08-15 Lsi Logic Corporation Trench planarization techniques
US5248384A (en) * 1991-12-09 1993-09-28 Taiwan Semiconductor Manufacturing Company Rapid thermal treatment to eliminate metal void formation in VLSI manufacturing process
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