JPS6079748A - Multilayer interconnection structure for semiconductor integrated circuit - Google Patents
Multilayer interconnection structure for semiconductor integrated circuitInfo
- Publication number
- JPS6079748A JPS6079748A JP18806883A JP18806883A JPS6079748A JP S6079748 A JPS6079748 A JP S6079748A JP 18806883 A JP18806883 A JP 18806883A JP 18806883 A JP18806883 A JP 18806883A JP S6079748 A JPS6079748 A JP S6079748A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- insulating film
- hole
- semiconductor integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は半導体集積回路の多層配線構造の改良に関する
。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to improvements in multilayer wiring structures of semiconductor integrated circuits.
（ロ）従来技術
最近半導体集積回路においてはポリイシド膜等の層間絶
縁膜を用いて多層配線を利用し、集積度の向上を図って
いる。(B) Prior Art Recently, in semiconductor integrated circuits, an interlayer insulating film such as a polyamide film is used to utilize multilayer wiring to improve the degree of integration.
具体的に半導体集積回路の多層配線構造は第１図に示す
如く、半導体基板（１）と、基板（１）内に設けた所望
の拡散領域より成る素子（２）と、基板＋１１の素子（
２）を設けた一主面を被覆する酸化シリコンより成る第
１の絶縁膜（３）と、素子（２）の所望の領域にオーミ
ックコンタクトとし第１の絶縁膜（３）上を延在される
蒸着アルミニウムにより形成された第１の電極（４）と
、第１の電極（４）および第１の絶縁膜（３）を被覆す
る層間絶縁のためのポリイシド等より成る第２の絶縁膜
（５）と、第１の電極（４）上の第２の絶縁膜（５）に
設けたスルーホール（６）を介して第１の電極（４）と
接続され第２の絶縁膜（５）上に延在される蒸着アルミ
ニウムにより形成された第２の電極（力と、より構成さ
れている。Specifically, the multilayer wiring structure of a semiconductor integrated circuit, as shown in FIG. 1, includes a semiconductor substrate (1), an element (2) consisting of a desired diffusion region provided in the substrate (1), and an element (
A first insulating film (3) made of silicon oxide covers one main surface provided with 2); A first electrode (4) formed of vapor-deposited aluminum, and a second insulating film (4) made of polyamide or the like for interlayer insulation covering the first electrode (4) and the first insulating film (3). 5) and a second insulating film (5) connected to the first electrode (4) via a through hole (6) provided in the second insulating film (5) on the first electrode (4). A second electrode (formed by vapor deposited aluminum) extends over it.
従来では斯る半導体集積回路の多層配線構造に於いて、
第２の絶縁膜（５）に設けるスルーホール（６）を第２
図（ａ）（ｂ）（Ｃ） Ｋ示す如く正方形、長方形ある
いは円形で形成し５ていた。しかしながら第２の電極（
力に大電流が流れるとスルーホール（６）にも大電流が
流れ、スルーホール（６）のエッヂ部分で第２の電極（
力の段間被覆性（ステップカバレッジ）が悪くなってい
るので第２の電極（７）の電流容量がそこで少なくなり
局部的に発熱をするおそれがあった。Conventionally, in the multilayer wiring structure of such a semiconductor integrated circuit,
The through hole (6) provided in the second insulating film (5) is
As shown in Figures (a), (b), and (C), they were formed into squares, rectangles, or circles. However, the second electrode (
When a large current flows through the force, a large current also flows through the through hole (6), and the second electrode (
Since the step coverage of the force is poor, the current capacity of the second electrode (7) decreases there, and there is a risk of local heat generation.
そして第２の絶縁膜（５）に熱に弱い高分子化合物等を
用いていると、第２の絶縁膜（５）は第１の電極（４）
と第２の電極（７）とが重なる部分で破壊され、層間絶
縁破壊を発生し第１の電極（４）と第２の電極（７）と
が導通する不良を発生する。If a heat-sensitive polymer compound or the like is used for the second insulating film (5), the second insulating film (5) will be used as the first electrode (4).
The first electrode (4) and the second electrode (7) are broken at the overlapped portion, resulting in interlayer dielectric breakdown and a failure in which the first electrode (4) and the second electrode (7) are electrically connected.
（ハ）発明の目的
本発明は断点に鑑みてなされ、従来の欠点を完全に除去
した半導体集積回路の多層配線構造を提供するものであ
る。(c) Purpose of the Invention The present invention has been made in view of the drawbacks and provides a multilayer wiring structure for a semiconductor integrated circuit that completely eliminates the conventional drawbacks.
（→ 発明の構成
本発明による半導体集積回路の多層配線構造は、ａ）
少くとも一主面を有する半導体基板（１）と、ｂ） 該
半導体基板（１）に形成された複数の素子（２）と、
Ｃ） 前記半導体基板（１１の一主面を被覆する第１の
絶縁膜（３）と、
ｄ） 前記素子（２）の所望の領域に接触し且つ前記第
１の絶縁膜（３）上を延在される第１の電極（４）と、
ｅ） 前記第１の絶縁膜（３）及び第１の電極（４）を
被覆する第２の絶縁膜（５）と、
ｆ） 前記第１の電極（４）上の第２の絶縁膜（５）に
周辺が凹凸を有するスルーホール（６）を設け、該スル
ーホール（６）を介して前記第１の電極（４）と接触し
前記第２の絶縁膜（５）上を延在される第２の電極（力
と、
より構成されている。(→ Structure of the Invention The multilayer wiring structure of the semiconductor integrated circuit according to the present invention is a)
a) a semiconductor substrate (1) having at least one main surface; b) a plurality of elements (2) formed on the semiconductor substrate (1); and C) a first semiconductor substrate (1) covering one main surface of the semiconductor substrate (11). d) a first electrode (4) that contacts a desired region of the element (2) and extends over the first insulating film (3); e) the a second insulating film (5) covering the first insulating film (3) and the first electrode (4); f) a second insulating film (5) on the first electrode (4); A through hole (6) having an uneven periphery is provided, and a second electrode contacts the first electrode (4) through the through hole (6) and extends over the second insulating film (5). The electrode (force and consists of
（ホ）実施例
本発明に依れば第１図に示す如く、−主面を有する半導
体基板（１）には−主面より不純物を選択拡散してトラ
ンジスタや抵抗等の複数の素子（２）が集積化されてい
る。基板（１）の−主面は熱酸化による酸化シリコンよ
り成る第１の絶縁膜（３）で被覆される。第１の絶縁膜
（３）にはコンタクト孔を設け、素子（２）の所望の領
域とオーミック接触し且つ第１の絶縁膜（３）上を延在
される蒸着アルミニウムより形成された第１の電極（４
）を設ける。第１の絶縁膜（３）及び第１の電極（４）
上には層間絶縁のためのポリイシド等より成る第２の絶
縁膜（５）を設ける。第１の電極（４）上の第２の絶縁
膜（５）には本発明の特徴とする周辺が凹凸を有するス
ルーホール（６）を形成し、このスルーホール（６）を
介して第１の電極（４）と接続され且つ第２の絶縁膜（
５）上を延在される蒸着アルミニウムによる第２の電極
（７）を設けている。(e) Embodiment According to the present invention, as shown in FIG. ) are integrated. The main surface of the substrate (1) is covered with a first insulating film (3) made of silicon oxide by thermal oxidation. A contact hole is provided in the first insulating film (3), and a first insulating film made of vapor-deposited aluminum is provided in ohmic contact with a desired region of the element (2) and extends over the first insulating film (3). electrode (4
) will be established. First insulating film (3) and first electrode (4)
A second insulating film (5) made of polyamide or the like is provided on top for interlayer insulation. A through hole (6) having an uneven periphery, which is a feature of the present invention, is formed in the second insulating film (5) on the first electrode (4). is connected to the electrode (4) of the second insulating film (
5) providing a second electrode (7) of evaporated aluminum extending above;
本発明の特徴は第２の絶縁膜（５）に設けたスルーホー
ル（６）の形状にある。即ちスルーホール（６）はぞの
周辺が凹凸を有する形状にする。具体的には第３図（ａ
）に示す如く、正方形の各辺を内側にくぼませた形状で
あり、第３図（ｂ）に示す如く長方形の第２の電極（力
の延在方向の一辺を交互に凹凸状とした形状であり、第
３図（Ｃ）に示す如く円形の周辺を凹凸状にして波状に
した形状である。斯上したスルーホール（６）の形状で
はスルーホール（６）の面積に比べて周辺長を大きく取
れるので、第２の絶縁＋＋＝（５）のスルーホール（６
）のエッヂにおけるステップカバレッジの悪さによる大
きい接触抵抗を分散でき等測的にその値を少さくでき、
発熱を抑えることができる。The feature of the present invention lies in the shape of the through hole (6) provided in the second insulating film (5). That is, the through hole (6) is shaped so that the periphery thereof is uneven. Specifically, Figure 3 (a
), each side of a square is concave inward, and as shown in Figure 3(b), the second electrode is rectangular (one side in the direction of force extension is alternately uneven) As shown in Fig. 3(C), the circular periphery is uneven and wavy.In the shape of the through hole (6) described above, the peripheral length is smaller than the area of the through hole (6). Since the second insulation ++=(5) through hole (6
) can disperse the large contact resistance due to poor step coverage at the edge, and reduce its value isometrically.
It can suppress fever.
第４図は本発明による多層配線構造を説明する上面図で
ある。点線で示す部分は第１の電極（４）であり、実線
で示す部分は第２の絶縁膜（５）に形成したスルーホー
ル（６）であり、一点破線で示す部分は第２の電極（７
）である。本実施例では電流の流入方向である第２の電
極（７）の延在方向の一辺に凹凸を設けた長方形のスル
ーホール（６）により発熱を抑えて層間絶縁破壊を防止
している。FIG. 4 is a top view illustrating a multilayer wiring structure according to the present invention. The part indicated by the dotted line is the first electrode (4), the part indicated by the solid line is the through hole (6) formed in the second insulating film (5), and the part indicated by the dotted line is the second electrode (4). 7
). In this embodiment, a rectangular through-hole (6) with an uneven surface on one side in the extending direction of the second electrode (7), which is the current flow direction, suppresses heat generation and prevents interlayer dielectric breakdown.
（へ）発明の効果
本発明に依れば半導体集積回路の多層配線構造に於いて
第２の電極（７）に電流を流しても発熱を抑えられ層間
絶縁が保持できるので、多層配線を制約なく自由に行な
え集積度の向上に寄与できる。(F) Effects of the Invention According to the present invention, even if current is passed through the second electrode (7) in the multilayer wiring structure of a semiconductor integrated circuit, heat generation can be suppressed and interlayer insulation can be maintained, thereby limiting the multilayer wiring. This can be done freely without any problems, and it can contribute to improving the degree of integration.
また本発明ではスルーホールの面積を変えることなく周
辺長を増大させるので、集積度の低下を招くおそれはな
い。更に本発明はその実施に当りスルーホール（６）の
マスクのみの変更で足り、現行の製造工程に直ちに導入
することが可能である。Furthermore, in the present invention, the peripheral length is increased without changing the area of the through hole, so there is no risk of a decrease in the degree of integration. Furthermore, in carrying out the present invention, it is sufficient to change only the mask of the through hole (6), and it can be immediately introduced into the current manufacturing process.
第１図は半導体集積回路の多層配線構造を説明する断面
図、第２図（ａ）（ｂ）（Ｃ）は従来のスルーホールの
形状を説明する上面図、第３図（ａ）（ｂ）（Ｃ）は本
発明のスルーホールの形状を説明する上面図、第４図は
本発明による半導体集積回路の多層配線構造を説明する
上面図である。
（１）は半導体基板、 （２）は素子、 （３）は第１
の絶縁膜、 （４）は第１の電極、 （５）は第２の絶
縁膜、（６）はスルーホール、（７）は第２の電極であ
る。Figure 1 is a cross-sectional view explaining the multilayer wiring structure of a semiconductor integrated circuit, Figures 2 (a), (b), and (C) are top views explaining the shape of conventional through holes, and Figures 3 (a) and (b). )(C) is a top view illustrating the shape of a through hole according to the present invention, and FIG. 4 is a top view illustrating a multilayer wiring structure of a semiconductor integrated circuit according to the present invention. (1) is the semiconductor substrate, (2) is the element, (3) is the first
(4) is the first electrode, (5) is the second insulating film, (6) is the through hole, and (7) is the second electrode.
Claims (1)
ｂ） 該半導体基板に形成された複数の素子と、 Ｃ） 前記基板の一主面を被覆する第１の絶縁膜と、 ｄ） 前記素子の所望の領域に接触し且つ前記第１の絶
縁膜上を延在される第１の電極と、 ｅ） 前記第１の絶縁膜及び第１の電極を被慢する第２
の絶縁膜と、 ｆ） 前記第１の電極上の第２の絶縁膜に周辺が凹凸を
有するスルーホールを設は該スルーホールを介して前記
第１の電極と接触し前記第２の絶縁膜上を延在される第
２の電極と、 を具備することを特徴とする半導体集積回路の多層配線
構造。[Claims] (118”) A semiconductor substrate having at least one principal surface;
b) a plurality of elements formed on the semiconductor substrate; C) a first insulating film covering one main surface of the substrate; and d) the first insulating film in contact with a desired region of the element. e) a second electrode extending over the first insulating film and the first electrode;
f) a through hole having an uneven periphery is provided in the second insulating film on the first electrode, and the second insulating film contacts the first electrode through the through hole; A multilayer wiring structure for a semiconductor integrated circuit, comprising: a second electrode extending thereover; and a second electrode extending thereover.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18806883A JPS6079748A (en) | 1983-10-06 | 1983-10-06 | Multilayer interconnection structure for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18806883A JPS6079748A (en) | 1983-10-06 | 1983-10-06 | Multilayer interconnection structure for semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6079748A true JPS6079748A (en) | 1985-05-07 |
Family
ID=16217141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18806883A Pending JPS6079748A (en) | 1983-10-06 | 1983-10-06 | Multilayer interconnection structure for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6079748A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6242244U (en) * | 1985-09-03 | 1987-03-13 | ||
| JPH022147A (en) * | 1988-06-15 | 1990-01-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| US4941034A (en) * | 1985-10-22 | 1990-07-10 | Siemens Aktiengesellschaft | Integrated semiconductor circuit |
| JPH02219420A (en) * | 1989-02-16 | 1990-09-03 | Nec Corp | Power circuit |
| JPH0541455A (en) * | 1990-12-28 | 1993-02-19 | Kawasaki Steel Corp | Semiconductor integrated circuit and its interlayer connection method |
-
1983
- 1983-10-06 JP JP18806883A patent/JPS6079748A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6242244U (en) * | 1985-09-03 | 1987-03-13 | ||
| JPH0546274Y2 (en) * | 1985-09-03 | 1993-12-03 | ||
| US4941034A (en) * | 1985-10-22 | 1990-07-10 | Siemens Aktiengesellschaft | Integrated semiconductor circuit |
| JPH022147A (en) * | 1988-06-15 | 1990-01-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH02219420A (en) * | 1989-02-16 | 1990-09-03 | Nec Corp | Power circuit |
| JPH0541455A (en) * | 1990-12-28 | 1993-02-19 | Kawasaki Steel Corp | Semiconductor integrated circuit and its interlayer connection method |
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