JPS6248892B2 - - Google Patents
Info
- Publication number
- JPS6248892B2 JPS6248892B2 JP54095012A JP9501279A JPS6248892B2 JP S6248892 B2 JPS6248892 B2 JP S6248892B2 JP 54095012 A JP54095012 A JP 54095012A JP 9501279 A JP9501279 A JP 9501279A JP S6248892 B2 JPS6248892 B2 JP S6248892B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- film
- insulating film
- bonding
- resin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000011347 resin Substances 0.000 description 40
- 229920005989 resin Polymers 0.000 description 40
- 239000010410 layer Substances 0.000 description 9
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 230000007547 defect Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- SDQJTWBNWQABLE-UHFFFAOYSA-N 1h-quinazoline-2,4-dione Chemical compound C1=CC=C2C(=O)NC(=O)NC2=C1 SDQJTWBNWQABLE-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000000284 resting effect Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 この発明は半導体装置に関する。[Detailed description of the invention] The present invention relates to a semiconductor device.
IC、LBI等の半導体集積回路は一般に半導体基
板（チツプ）の一主面に拡散接合を有する回路素
子を形成し、基板表面絶縁膜上に各素子と接続す
る１層又は多層のアルミニウム配線を配設してそ
の各端子をワイヤボンデイング用パツドとして露
出させ、バツド周辺にはパツシベーシヨン膜とし
て絶縁膜で被覆している。この絶縁膜には一般に
耐熱性が高く、表面平坦性のある有機樹脂のポリ
イミド系樹脂が使用されている。この種の樹脂パ
ツシベーシヨンを用いた従来の配線端子の構造は
第１図に示すようにSi基板１の表面絶縁膜２，３
上に第１のAl膜（配線）４を形成し、その周辺
を覆う第１の樹脂膜５を形成し、第１の樹脂膜の
窓穴周辺に重なるように第２のAl膜（パツド）
６を形成し、第２のAl膜６の周辺を覆う第２の
樹脂膜７を形成したものである。しかしこのよう
なボンデイングパツド構造ではパツド周縁部が膜
厚1.5μｍの樹脂膜と膜厚0.9μｍのAl膜とがそれ
ぞれ二重になつて形成されているためそこだけ異
常に突出し、LSIのボンダビリテイ不良が発生し
易い。すなわち、第１図に示すようにボンデイン
グの際にAuボール８やAlワイヤがパツド周縁部
に乗り上げた場合、２層の樹脂膜とAl膜の厚み
が大きいため接合部（Al面）にとどきにくいこ
とと、樹脂膜がいくらか柔軟性をもつためにボン
デイングエネルギーがそこに吸収されること、あ
るいはガスが発生することによる。 Semiconductor integrated circuits such as ICs and LBIs generally have circuit elements with diffusion bonding formed on one main surface of a semiconductor substrate (chip), and one or multiple layers of aluminum wiring connected to each element on an insulating film on the substrate surface. Each terminal is exposed as a pad for wire bonding, and the periphery of the pad is covered with an insulating film as a passivation film. This insulating film is generally made of polyimide resin, which is an organic resin with high heat resistance and surface flatness. The structure of a conventional wiring terminal using this type of resin passivation is as shown in FIG.
A first Al film (wiring) 4 is formed on top, a first resin film 5 is formed to cover the periphery thereof, and a second Al film (pad) is formed so as to overlap around the window hole of the first resin film.
6 is formed, and a second resin film 7 covering the periphery of the second Al film 6 is formed. However, in this type of bonding pad structure, the peripheral edge of the pad is formed by doubling the resin film with a thickness of 1.5 μm and the Al film with a thickness of 0.9 μm, so it protrudes abnormally in that area, which may affect the bondability of the LSI. Defects are likely to occur. In other words, as shown in Figure 1, if the Au ball 8 or the Al wire rides on the peripheral edge of the pad during bonding, it will be difficult for it to reach the bonding area (Al surface) because the two layers of resin film and Al film are thick. This is because the resin film has some flexibility, so bonding energy is absorbed there, or gas is generated.
本発明は上記した従来技術の欠点を取除くため
になされたものである。したがつて本発明の目的
はボンデイングパツド周縁部を平坦化してワイヤ
ボンデイング不良をなくすことにある。 The present invention has been made to eliminate the drawbacks of the prior art described above. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to flatten the peripheral edge of a bonding pad to eliminate wire bonding defects.
以下、本発明の好適な実施例を用いて本発明を
具体的に詳述する。 Hereinafter, the present invention will be specifically described in detail using preferred embodiments of the present invention.
第２図ａ，ｂは本発明によるボンデイングパツ
ドの一実施例を示す。同図において１はSi基板、
２は熱酸化によるSiO2膜（膜厚0.8μｍ）、３は
PSG（リン・シリケート・ガラス）膜（膜厚0.6
μｍ）、４は配線端子となる第１のAl膜でやや正
方形状をなしその膜厚は0.9μｍ、縦横寸法をＤ
とする。６は表面がボンデイング面となる第２の
Al配線でその膜厚を0.9μｍ、縦横寸法（最大寸
法）をＣとする。５は第１の有機樹脂膜でその膜
厚は1.5μｍで正方形の窓穴の縦横の寸法をＡと
する。７は第２の有機樹脂膜でその膜厚を1.5μ
ｍ、窓穴の縦横寸法をＢとする。なお、上記有機
樹脂膜５，７としてはポリイミド・イソインド
ロ・キナゾリンジオンからなる膜が用いられてい
る。上記Al配線の寸法をＣ，Ｄ樹脂膜の窓穴の
寸法Ａ，Ｂは少なくともボンダのキヤビラリの水
平移動方向Ｘ，Ｙ，Y′の三方向について下式：
Ａ＞Ｃ＞Ｂ＞Ｄ
を満足するように形成する。すなわち、樹脂膜
５は、Al４及びAl６のいずれの上にも載らない
ようにする。Al６がAl４より大きくされるた
め、ボンデイングパツドの縁の部分はAl６のみ
からなつている。第２図に示した実施例では、前
記Al６のみからなる縁の部分に樹脂膜７のみが
載るように形成している。 Figures 2a and 2b show an embodiment of a bonding pad according to the invention. In the same figure, 1 is a Si substrate,
2 is SiO 2 film (film thickness 0.8 μm) by thermal oxidation, 3 is
PSG (phosphorus silicate glass) film (thickness 0.6
μm), 4 is the first Al film that will serve as the wiring terminal, which has a slightly square shape, the film thickness is 0.9 μm, and the vertical and horizontal dimensions are D.
shall be. 6 is the second surface whose surface is the bonding surface.
The thickness of the Al wiring is 0.9 μm, and the vertical and horizontal dimensions (maximum dimensions) are C. 5 is a first organic resin film having a thickness of 1.5 μm, and the vertical and horizontal dimensions of the square window hole are A. 7 is the second organic resin film with a thickness of 1.5μ
m, and the vertical and horizontal dimensions of the window hole are B. Incidentally, as the organic resin films 5 and 7, films made of polyimide, isoindolo, and quinazolinedione are used. The dimensions of the Al wiring above are C and D, and the dimensions A and B of the window holes in the resin film satisfy the following formula: A>C>B>D at least in the three directions of horizontal movement of the bonder cavity, X, Y, and Y'. Form it so that it does. That is, the resin film 5 is made not to rest on either Al4 or Al6. Since Al6 is made larger than Al4, the edge portion of the bonding pad is made only of Al6. In the embodiment shown in FIG. 2, only the resin film 7 is placed on the edge portion made only of Al6.
以上のように、ボンデイングパツドの縁の部分
に樹脂膜５が載らないように形成していることに
より、ボンデイングパツドの縁部の突出が低減さ
れて平担化されるので、ボンダビリテイを向上す
ることができる。 As described above, by forming the resin film 5 so that it does not rest on the edge of the bonding pad, the protrusion of the edge of the bonding pad is reduced and the bonding pad is made flat, thereby improving bondability. can do.
また、Al６をAl４より大きくして樹脂膜７の
下に入り込ませていることにより、Al４とAl６
の重なり、Al６と樹脂膜７の重なり、樹脂膜５
と樹脂膜７の重なりというように、２層ずつの重
なりとなり、基板上全体の平担化を図ることがで
きる。 Also, by making Al6 larger than Al4 and entering under the resin film 7, Al4 and Al6
overlap, overlap of Al6 and resin film 7, resin film 5
The resin film 7 and the resin film 7 overlap each other, so that the entire substrate can be made flat.
なお、本実施例によれば、従来、樹脂膜７の上
とAl６の主面の相対高さｈが4.2μｍであつたの
に対し、本発明の場合相対高さh0.6〜1.2μｍと
少くなり、ボンデイング失敗の確率を大幅に減少
させることができた。なお、在来のリニアICの
場合のように、第1Al４の膜厚を1.7μｍ、第2Al
６の膜厚を3.5μｍとするとき樹脂膜７の上面と
の相対高さｈの差はさらに少なくなり、ボンデイ
ング不良防止効果はさらに大である。 According to this embodiment, while the relative height h between the top of the resin film 7 and the main surface of the Al6 was 4.2 μm in the past, in the present invention, the relative height h was 0.6 to 1.2 μm. This greatly reduced the probability of bonding failure. Note that, as in the case of conventional linear ICs, the film thickness of the first Al4 is 1.7 μm, and the thickness of the second Al4 is 1.7 μm.
When the film thickness of resin film 6 is set to 3.5 μm, the difference in relative height h with respect to the upper surface of resin film 7 becomes even smaller, and the effect of preventing bonding defects is even greater.
第３図は、本発明の他の実施例であつて、各構
成部の記号番号は第２図のそれと同じ記号番号で
示してある。 FIG. 3 shows another embodiment of the present invention, in which the symbol numbers of each component are the same as those in FIG. 2.
本実施例では、第３図に示すように、Alの寸
法Ｃ，Ｄと樹脂膜５，７の窓穴の寸法Ａ，Ｂは下
記：
Ａ＞Ｂ＞Ｃ＞Ｄ
を満足するように形成する。 In this example, as shown in FIG. 3, the dimensions C and D of Al and the dimensions A and B of the window holes in the resin films 5 and 7 are formed so as to satisfy the following: A>B>C>D. .
すなわち、樹脂膜５のみならず樹脂膜７もボン
デイングパツド上に載らないようにする。これに
より、ボンデイングパツド上に突出する部分が全
くなくなるので平担性が向上し、ボンダビリテイ
が向上する。また、Al６をAl４より大きくした
ことにより、ボンデイングパツドの周縁部分が
Al６一層のみとなるので、ボンデイングパツド
と絶縁膜３との間の段差も小さくなつている。ま
た、Ａ＞Ｂとしていることにより、ボンデイング
パツドの縁部に隣接した部分では樹脂膜７のみと
なつているため、これと絶縁膜３との間の段差も
少くなつている。 That is, not only the resin film 5 but also the resin film 7 is prevented from being placed on the bonding pad. This eliminates any protruding portion above the bonding pad, improving flatness and bondability. Also, by making Al6 larger than Al4, the peripheral edge of the bonding pad
Since only one layer of Al6 is used, the difference in level between the bonding pad and the insulating film 3 is also reduced. Further, by setting A>B, only the resin film 7 is present in the portion adjacent to the edge of the bonding pad, and the level difference between this and the insulating film 3 is also reduced.
なお、樹脂膜７と絶縁膜（PSG）３の選択エツ
チング法により、絶縁膜３の樹脂膜５，７及び
Al４，６から露出している部分が損われること
はない。第４図は、本発明の前記と異る他の実施
例であつて、ボンデイングパツドをAl４のみで
構成した実施例である。ボンデイングパツドであ
るAl４の寸法Ｄ、樹脂膜５，７のそれぞれの窓
穴の寸法Ａ，Ｂは、
Ａ＞Ｄ＞Ｂ
を満足するように形成する。 Note that by selectively etching the resin film 7 and the insulating film (PSG) 3, the resin films 5, 7 and the insulating film 3 are etched.
The parts exposed from Al4 and Al6 are not damaged. FIG. 4 shows another embodiment of the present invention different from the above, in which the bonding pad is made of only Al4. The dimension D of Al4, which is the bonding pad, and the dimensions A and B of the respective window holes in the resin films 5 and 7 are formed so as to satisfy A>D>B.
すなわち、Al４上に樹脂膜７のみが載るよう
にしている。このように、本発明によれば、基板
上１上にAl４，Al６、樹脂膜５，７を有する半
導体装置において、ボンデイングパツドをAl４
のみで構成した場合も、そのボンデイングパツド
の縁部の突出が小さくなり、平担性が良くなるの
で、ボンダビリテイを向上することができる。 That is, only the resin film 7 is placed on the Al4. As described above, according to the present invention, in a semiconductor device having Al4, Al6 and resin films 5 and 7 on the substrate 1, the bonding pad is
Even in the case where the bonding pad is made of only a single piece, the protrusion of the edge of the bonding pad is reduced and the flatness is improved, so that bondability can be improved.
なお、樹脂膜７と絶縁膜（PSG）３の間の選択
エツチング性により、
Ａ＞Ｂ＞Ｄ
となるようにしてもよい。 Note that depending on the selective etching properties between the resin film 7 and the insulating film (PSG) 3, the relationship A>B>D may be satisfied.
すなわち、樹脂膜５，７の双方がボンデイング
パツドAl４上に載らないようにしてもよい。こ
れにより、ボンデイングパツド上に全く突出部が
なくなるので、ボンダビリテイを向上することが
できる。また、ボンデイングパツドがAl４のみ
からなるので、ボンデイングパツドと絶縁膜３の
間の段差が小さくなる。 That is, both resin films 5 and 7 may not be placed on the bonding pad Al4. This eliminates any protrusions on the bonding pad, thereby improving bondability. Furthermore, since the bonding pad is made of only Al4, the difference in level between the bonding pad and the insulating film 3 is reduced.
第５図は、本発明の前記と異る他の実施例であ
つて、CMOS（相補形MOS）半導体装置に適用
したものである。ボンデイングパツドを構成する
Al４，Al６の下敷層として、SiO2膜２とPSG膜
３の間にMOSのゲート電極と同層のポリSi層８
を埋設している。ポリSi膜８の膜厚を0.4μｍ、
縦横の寸法をＥとしたとき、第２のAl６の寸法
Ｃ（最大寸法）、樹脂膜５，７の窓穴のそれぞれ
の寸法Ａ，Ｂの間に、
Ａ＞Ｃ＞Ｂ＞Ｅ
が成り立つようにする。 FIG. 5 shows another embodiment of the present invention different from the above, which is applied to a CMOS (complementary MOS) semiconductor device. Configure the bonding pad
A poly-Si layer 8, which is the same layer as the MOS gate electrode, is placed between the SiO 2 film 2 and the PSG film 3 as an underlying layer for Al4 and Al6.
is buried. The thickness of the poly-Si film 8 is 0.4 μm,
When the vertical and horizontal dimensions are E, A>C>B>E should hold between the dimension C (maximum dimension) of the second Al6 and the respective dimensions A and B of the window holes in the resin films 5 and 7. Make it.
すなわち、樹脂膜５がボンデイングパツドの縁
に載らないようにして、ボンデイングパツドの縁
部の突出を低減し平担化して、ボンダビリテイを
向上している。また、ボンデイングパツドがポリ
Si層８によつて下から押し上げられていることに
より、Al６と樹脂膜７との間の高低差が少くな
るので、ボンデイングパツドの縁部の突出が小さ
くなり、ボンダビリテイを向上することができ
る。樹脂膜７の上面とAl６主面の相対高さｈ
が、従来の場合ｈ＝4.2μｍであつたのが、この
実施例の場合、ボンデイングパツド近傍部でｈ＝
（＋）0.7μｍ、ボンデイングパツド遠隔部でｈ＝
（−）0.8μｍとなり、ボンデイング失敗確率が減
少する。 That is, by preventing the resin film 5 from resting on the edge of the bonding pad, the protrusion of the edge of the bonding pad is reduced and flattened, thereby improving bondability. Also, the bonding pad is poly
Being pushed up from below by the Si layer 8 reduces the height difference between the Al 6 and the resin film 7, which reduces the protrusion of the edge of the bonding pad and improves bondability. . Relative height h between the upper surface of the resin film 7 and the main surface of Al6
However, in the case of this embodiment, h = 4.2 μm in the conventional case, but h = 4.2 μm in the vicinity of the bonding pad.
(+)0.7μm, h= at the remote part of the bonding pad
(-) 0.8 μm, and the probability of bonding failure decreases.
第６図は、本発明の前記と異る他の実施例であ
つて、フイールドSiO2膜９をボンデイングパツ
ドの下以外の部分から充分に遠くまで取り除くこ
とにより、ボンデイングパツドの下にフイールド
SiO2膜９からなる下地膜を設けたものである。
このフイールドSiO2膜９の寸法をＥとした場
合、Al６、樹脂膜５，７の窓穴の寸法の関係は
前記第５図に示した実施例と同様にする。これに
より、第５図に示した実施例と同様の効果を得る
ことができるとともに、フイールドSiO2膜９の
縁の部分がなだらかなことにより、その上のボン
デイングパツドの縁の部分の傾斜をなだらかにす
ることができる。 FIG. 6 shows another embodiment of the present invention, in which the field SiO 2 film 9 is removed sufficiently far from the part other than under the bonding pad to form a field under the bonding pad.
A base film made of a SiO 2 film 9 is provided.
When the dimensions of this field SiO 2 film 9 are E, the relationship between the dimensions of the window holes in the Al 6 and resin films 5 and 7 is the same as in the embodiment shown in FIG. 5 above. As a result, the same effect as the embodiment shown in FIG. 5 can be obtained, and since the edge portion of the field SiO 2 film 9 is gentle, the slope of the edge portion of the bonding pad above it can be reduced. It can be made gentle.
第７図は、本発明の前記と異る他の実施例であ
つて、Si基板１の表面のボンデイングパツドの周
辺に例えばエツチングを施して凹部１０を形成し
て、相対的に突出部を形成することにより、ボン
デイングパツドを押し上げるようにしたものであ
る。第７図と、第５図及び第６図を比較すると分
るように、凹部１０の間の突出部の寸法をＥとし
たとき、これとAl６、樹脂膜５，７の窓穴の寸
法の関係は、第５図及び第６図に示した実施例と
同様にしている。これにより、第５図又は第６図
の実施例と同様の効果が得られる。 FIG. 7 shows another embodiment of the present invention different from the above, in which a concave portion 10 is formed by etching, for example, around a bonding pad on the surface of a Si substrate 1, and a relatively protruding portion is formed. By forming this, the bonding pad is pushed up. As can be seen by comparing FIG. 7 with FIGS. 5 and 6, when the size of the protrusion between the recesses 10 is E, this is the same as the size of the window holes in the Al6 and resin films 5 and 7. The relationship is the same as in the embodiment shown in FIGS. 5 and 6. As a result, the same effect as the embodiment shown in FIG. 5 or 6 can be obtained.
以上、説明したように、本発明によれば、前記
基板１上にボンデイングパツド電極を設け、該ボ
ンデイングパツド電極を覆う第１絶縁膜を設け、
該第１絶縁膜の前記ボンデイングパツド電極の上
の部分を除去して第１の窓を設け、該第１の窓か
ら露出するボンデイングパツド電極及び第１絶縁
膜の上に第２絶縁膜を設け、該第２絶縁膜の前記
ボンデイングパツド電極の上の部分を除去して第
２の窓を設けた半導体装置において、前記第１の
窓の径を前記第２の窓の径及びボンデイングパツ
ド電極の径より大きくしたので、ボンデイングパ
ツドの縁部の突出が低減されて平担になり、ボン
ダビリテイを向上することができる。 As described above, according to the present invention, a bonding pad electrode is provided on the substrate 1, a first insulating film covering the bonding pad electrode is provided,
A first window is provided by removing a portion of the first insulating film above the bonding pad electrode, and a second insulating film is formed on the bonding pad electrode and the first insulating film exposed through the first window. In the semiconductor device in which a second window is provided by removing a portion of the second insulating film above the bonding pad electrode, the diameter of the first window is set to the diameter of the second window and the bonding pad electrode. Since the diameter of the bonding pad is larger than that of the pad electrode, the protrusion of the edge of the bonding pad is reduced and becomes flat, thereby improving bondability.
本発明は、特に、上記絶縁膜５を多層配線層の
ための層間絶縁膜として使用する場合に有効であ
る。すなわち、上記第1Al配線４と上記第2Al配
線６とを多層配線層として使用する場合、それら
の間を絶縁するための層間絶縁膜５を必要とする
が、この場合に上記本発明をパツド形成部に適用
すれば、上述のように、ボンデイング不良を防止
できる。 The present invention is particularly effective when the insulating film 5 is used as an interlayer insulating film for multilayer wiring layers. That is, when the first Al wiring 4 and the second Al wiring 6 are used as a multilayer wiring layer, an interlayer insulating film 5 is required to insulate between them. If applied to the area, bonding defects can be prevented as described above.
本発明は上述したものに限らず、CVDSiO2，
PSGなどの無機絶縁物からなる層間絶縁膜、
An，Ｗ，Mo等の金属材料からなるボンデイング
パツド電極を有するものなど種々の態様の半導体
装置に適用できるものである。 The present invention is not limited to the above-mentioned, but includes CVDSiO 2 ,
Interlayer insulation film made of inorganic insulators such as PSG,
It can be applied to various types of semiconductor devices, including those having bonding pad electrodes made of metal materials such as An, W, and Mo.
第１図は従来のボンデイングパツド構造の例を
示す断面図である。第２図ａ，ｂは本発明による
ボンデイングパツドの一実施例を示し、ａは平面
図、ｂはａのＡ−A′視断面図、第３図ａ，ｂは
本発明によるボンデイングパツドの他の実施例を
示し、ａは平面図、ｂはａのＡ−A′視断面図、
第４図、第５図、第６図及び第７図は本発明によ
るボンデイングパツドの他の各実施例をそれぞれ
に示す断面図である。
１……Si基板、２……SiO2膜、３……PSG膜、
４……第1Al配線（配線端子部）、５……第1PII
膜、６……第2Al配線（パツド部）、７……第2PII
膜、８……ポリSi層、９……フイルドSiO2膜、１
０……凹部。
FIG. 1 is a sectional view showing an example of a conventional bonding pad structure. Figures 2a and b show an embodiment of the bonding pad according to the present invention, where a is a plan view, b is a sectional view taken along line A-A' of a, and Figures 3a and b are the bonding pads according to the present invention. shows another example, where a is a plan view, b is a sectional view taken along line A-A' of a,
FIGS. 4, 5, 6 and 7 are sectional views showing other embodiments of the bonding pad according to the present invention. 1...Si substrate, 2...SiO 2 film, 3...PSG film,
4...1st Al wiring (wiring terminal part), 5...1st PII
Film, 6...2nd Al wiring (pad part), 7...2nd PII
Film, 8... Poly Si layer, 9... Field SiO 2 film, 1
0... Concavity.
Claims (1)
ボンデイングパツド電極を覆う第１絶縁膜を設
け、該第１絶縁膜の前記ボンデイングパツド電極
の上の部分を除去して第１の窓を設け、該第１の
窓から露出するボンデイングパツド電極及び前記
第１絶縁膜の上に第２絶縁膜を設け、該第２絶縁
膜の前記ボンデイングパツド電極の上の部分を除
去して第２の窓を設けた半導体装置において、前
記第１の窓の寸法を前記第２の窓の寸法及びボン
デイングパツド電極の寸法より大きくしたことを
特徴とする半導体装置。1. A bonding pad electrode is provided on a substrate, a first insulating film is provided to cover the bonding pad electrode, and a first window is provided by removing a portion of the first insulating film above the bonding pad electrode. , a second insulating film is provided on the bonding pad electrode and the first insulating film exposed through the first window, and a portion of the second insulating film above the bonding pad electrode is removed to form a second insulating film. 1. A semiconductor device provided with a window, characterized in that the dimensions of the first window are larger than the dimensions of the second window and the dimensions of the bonding pad electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9501279A JPS5619639A (en) | 1979-07-27 | 1979-07-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9501279A JPS5619639A (en) | 1979-07-27 | 1979-07-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5619639A JPS5619639A (en) | 1981-02-24 |
| JPS6248892B2 true JPS6248892B2 (en) | 1987-10-16 |
Family
ID=14126046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9501279A Granted JPS5619639A (en) | 1979-07-27 | 1979-07-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5619639A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02113522U (en) * | 1989-02-28 | 1990-09-11 |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56105644A (en) * | 1980-01-25 | 1981-08-22 | Mitsubishi Electric Corp | Semiconductor ic device |
| JPS57150947U (en) * | 1981-03-16 | 1982-09-22 | ||
| JPS57211248A (en) * | 1981-06-22 | 1982-12-25 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS5840835A (en) * | 1981-09-03 | 1983-03-09 | Nec Corp | Semiconductor device |
| JPS6035525A (en) * | 1983-08-08 | 1985-02-23 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
| JPS6072253A (en) * | 1983-09-28 | 1985-04-24 | Oki Electric Ind Co Ltd | Semiconductor device |
| JPS60257550A (en) * | 1984-06-04 | 1985-12-19 | Mitsubishi Electric Corp | Semiconductor device |
| JPH01305531A (en) * | 1988-06-03 | 1989-12-08 | Nec Corp | Semiconductor device having improved bonding pad |
| JP2770390B2 (en) * | 1989-03-24 | 1998-07-02 | 日本電気株式会社 | Semiconductor device |
| US5227812A (en) * | 1990-02-26 | 1993-07-13 | Canon Kabushiki Kaisha | Liquid jet recording head with bump connector wiring |
| ES2082129T3 (en) * | 1990-02-26 | 1996-03-16 | Canon Kk | PRINTING DEVICE WITH MAGNETIC HEAD THAT HAS A WIRING SUBSTRATE. |
| CN102282659B (en) | 2009-02-04 | 2013-11-20 | 松下电器产业株式会社 | Semiconductor substrate structure and semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5317165B2 (en) * | 1974-03-12 | 1978-06-06 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5317165U (en) * | 1976-07-23 | 1978-02-14 |
-
1979
- 1979-07-27 JP JP9501279A patent/JPS5619639A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5317165B2 (en) * | 1974-03-12 | 1978-06-06 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02113522U (en) * | 1989-02-28 | 1990-09-11 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5619639A (en) | 1981-02-24 |
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