JPH01305531A - Semiconductor device having improved bonding pad - Google Patents
Semiconductor device having improved bonding padInfo
- Publication number
- JPH01305531A JPH01305531A JP13772888A JP13772888A JPH01305531A JP H01305531 A JPH01305531 A JP H01305531A JP 13772888 A JP13772888 A JP 13772888A JP 13772888 A JP13772888 A JP 13772888A JP H01305531 A JPH01305531 A JP H01305531A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- thickness
- bonding
- insulating layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000008021 deposition Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子とボデングパッドの構造に関し、特
にＡｐ（アルミニウム）線ワイヤーボンデンダ時にボン
デングパッド部のＡＡ （アルミニウム）がパッド部以
外にあふれ出ることを防止するためのボンデングパッド
の構造に関する。Detailed Description of the Invention [Industrial Field of Application] The present invention relates to the structure of a semiconductor element and a bonding pad, and in particular, to the structure of a semiconductor element and a bonding pad, and in particular, when bonding an Ap (aluminum) wire, AA (aluminum) in a bonding pad portion overflows to areas other than the pad portion. This invention relates to the structure of a bonding pad to prevent it from coming out.
従来のボンデングパッドの構造について、第４図、第５
図を用いて説明する。半導体素子１は公知の半導体素子
製造技術により形成される。Ａβ層６は比較的電流容量
を必要とするためへρ厚膜が１．５μｍ〜２．５μｍ形
成され、ボンデング部以外を絶縁層７で覆う構造となっ
ていた。The structure of conventional bonding pads is shown in Figures 4 and 5.
This will be explained using figures. The semiconductor element 1 is formed by a known semiconductor element manufacturing technique. Since the Aβ layer 6 requires a relatively high current capacity, a ρ thick film of 1.5 μm to 2.5 μm was formed, and the structure was such that the area other than the bonding portion was covered with the insulating layer 7.
上述した従来のボンデングパッド構造は、ボンデング部
のＡｊ２膜厚が比較的厚く、ＡＩ！線ワビワイヤーボン
デング時ンデング部がズして絶縁層部にかかるとパッド
部分以外にあふれ出し、隣接のパッドやスクライブ縁端
に達してショートする危険があるため、パッド間隔及び
パッドとスクライブ縁端までの距離を大きくしなければ
ならないという欠点がある。In the conventional bonding pad structure described above, the Aj2 film thickness of the bonding part is relatively thick, and the AI! When wire bonding, if the bent part slips and touches the insulating layer, it may overflow outside the pad area and reach the adjacent pad or edge of the scribe, causing a short circuit. The disadvantage is that the distance must be increased.
上述した従来のボンデングパッド構造に対し、本発明は
Ａｊ２線ワイヤーボンデンダ時にパッド部のＡｆｆｌが
パッド部分以外にあふれ出ないという相違点を有する。The present invention differs from the conventional bonding pad structure described above in that the Affl of the pad portion does not overflow outside the pad portion during AJ two-wire wire bonding.
本発明のボンデングパッドの構造は、ボンデングパッド
の少なくとも３辺お周辺部のＡｌ膜厚をボンデングパッ
ド部の他の部分より薄く形成することを有している。The structure of the bonding pad of the present invention includes forming an Al film thinner in the peripheral portions of at least three sides of the bonding pad than in other portions of the bonding pad portion.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の正面図であり、第２図は第
１図の縦断面図である。第１図及び第２図において、半
導体素子１は公知の半導体技術によって形成されている
。第１Ａｐ層２は蒸着、スパッタ法等により０．８μｍ
〜１．３μｍの厚さで形成される。第１絶縁層３は５ｉ
０２．Ｐ ＳｉＮ膜で約０．５μｍ〜１０μｍの厚さ
で形成される。FIG. 1 is a front view of one embodiment of the present invention, and FIG. 2 is a longitudinal sectional view of FIG. 1. In FIGS. 1 and 2, a semiconductor element 1 is formed using known semiconductor technology. The first Ap layer 2 has a thickness of 0.8 μm by vapor deposition, sputtering, etc.
It is formed with a thickness of ~1.3 μm. The first insulating layer 3 is 5i
02. The P SiN film is formed with a thickness of approximately 0.5 μm to 10 μm.
第２ＡＡ層４は第１Ａｌ層２と同様に同程度の膜厚で形
成される。第２絶縁層５は第１絶縁層３と同様の方法で
約１．０μｍ〜１．５μｍの膜厚でボンデングパッド部
以外を反覆する。The second AA layer 4 is formed to have the same thickness as the first Al layer 2. The second insulating layer 5 is formed by repeating the same method as the first insulating layer 3 to have a thickness of about 1.0 μm to 1.5 μm except for the bonding pad portion.
第３図は本発明の実施例２の正面図である。第１の絶縁
層３は隣接のパッド側とスクライブ縁端を覆うだけで内
部配線側は反覆しないようにする。FIG. 3 is a front view of Embodiment 2 of the present invention. The first insulating layer 3 only covers the adjacent pad side and the scribe edge, but does not cover the internal wiring side.
この実施例では内部配線側に第１の絶縁層を設けないた
め、ボンデング時が平坦でありボンデング性が向上する
とともにポンチングパッドの縮少化が図れる利点がある
。In this embodiment, since the first insulating layer is not provided on the internal wiring side, there is an advantage that the surface is flat during bonding, improving bonding performance and reducing the number of punching pads.
以上説明したように本発明は、半導体素子のボンデング
パッドの周辺部をボンデングパッドの他の部分よりＡｆ
ｌ膜厚を薄く形成することにより、ボンデング時にボン
デングパッドのＡｌがボンデングパッド以外にあふれ出
すことを防止できるため、パッドとパッドの間隔及びパ
ッドとスクライブ縁端間の距離を小さくできる効果があ
る。As explained above, in the present invention, the periphery of the bonding pad of a semiconductor element is made Af higher than other parts of the bonding pad.
By forming a thin film, it is possible to prevent Al from the bonding pad from overflowing to areas other than the bonding pad during bonding, which has the effect of reducing the spacing between pads and the distance between the pads and the edge of the scribe. be.
第１図は本発明のボンデングパッドの構造の実施例１を
説明するための正面図、第２図は第１図の縦断面図、第
３図は実施例２を説明するための正面図、第４図は従来
のポンチングパッドの構造を説明するための正面図、第
５図は第４図の縦断面図である。
１・・・・・・半導体素子、２・・・・・・第１Ａβ層
、３・・・・・・第１絶縁層、４・・・・・・第２Ａ、
ｆ２層、訃・・・・・第２絶縁層、６・・・・・・Ａ４
層、７・・・・・・絶縁層。
代理人 弁理士 内 原 晋FIG. 1 is a front view for explaining Embodiment 1 of the structure of a bonding pad of the present invention, FIG. 2 is a longitudinal sectional view of FIG. 1, and FIG. 3 is a front view for explaining Embodiment 2. , FIG. 4 is a front view for explaining the structure of a conventional punching pad, and FIG. 5 is a longitudinal sectional view of FIG. 4. DESCRIPTION OF SYMBOLS 1... Semiconductor element, 2... First Aβ layer, 3... First insulating layer, 4... Second A,
f2 layer, 2nd insulating layer, 6...A4
Layer 7...Insulating layer. Agent Patent Attorney Susumu Uchihara
Claims (1)
デングパッドの少なくとも３辺の周辺部のＡｌ膜厚をボ
ンデングパッド部の他の部分より薄く形成したボンデン
グパッドを有する半導体装置。A semiconductor device having a structure of a bonding pad for a semiconductor element, which has a bonding pad in which the thickness of an Al film on the periphery of at least three sides of the bonding pad is thinner than on other parts of the bonding pad portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13772888A JPH01305531A (en) | 1988-06-03 | 1988-06-03 | Semiconductor device having improved bonding pad |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13772888A JPH01305531A (en) | 1988-06-03 | 1988-06-03 | Semiconductor device having improved bonding pad |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01305531A true JPH01305531A (en) | 1989-12-08 |
Family
ID=15205444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13772888A Pending JPH01305531A (en) | 1988-06-03 | 1988-06-03 | Semiconductor device having improved bonding pad |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01305531A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH045828A (en) * | 1990-04-23 | 1992-01-09 | Nec Corp | Semiconductor device |
| US5126819A (en) * | 1989-11-10 | 1992-06-30 | Kabushiki Kaisha Toshiba | Wiring pattern of semiconductor integrated circuit device |
| KR100596826B1 (en) * | 1999-12-30 | 2006-07-03 | 주식회사 하이닉스반도체 | A method for forming a pad of a semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5619639A (en) * | 1979-07-27 | 1981-02-24 | Hitachi Ltd | Semiconductor device |
| JPS6164147A (en) * | 1984-09-05 | 1986-04-02 | Nec Corp | Semiconductor device |
-
1988
- 1988-06-03 JP JP13772888A patent/JPH01305531A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5619639A (en) * | 1979-07-27 | 1981-02-24 | Hitachi Ltd | Semiconductor device |
| JPS6164147A (en) * | 1984-09-05 | 1986-04-02 | Nec Corp | Semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5126819A (en) * | 1989-11-10 | 1992-06-30 | Kabushiki Kaisha Toshiba | Wiring pattern of semiconductor integrated circuit device |
| US5523627A (en) * | 1989-11-10 | 1996-06-04 | Kabushiki Kaisha Toshiba | Wiring pattern of semiconductor integrated circuit device |
| USRE37059E1 (en) * | 1989-11-10 | 2001-02-20 | Kabushiki Kaisha Toshiba | Wiring pattern of semiconductor integrated circuit device |
| JPH045828A (en) * | 1990-04-23 | 1992-01-09 | Nec Corp | Semiconductor device |
| KR100596826B1 (en) * | 1999-12-30 | 2006-07-03 | 주식회사 하이닉스반도체 | A method for forming a pad of a semiconductor device |
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