JPH0529375A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0529375A JPH0529375A JP3206425A JP20642591A JPH0529375A JP H0529375 A JPH0529375 A JP H0529375A JP 3206425 A JP3206425 A JP 3206425A JP 20642591 A JP20642591 A JP 20642591A JP H0529375 A JPH0529375 A JP H0529375A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- semiconductor device
- wiring metal
- metal layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体装置、詳しく
は、ボンディングパッドの構造に特徴を有する半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device characterized by a bonding pad structure.
【０００２】[0002]
【従来の技術】従来の半導体装置のボンディングパッド
としては、例えば、図５に断面図を示すような構造のボ
ンディングパッドが知られている。この従来の半導体装
置Ｃにおいては、半導体基板２１の上に、ＳｉＯ2，Ｓ
ｉＮXなどからなる下地絶縁体層２２が形成されてい
る。この下地絶縁体層２２の上には、配線金属層２３が
配設され、さらに、配線金属層２３の上には、Ｓｉ
Ｏ2，ＳｉＮXなどからなる絶縁体層２４が積層されてい
る。そして、上記絶縁体層２４の一部は、エッチング等
の方法で取り除かれており、そこから配線金属層２３の
一部２３ａが露出し、この部分が素子の電極やワイヤな
どをボンディングするためのボンディングパッド２５と
なっている。2. Description of the Related Art As a conventional bonding pad for a semiconductor device, for example, a bonding pad having a structure shown in FIG. 5 is known. In this conventional semiconductor device C, on the semiconductor substrate 21, SiO 2 , S
A base insulator layer 22 made of iN x or the like is formed. A wiring metal layer 23 is provided on the underlying insulator layer 22, and a Si layer is formed on the wiring metal layer 23.
An insulator layer 24 made of O 2 , SiN x or the like is laminated. Then, a part of the insulator layer 24 is removed by a method such as etching, and a part 23a of the wiring metal layer 23 is exposed therefrom, and this part is used for bonding electrodes and wires of the element. It is the bonding pad 25.
【０００３】なお、従来例としては、上記の構造のもの
以外にも、下地絶縁体層２２を省略したものや、あるい
は、配線金属層２３のすぐ下に、オーミック電極やショ
ットキー電極（図示せず）などの素子の一部を配設した
ものなどがある。As a conventional example, in addition to the structure described above, a structure in which the underlying insulator layer 22 is omitted, or an ohmic electrode or a Schottky electrode (not shown) immediately below the wiring metal layer 23 is shown. There is a device in which a part of the element such as () is provided.
【０００４】[0004]
【発明が解決しようとする課題】しかし、前記従来の半
導体装置Ｃにおいては、ボンディングパッド（配線金属
層の露出部分）２５が、周囲の絶縁体層２４の表面より
低い位置にあり、凹状になっているため、レジストを用
いたリフトオフ工程や、ワックスを用いたウエハの研磨
工程などにおいて、ボンディングパッド２５の端部の角
などにレジストやワックスなどの残渣２６の堆積が生じ
やすく、ボンディングパッド２５とワイヤ（図示せず）
などとの間に残渣２６がはさまれると、ワイヤとボンデ
ィングパッド２５との間の抵抗値の増大や、ボンディン
グ強度の低下を引き起こし、製品としての半導体装置の
特性のばらつきや、特性不良を引き起こすという問題点
がある。However, in the conventional semiconductor device C, the bonding pad (exposed portion of the wiring metal layer) 25 is located lower than the surface of the surrounding insulating layer 24, and has a concave shape. Therefore, in a lift-off process using a resist, a wafer polishing process using a wax, and the like, a residue 26 such as a resist and a wax is likely to be deposited on the corners of the end portions of the bonding pad 25, and the bonding pad 25 and Wire (not shown)
If the residue 26 is sandwiched between the wire and the like, the resistance value between the wire and the bonding pad 25 increases, the bonding strength decreases, and the characteristics of the semiconductor device as a product are varied and the characteristics are defective. There is a problem.
【０００５】この発明は、上記問題点を解決するもので
あり、製造工程において、レジストやワックスなどの残
渣がたまりにくいボンディングパッドを有する半導体装
置を提供することを目的とする。The present invention solves the above problems, and an object of the present invention is to provide a semiconductor device having a bonding pad in which a residue such as a resist or wax is unlikely to accumulate in a manufacturing process.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に、この発明の半導体装置は、半導体基板上に配設さ
れ、絶縁体層で覆われた配線金属層の一部を、該絶縁体
層から露出させたボンディングパッドを有する半導体装
置であって、前記配線金属層の一部を凸状に成形し、該
凸状部の表面を前記絶縁体層から露出させるとともに、
該凸状部の表面を該配線金属層の他の部分を覆う絶縁体
層の表面より高い位置に配設してなるボンディングパッ
ドを有することを特徴とする。In order to achieve the above object, a semiconductor device of the present invention comprises a wiring metal layer disposed on a semiconductor substrate and covered with an insulating layer, wherein a portion of the wiring metal layer is covered with the insulating layer. A semiconductor device having a bonding pad exposed from a layer, wherein a part of the wiring metal layer is formed into a convex shape, and the surface of the convex portion is exposed from the insulator layer,
It is characterized in that it has a bonding pad formed by disposing the surface of the convex portion at a position higher than the surface of the insulator layer covering the other portion of the wiring metal layer.
【０００７】[0007]
【作用】配線金属層の凸状に形成された部分の表面が、
該配線金属層を覆う絶縁体層から突出しており、周囲の
絶縁体層の表面よりも高い位置にボンディングパッドが
配設されているため、レジストを用いたリフトオフ工程
や、ワックスを用いたウエハの研磨工程などを含む半導
体装置の製造工程において、ボンディングパッドにレジ
ストやワックスなどの残渣２６が堆積しにくくなり、ボ
ンディングパッドにワイヤなどを接続した場合に、ワイ
ヤなどとボンディングパッドとの間の抵抗値の増大やボ
ンディング強度の低下を引き起こしたりすることがな
く、特性不良の発生を防止して、信頼性の高い半導体装
置を得ることができる。[Function] The surface of the convex portion of the wiring metal layer is
Since the bonding pad is provided at a position higher than the surface of the surrounding insulating layer and protruding from the insulating layer covering the wiring metal layer, a lift-off process using a resist or a wafer using a wax is performed. In a semiconductor device manufacturing process including a polishing process and the like, residues 26 such as resist and wax are less likely to be deposited on the bonding pad, and when a wire or the like is connected to the bonding pad, the resistance value between the wire and the bonding pad is reduced. It is possible to obtain a highly reliable semiconductor device by preventing the occurrence of characteristic defects without causing an increase in the resistance and a decrease in the bonding strength.
【０００８】[0008]
【実施例】以下、この発明の実施例を図に基づいて説明
する。図１はこの発明の一実施例を示す半導体装置の断
面図であり、図２はその平面図である。図に示すよう
に、この実施例の半導体装置Ａにおいては、半導体基板
１の上に、ＳｉＯ2やＳｉＮXなどからなる下地絶縁体層
２が形成されており、下地絶縁体層２の上には、ボンデ
ィングパッド５の下地となる金属材料からなる台部７が
形成されている。また、上記下地絶縁体層２上には、台
部７を覆うように配線金属層３が配設されており、この
配線金属層３の、上記台部７を覆う部分３ａは、凸状に
なっている。そして、配線金属層３上には、ＳｉＯ2，
ＳｉＮXなどからなる絶縁体層４が積層されており、配
線金属３は絶縁体層４により覆われているが、凸状部３
ａ（の表面）は、絶縁体層４の表面より高い位置にあ
り、絶縁体層４から露出して、ボンディングパッド５を
形成している。Embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention, and FIG. 2 is a plan view thereof. As shown in the figure, in the semiconductor device A of this embodiment, the base insulator layer 2 made of SiO 2 or SiN x is formed on the semiconductor substrate 1, and the base insulator layer 2 is formed on the base insulator layer 2. Is formed with a base 7 made of a metal material as a base of the bonding pad 5. A wiring metal layer 3 is provided on the underlying insulator layer 2 so as to cover the base portion 7. The portion 3a of the wiring metal layer 3 that covers the base portion 7 has a convex shape. Is becoming Then, on the wiring metal layer 3, SiO 2 ,
The insulating layer 4 made of SiN x or the like is laminated, and the wiring metal 3 is covered with the insulating layer 4, but the convex portion 3
The surface (a) is higher than the surface of the insulating layer 4, and is exposed from the insulating layer 4 to form the bonding pad 5.
【０００９】次に、上記ボンディングパッド５の形成方
法について説明する。半導体装置の製造プロセスの一部
において、上記のような構造のボンディングパッドを形
成する場合、まず半導体基板１の上に、ＣＶＤなどの方
法により、ＳｉＯ2、ＳｉＮXなどからなる下地絶縁体層
２を形成し、その上にリフトオフ法により、ボンディン
グパッド５の下地となる金属材料からなる台部７を形成
し、さらに、リフトオフ法により、その上から所定のパ
ターンの配線金属層３を形成する。次いで、ＣＶＤ法な
どにより、配線金属層３の上から、ＳｉＯ2、ＳｉＮXな
どからなる絶縁体層４を積層して、配線金属層３を覆う
（図３）。それから、上記絶縁体層４の、配線金属層３
の凸状部３ａを覆う部分４ａをエッチング等の方法で取
り除き、配線金属層３の凸状部（の表面）３ａを絶縁体
層４から露出させることによりボンディングパッド５を
形成する（図１）。Next, a method of forming the bonding pad 5 will be described. When forming the bonding pad having the above structure in a part of the manufacturing process of the semiconductor device, first, the base insulating layer 2 made of SiO 2 , SiN x or the like is formed on the semiconductor substrate 1 by a method such as CVD. Is formed, the lift-off method is used to form the base 7 made of a metal material which is a base of the bonding pad 5, and the lift-off method is used to form the wiring metal layer 3 having a predetermined pattern thereon. Then, an insulating layer 4 made of SiO 2 , SiN x or the like is laminated on the wiring metal layer 3 by the CVD method or the like to cover the wiring metal layer 3 (FIG. 3). Then, the wiring metal layer 3 of the insulator layer 4
The portion 4a covering the convex portion 3a of is removed by a method such as etching, and the convex portion (the surface) 3a of the wiring metal layer 3 is exposed from the insulating layer 4 to form the bonding pad 5 (FIG. 1). .
【００１０】上述のようにして形成されたボンディング
パッド５（凸状部３ａ）は、配線金属層３を覆う絶縁体
層４から突出しており、周囲の絶縁体層４の表面よりも
高い位置にあるため、レジストを用いたリフトオフ工程
や、ワックスを用いたウエハの研磨工程などを含む半導
体装置の製造工程において、レジストやワックスなどの
残渣６が堆積したりせず（残渣６がボンディングパッド
５と絶縁体層４の段部に堆積することがあるが、この位
置にはワイヤなどがボンディングされることはなくボン
ディングに影響することはない）、ボンディングパッド
５にワイヤなどを接続した場合に、ワイヤとボンディン
グパッド５との間の抵抗値の増大やボンディング強度の
低下を引き起こしたりすることがなく、信頼性の高い半
導体装置を得ることができる。The bonding pad 5 (convex portion 3a) formed as described above projects from the insulating layer 4 covering the wiring metal layer 3 and is located at a position higher than the surface of the surrounding insulating layer 4. Therefore, in a semiconductor device manufacturing process including a lift-off process using a resist and a wafer polishing process using a wax, a residue 6 such as a resist or a wax is not deposited (the residue 6 is a bonding pad 5). Although it may be deposited on the stepped portion of the insulator layer 4, a wire or the like is not bonded at this position and does not affect the bonding.) When a wire or the like is connected to the bonding pad 5, It is possible to obtain a highly reliable semiconductor device without increasing the resistance value between the bonding pad 5 and the bonding pad 5 or lowering the bonding strength. Can.
【００１１】また、図４は、この発明の他の実施例を示
す断面図である。この実施例の半導体装置Ｂにおいて
は、半導体基板１１に、凸部１７を形成し、その上か
ら、上記実施例と同様の方法で、下地絶縁体層１２、配
線金属層１３を形成し、さらにその上から絶縁体層１４
を積層した後、上記絶縁体層１４の、配線金属層１３の
凸状部１３ａを覆う部分（図示せず）をエッチング等の
方法で取り除き、配線金属層１３の凸状部（の表面）１
３ａを絶縁体層１４から露出させることによりボンディ
ングパッド１５を形成している。FIG. 4 is a sectional view showing another embodiment of the present invention. In the semiconductor device B of this embodiment, the convex portion 17 is formed on the semiconductor substrate 11, and the underlying insulator layer 12 and the wiring metal layer 13 are formed on the convex portion 17 by the same method as in the above embodiment. Insulator layer 14 from above
After stacking, the portion (not shown) of the insulating layer 14 covering the convex portion 13a of the wiring metal layer 13 is removed by a method such as etching, and the convex portion (surface) 1 of the wiring metal layer 13 is removed.
The bonding pad 15 is formed by exposing 3a from the insulator layer 14.
【００１２】この実施例の半導体装置Ｂにおいては、半
導体基板１１に凸部１７を形成しているので、上記実施
例のように、ボンディングパッドの下地となる台部７
（図１，図３）を形成する必要がなく、従来例と比較し
て特に工程数を増やすことなしに、上記構造を有するボ
ンディングパッド１５を形成することが可能になる。In the semiconductor device B of this embodiment, since the convex portion 17 is formed on the semiconductor substrate 11, as in the above-described embodiment, the base portion 7 which is the base of the bonding pad is formed.
It is not necessary to form (FIGS. 1 and 3), and the bonding pad 15 having the above structure can be formed without increasing the number of steps compared with the conventional example.
【００１３】なお、この実施例の半導体装置Ｂにおいて
も、上記実施例の場合と同様に、ボンディングパッド１
５が、配線金属層１３を覆う絶縁体層１４から突出し、
周囲の絶縁体層１４の表面よりも高い位置にあるため、
上記実施例と同様に、半導体装置の製造工程において、
レジストやワックスなどの残渣が堆積しにくいという効
果を奏する。In the semiconductor device B of this embodiment, the bonding pad 1 is also used as in the case of the above embodiment.
5 protrudes from the insulator layer 14 that covers the wiring metal layer 13,
Since it is located higher than the surface of the surrounding insulator layer 14,
Similar to the above embodiment, in the manufacturing process of the semiconductor device,
This has the effect that residues such as resist and wax do not easily accumulate.
【００１４】上記の各実施例では、半導体基板の上に下
地絶縁体層２（図１），１２（図４）が形成された構造
の半導体装置Ａ，Ｂについて説明したが、この発明が適
用できる半導体装置の構造は、上記の構造に限られるも
のではなく、下地絶縁体層２，１２を省略したものや、
あるいは、配線金属層３，１３のすぐ下に、オーミック
電極やショットキー電極（図示せず）などの素子の一部
を配設した構造のものなどにも適用することが可能であ
る。In each of the above embodiments, the semiconductor devices A and B having the structure in which the base insulator layers 2 (FIG. 1) and 12 (FIG. 4) are formed on the semiconductor substrate have been described, but the present invention is applied. The structure of the semiconductor device that can be formed is not limited to the structure described above, and the base insulator layers 2 and 12 may be omitted.
Alternatively, it can be applied to a structure in which a part of an element such as an ohmic electrode or a Schottky electrode (not shown) is provided immediately below the wiring metal layers 3 and 13.
【００１５】[0015]
【発明の効果】上述のように、この発明の半導体装置
は、配線金属層の一部に凸状部を形成し、該凸状部の表
面を、配線金属層の他の部分を覆う絶縁体層の表面から
突出させることにより、周囲の絶縁体層表面より高い位
置にボンディングパッドを形成しているので、レジスト
を用いたリフトオフ工程や、ワックスを用いたウエハの
研磨工程などを含む半導体装置の製造工程において、レ
ジストやワックスなどの残渣が堆積することがなく、ボ
ンディングパッドにワイヤなどを接続した場合の、接続
部における抵抗の増大やボンディング強度の低下を防止
して、半導体装置の信頼性を向上させることができる。As described above, according to the semiconductor device of the present invention, the convex portion is formed on a part of the wiring metal layer, and the surface of the convex portion covers the other portion of the wiring metal layer. By protruding from the surface of the layer, the bonding pad is formed at a position higher than the surface of the surrounding insulating layer, so that a semiconductor device including a lift-off process using a resist, a wafer polishing process using a wax, etc. In the manufacturing process, residue such as resist and wax does not accumulate, and when a wire or the like is connected to the bonding pad, increase in resistance and decrease in bonding strength at the connection part are prevented, and reliability of the semiconductor device is improved. Can be improved.
【図１】この発明の一実施例にかかる半導体装置のボン
ディングパッドの構造を示す、図２のＩ−Ｉ線断面図で
ある。FIG. 1 is a sectional view taken along the line I-I of FIG. 2, showing a structure of a bonding pad of a semiconductor device according to an embodiment of the present invention.
【図２】この発明の一実施例にかかる半導体装置のボン
ディングパッドを示す平面図である。FIG. 2 is a plan view showing a bonding pad of a semiconductor device according to an embodiment of the present invention.
【図３】この発明の一実施例にかかる半導体装置のボン
ディングパッドの形成工程を示す断面図である。FIG. 3 is a sectional view showing a step of forming a bonding pad of a semiconductor device according to an embodiment of the present invention.
【図４】この発明の他の実施例にかかる半導体装置のボ
ンディングパッドの構造を示す断面図である。FIG. 4 is a sectional view showing a structure of a bonding pad of a semiconductor device according to another embodiment of the present invention.
【図５】従来の半導体装置のボンディングパッドの構造
を示す断面図である。FIG. 5 is a cross-sectional view showing a structure of a bonding pad of a conventional semiconductor device.
Ａ，Ｂ 半導体装置 １，１１ 半導体基板 ３，１３ 配線金属層 ３ａ，１３ａ 凸状部 ４，１４ 絶縁体層 ５，１５ ボンディングパッド（配線金属層の
凸状部）A, B Semiconductor device 1,11 Semiconductor substrate 3,13 Wiring metal layer 3a, 13a Convex portion 4,14 Insulator layer 5,15 Bonding pad (convex portion of wiring metal layer)
Claims (1)
われた配線金属層の一部を、該絶縁体層から露出させた
ボンディングパッドを有する半導体装置であって、前記
配線金属層の一部を凸状に成形し、該凸状部の表面を前
記絶縁体層から露出させるとともに、該凸状部の表面を
該配線金属層の他の部分を覆う絶縁体層の表面より高い
位置に配設してなるボンディングパッドを有することを
特徴とする半導体装置。Claim: What is claimed is: 1. A semiconductor device having a bonding pad which is disposed on a semiconductor substrate and has a part of a wiring metal layer covered with an insulating layer exposed from the insulating layer. A part of the wiring metal layer is formed into a convex shape, the surface of the convex part is exposed from the insulator layer, and the surface of the convex part covers the other part of the wiring metal layer. A semiconductor device having a bonding pad arranged at a position higher than the surface of the body layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3206425A JPH0529375A (en) | 1991-07-23 | 1991-07-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3206425A JPH0529375A (en) | 1991-07-23 | 1991-07-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0529375A true JPH0529375A (en) | 1993-02-05 |
Family
ID=16523167
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3206425A Pending JPH0529375A (en) | 1991-07-23 | 1991-07-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0529375A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7956473B2 (en) | 2007-07-23 | 2011-06-07 | Renesas Electronics Corporation | Semiconductor device |
| JP2017108070A (en) * | 2015-12-11 | 2017-06-15 | 新光電気工業株式会社 | Wiring board, semiconductor device and wiring board manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS604248A (en) * | 1983-06-22 | 1985-01-10 | Nec Corp | Semiconductor device |
| JPH0410447A (en) * | 1990-04-26 | 1992-01-14 | Minolta Camera Co Ltd | Ic chip mounting board |
| JPH0444233A (en) * | 1990-06-07 | 1992-02-14 | Seiko Instr Inc | Semiconductor device |
-
1991
- 1991-07-23 JP JP3206425A patent/JPH0529375A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS604248A (en) * | 1983-06-22 | 1985-01-10 | Nec Corp | Semiconductor device |
| JPH0410447A (en) * | 1990-04-26 | 1992-01-14 | Minolta Camera Co Ltd | Ic chip mounting board |
| JPH0444233A (en) * | 1990-06-07 | 1992-02-14 | Seiko Instr Inc | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7956473B2 (en) | 2007-07-23 | 2011-06-07 | Renesas Electronics Corporation | Semiconductor device |
| JP2017108070A (en) * | 2015-12-11 | 2017-06-15 | 新光電気工業株式会社 | Wiring board, semiconductor device and wiring board manufacturing method |
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| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19970916 |