JPH08306701A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide a semiconductor device which is protected against dielectric breakdown by providing a second insulation film selectively beneath a bonding pad while preventing a wafer from warping. CONSTITUTION: A base region 11 and an emitter region 12 are formed on the surface of a substrate 10 in order to fabricate an NPN transistor and then first base electrode and emitter electrode are formed. Subsequently, a second silicon oxide 20 is deposited selectively at a part for forming a pad. Thereafter, a first silicon nitride 16 is deposited on the entire surface and second base electrode and emitter electrodes are formed on the mitride 16. Finally, a bonding pad 19 is formed on the second silicon oxide 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to prevention of insulation failure of a semiconductor device having a bonding pad arranged on a unit cell by a multi-layer electrode structure.

[0002]

2. Description of the Related Art In order to increase a peripheral length of an emitter to increase a current of a transistor, an emitter region is formed in a lattice shape or an island shape to form a plurality of unit cells, and the unit cells are connected in parallel with electrodes. Are known. Also, if the bonding pad for external connection is composed of the electrode of the first layer, the cells for the pad area become invalid. Therefore, by forming the bonding pad with the electrode of the second layer using the multilayer electrode structure, It is known that a cell is arranged below the cell to form a small-area, large-current transistor.

To explain this structure with reference to FIG. 5, a P-type base region 2 is formed on the surface using the N-type semiconductor layer 1 as a collector, and a lattice type N + emitter region 3 is provided on the surface of the base region 2. Through the contact holes formed in the oxide film 4, the base electrode 5 and the emitter electrode 6 formed by the first electrode layer contact the respective diffusion regions, and the electrodes 5 and 6 are covered with the interlayer insulating film 7 made of a silicon nitride film. To do.
A second comb-shaped base (not shown) extending over the interlayer insulating film 7 through a through hole formed in the interlayer insulating film 7,
The emitter electrodes are commonly connected to the electrodes of the first layer, and the electrodes of the second layer are extended on the interlayer insulating film 7 on the cell to form bonding pads 8. (For example, JP-A-64-22062)

[0004]

As the current of the transistor is increased, it is necessary to increase the current capacity of the wire connected to the bonding pad 8. In recent years, a diameter of 40 μm has been required to pass an emitter current of several tens of amperes. It is not uncommon for the above large-diameter wire to be required. As the diameter of the wire increases, the ultrasonic energy required for wire bonding the wire also increases, and the interlayer insulating film 7 is cracked by the mechanical stress applied during wire bonding, and the bonding pad 8 and one layer below it are cracked. There is a drawback that short-circuiting between the base electrode and emitter occurs frequently due to short-circuiting with the eye electrode.

To simply solve this drawback, the thickness of the interlayer insulating film 7 may be increased. However, while the silicon nitride film has a suitable hardness to withstand ultrasonic energy during bonding, the mechanical stress applied to the silicon substrate is large due to the large difference in thermal expansion coefficient,
There is a problem of causing a large warp on the wafer. For example, when a silicon nitride film having a thickness of 3.0 μ or more is laminated as an interlayer insulating film, the warp of the wafer becomes 500 μ or more, which is a great obstacle to the subsequent assembly process.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional drawbacks.
It is intended to provide a semiconductor device capable of preventing warpage of a wafer and preventing occurrence of interlayer dielectric breakdown due to wire bonding by disposing a second interlayer insulating film partially.

[0007]

According to the present invention, since the lower part of the bonding pad has a large film pressure due to the second interlayer insulating film,
It can withstand the ultrasonic energy of wire bonding. On the other hand, since the second interlayer insulating film does not cover the entire surface of the chip, the stress applied to the wafer can be small.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device,
2 is a plan view showing a bonding pad portion of the base, and FIG. 1 is a sectional view taken along the line AA of FIG. Referring to FIGS. 1 and 2, a P type base region 11 is formed by selective diffusion on the front surface of an N type semiconductor substrate 10 having an N + type layer on the back surface,
An N + type emitter region 12 is also formed on the surface by selective diffusion.

The shape of the emitter region 12 is roughly classified into a lattice type and an island type. Here, the lattice type is taken as an example.
In the case of the lattice type, the surface of the base region 11 is exposed in an island shape in the grid portion (11a in FIG. 2), and the island-shaped base regions 11a are regularly arranged vertically and horizontally. The emitter region 12 surrounding one island-shaped base region 11a is used as a unit cell.

The surface of the substrate 10 is covered with a silicon oxide film 13, and a first base electrode 14 and a first emitter electrode 15 which are electrodes of the first layer are respectively formed through contact holes formed in the silicon oxide film 13. Ohmic contact is made to the diffusion region of. The first base electrodes 14 are in contact with the surface of the island-shaped base region 11a so as to be scattered,
The first emitter electrode 15 extends along the grid pattern and contacts almost the entire surface of the emitter region 12 via the grid-shaped contact holes.

The first-layer electrode is covered with a first silicon nitride film 16 having a thickness of 2.0 μ, and the second-layer electrode is formed through a through hole formed in the first silicon nitride film 16. A second base electrode 17 and a second emitter electrode 18 (illustrated in FIG. 2) made of electrodes are in contact with the first base electrode 14 and the first emitter electrode 15, respectively. The second base electrode 17 and the second emitter electrode 18 extend in a comb shape on the first silicon nitride film 16 and extend in parallel so that the comb teeth face each other. The second base electrode 17 connects the first base electrodes 14 in common through through holes provided immediately above the scattered first base electrodes 14. Second
The emitter electrode 18 is contacted with the first emitter electrode 15 by meeting through holes provided so as to be scattered at the intersections of the lattice-shaped mesh.

The second base electrode 17 and the second emitter electrode 18 are expanded on the first silicon nitride film 16 to form a rectangular bonding pad 19 having a side of about 100 μ, and the comb of the comb-teeth electrode is formed. All bonding pads 19
It is connected to the. Since FIG. 1 shows the base bonding pad, it also contacts the first base electrode 14 therebelow.

Then, in a region where the bonding pad 19 is arranged, in a range slightly larger than the bonding pad,
A second silicon nitride film 20 having a film thickness of 1.5 μ is formed between the bonding pad 19 and the first emitter electrode 15. If it is a base bonding pad, the second silicon nitride film 20 needs to cover at least the first emitter electrode 15, and if it is an emitter bonding pad, it needs to cover at least the first base electrode 14. There is. The second silicon nitride film 20 may be located on the first silicon nitride film 16, but the second silicon nitride film 20 is patterned to form a first base.
In order to avoid the problem that the silicon nitride film 16 is etched, it is advantageous in the manufacturing process that the second silicon nitride film 20 is located below. This does not apply if an insulating film having selectivity with the underlying insulating film is used.

The electrode of the second layer is covered with a final passivation film, or the electrode of the second layer is the final electrode and is directly molded. Then, the substrate 10 is die-bonded on the lead frame, and the pad 19 and the lead are connected by wire bonding with the wire 21,
Resin molded. The wire is a gold wire having a diameter of 40 μm or more and is bonded by ultrasonic thermocompression bonding.

FIG. 3 is a plan view showing only the diffusion layer and the first electrode layer of the entire chip, FIG. 4 is a plan view showing only the diffusion layer and the second interlayer insulating film, and FIG. 5 is the same. FIG. 6 is a plan view showing only a diffusion layer and a second electrode layer. In FIG. 3, after forming each diffusion region, the oxide film 13 covering the surface is formed.
A contact hole is formed in the first base electrode 14 by depositing an aluminum material on the entire surface and patterning it.
And the first emitter electrode 15 is formed. The first base electrode 14 is arranged in each of the island-shaped base regions 11a, and includes a ring-shaped base electrode 14b surrounding the emitter region 12. Further, a stripe-shaped base is formed in a portion where the emitter pad is to be buried under the emitter pad. Electrode 1
4b. The first emitter electrode 15 extends in a grid shape along the grid-shaped emitter region 12. 22 is a field electrode.

Referring to FIG. 4, a silicon nitride film is deposited on the entire surface by plasma CVD and patterned to form a second silicon nitride film 20.
At the base pad portion, a through hole 23 for contacting the base pad and the first base electrode 14 is also formed at the same time. The emitter pad portion is formed so as to cover the annular and striped base electrodes 14a and 14b. Then, the first silicon nitride film 16 is deposited again by the plasma CVD method to form through holes for interlayer connection (not shown).

Referring to FIG. 5, the second base electrode 17 and the second base electrode 17 are formed by depositing and patterning an aluminum material on the entire surface.
The emitter electrode 18, the base bonding pad 19a and the emitter bonding pad 19b are formed. The second base electrode 17 and the second emitter electrode 18 are the first base electrode 14 and the first emitter electrode 15, respectively.
Are connected in common and all the unit cells are connected in parallel. Each of the bonding pads 19a and 19b is connected to the corresponding first layer electrode in the lower portion through a through hole.
Below the emitter bonding pad 19b, the striped base electrode 1 connected to the second base electrode 17 is formed.
4b supplies a base bias to the unit cell.

In the semiconductor device of the present invention described above, since the second silicon nitride film 20 is formed under the bonding pads 19a and 19b, the film pressure of the interlayer insulating film is increased and the energy for wire bonding is increased. Can also withstand enough. Therefore, it is possible to prevent interlayer insulation breakdown due to cracks or the like. Further, since it is not formed on the entire surface of the chip, the warp of the wafer can be suppressed to be small. Furthermore, since the problem of wafer warpage can be eliminated by forming it partially, a silicon nitride film that is suitable for hardness can be used as the insulating film under the bonding pad, and therefore a highly reliable semiconductor device can be provided. is there.

The above embodiment has been described with respect to the lattice type emitter, but it is also applicable to an island type emitter. In this case, the base region is exposed in a lattice type.

[0020]

As described above, according to the present invention, the insulation by the energy at the time of wire bonding has an advantage that the opening can be prevented in advance. Therefore, a wire with a large diameter can be used, and the number of wires can be reduced as compared with the method of bonding a plurality of wires in order to increase the current capacity, which is advantageous in terms of cost and reliability.

Further, since the wafer is partially formed, the warp of the wafer can be suppressed to about 200 μ or less, and there is an advantage that obstacles in the assembly process can be eliminated. Furthermore, since there is no warp of the wafer, there is an advantage that the lower portion of the bonding pad can be made of a silicon nitride film. This means that compared to the case of using a silicon oxide film, it can be formed at a lower temperature, so that it does not require extra heat treatment to the aluminum material, and it is a material that is hard in hardness, so it can withstand the impact of wire bonding sufficiently. is there.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a plan view for explaining the present invention.

FIG. 3 is a plan view showing a diffusion layer and a first layer electrode.

FIG. 4 is a plan view showing a diffusion layer and a second silicon nitride film.

FIG. 5 is a plan view showing a diffusion layer and a second electrode.

FIG. 6 is a cross-sectional view for explaining a conventional example.

Claims (3)

[Claims] 1. A base region of opposite conductivity type formed on the surface of a semiconductor layer of one conductivity type, and a lattice type or island-shaped region formed on the surface of the base region.
A first conductivity type emitter region forming a number of unit cells; a first-layer base electrode contacting the surface of the base region; a first-layer emitter region contacting the surface of the emitter region; An interlayer insulating film that covers the base electrode and the emitter electrode of the first layer, and a base of the first layer that extends through the through hole formed in the interlayer insulating film in a comb shape extending over the interlayer insulating film. A second-layer base electrode, which is connected to the electrode, and a comb-teeth shape extending above the interlayer insulating film, and connected to the first-layer emitter electrode through a through hole formed in the interlayer insulating film. A base bonding pad that is continuous with and extends from the second-layer base electrode, and that is interlayer-insulated with the underlying first-layer emitter electrode, Emi of the layer An emitter bonding pad that is continuous with and extends from the base electrode of the first layer below the emitter electrode and that is partially formed below the base and emitter bonding pads. 2. A semiconductor device comprising a second interlayer insulating film for increasing the thickness of the interlayer insulating film. 2. The semiconductor device according to claim 1, wherein the first and second interlayer insulating films are silicon nitride films. 3. The semiconductor device according to claim 1, wherein the second interlayer insulating film is located between the interlayer insulating film and the base and emitter electrodes of the first layer.