JP2839007B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a conventional semiconductor device, first, as shown in FIG. 6, a passivation film 603 is formed so as to cover an uppermost layer wiring 602 formed on an interlayer film 601 and is formed by photolithography and etching. A part of the passivation film 603 is removed, and the pad opening 60 is removed.
4 had been formed. Since the etching opening is provided with a margin so that the passivation film 603 remains on the pad electrode, the opening 604 is concave.

[0003]

In the semiconductor device described above, the pad opening is concave, and when the pad opening is miniaturized with the miniaturization of an integrated circuit, the depth of the opening relative to the area of the opening is reduced. The ratio becomes large, and as shown in FIG.
1 and the passivation film 702 interfere with each other,
This causes bonding failure to the aluminum wiring 703. 7B and 7C, when the bonding position is shifted, the passivation film 702 is spread due to the spread of the wire / lead wire 701 during bonding at the position indicated by the arrow in the figure. Is pressed and cracks occur, or the passivation film 702 becomes an obstacle, resulting in poor bonding. Therefore, it is necessary to increase the area of the pad opening 704 in consideration of a margin depending on bonding accuracy.

Accordingly, an object of the present invention is to provide a structure and a manufacturing method of a semiconductor device which enables high integration of an LSI by reducing a margin required for bonding and enables bonding with good controllability. Is the thing.

[0005]

According to the first aspect of the present invention, the uppermost layer is provided on a semiconductor substrate and covers the side wall of the uppermost layer wiring, and the upper surface is flush with the upper surface of the uppermost layer wiring. A semiconductor device having a passivation film with the wiring exposed and also having a passivation film below the uppermost wiring is obtained.

According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the surface of the semiconductor substrate is covered with a passivation film.

According to the third aspect of the present invention, a step of forming a step in a region to be a pad portion, a step of forming an uppermost layer wiring including the pad portion, and a step of forming a top surface including side walls of the uppermost layer wiring A method of manufacturing a semiconductor device, comprising: forming a passivation film; and polishing the passivation film to expose the pad electrode portion.

According to a fourth aspect of the present invention, a step of forming an uppermost layer wiring, a step of forming a passivation film on a surface including a side wall of the uppermost layer wiring, and polishing the passivation film to form the uppermost layer wiring And a step of exposing a wiring.

According to the fifth aspect of the present invention, a step of forming a first passivation film, a step of forming an uppermost layer wiring on the first passivation film, and a surface including a side wall of the uppermost layer wiring Forming a second passivation film, and polishing the second passivation film to expose the uppermost layer wiring.

According to the present invention, a step of forming a first passivation film, a step of forming an uppermost layer wiring on the first passivation film, and a surface including a side wall of the uppermost layer wiring Forming a second passivation film, polishing the second passivation film to expose the uppermost layer wiring, and forming a third passivation layer on the uppermost layer wiring and the second passivation film. A method of manufacturing a semiconductor device is provided, which includes a step of forming a film and a step of forming an opening for bonding in the third passivation film.

According to a seventh aspect of the present invention, there is provided a semiconductor device manufactured by the method of manufacturing a semiconductor device according to any one of the third to sixth aspects, wherein the semiconductor device is provided on a semiconductor substrate. The pad electrode portion is formed higher than the other uppermost layer wiring, covers the surface including the side wall of the uppermost layer wiring including the pad electrode portion, and sets the upper surface to be flush with the upper surface of the pad electrode portion, thereby forming the pad electrode. A semiconductor device having an exposed passivation film is obtained.

According to an eighth aspect of the present invention, there is provided a semiconductor device manufactured by the method of manufacturing a semiconductor device according to any one of the third to sixth aspects, wherein the semiconductor device is provided on a semiconductor substrate. A semiconductor device having a passivation film which covers the side wall of the uppermost wiring and has the upper surface flush with the upper surface of the uppermost wiring to expose the uppermost wiring.

[0013]

Next, the present invention will be described with reference to the drawings.

FIG. 5 is a plan layout near a standard pad.
It is sectional drawing between A '. In FIG. 5, reference numeral 501 denotes an uppermost layer wiring, 502 denotes a pad lead-out portion of the uppermost layer wiring, 503 denotes a pad opening, and 504 denotes a scribe line.

[First Embodiment] FIGS. 1A to 1D are process cross-sectional views for explaining a manufacturing process according to a first embodiment of the present invention.

First, after the formation of the lower wiring and the interlayer film 101 is completed, the insulating film 102 is grown to 5000 °. Next, patterning is performed using ordinary photolithography technology and etching technology so that the insulating film 102 remains at the position where the pad electrode is formed (FIG. 1A).
reference). Subsequently, the uppermost aluminum wiring 103 is sputtered to a total thickness of 1.2 μm including the barrier film (Ti / TiN) and the antiglare film (TiN). Next, the uppermost aluminum wiring 103 is patterned by a normal photolithography technique and a dry etching technique (see FIG. 1B). Subsequently, a passivation film 104 such as a plasma oxide film or a plasma nitride film is
(FIG. 1 (c)), and the passivation film 104 is exposed using a wafer polishing technique until the pad electrode portion 103a is exposed.
Is polished (see FIG. 1D). By the above steps, the upper surface of the passivation film 104 and the upper surface of the pad electrode portion 103a are flush with each other and the pad electrode portion 103
It is possible to obtain a structure in which a is selectively exposed.

[Second Embodiment] FIGS. 2A and 2B are process cross-sectional views for explaining a manufacturing process according to a second embodiment of the present invention.

First, after a lower wiring and an interlayer film 201 are formed, an uppermost aluminum wiring 202 is formed by a barrier film (TiN / T
i) Sputtering is performed to a thickness of 1.2 μm including the antiglare film (TiN). Next, the uppermost aluminum layer wiring 20 is formed by ordinary photolithography and dry etching.
Then, a passivation film 203 such as a plasma oxide film or a plasma nitride film is grown to a thickness of 2 μm (see FIG. 2A). Next, the passivation film 203 is polished using a wafer polishing technique until the uppermost aluminum wiring 202 is exposed (see FIG. 2B).

By the above steps, the passivation film 20
3 and the uppermost aluminum layer wiring 202 including the pad electrode portion
Can be obtained, and the surface of the uppermost aluminum wiring 202 including the pad electrode is selectively exposed.

In the second embodiment, most of the uppermost wiring is exposed and the uppermost wiring can be used as a part of the passivation film. However, the second embodiment is different from the first embodiment. The step of forming one step under the pad for one PR can be reduced.

Third Embodiment FIGS. 3A and 3B are process cross-sectional views for explaining a manufacturing process according to a third embodiment of the present invention.

First, after forming a lower wiring and an interlayer film 301, a first passivation film 302 such as a plasma oxide film or a plasma nitride film is grown by 3000.degree., And then an uppermost aluminum wiring 303 is formed as a barrier film (TiN / Ti). And sputter with a thickness of 1.2 μm including the anti-glare film (TiN). Subsequently, the uppermost aluminum wiring 303 is patterned using a normal photolithography technique and a dry etching technique (see FIG. 3A). Next, after a second passivation film 304 is formed with a thickness of 2 μm, it is polished using a wafer polishing technique until the upper surface of the uppermost aluminum wiring 303 including the pad region 303a is exposed (FIG. 3).
(B)).

By the above steps, the passivation film 30
4 and the upper surface of the uppermost aluminum wiring 303 including the pad electrode 303a are flush with each other, and the surface of the pad electrode 303a including the uppermost aluminum wiring 303 is selectively exposed. I can do it.

In the third embodiment, a part of the wiring is used as a passivation film in the second embodiment. On the other hand, by forming a passivation film below the uppermost aluminum wiring, the uppermost aluminum wiring is formed. Although only the wiring is not covered with the passivation film, the lower layers are all covered with the passivation film.

Fourth Embodiment FIGS. 4A to 4C are process cross-sectional views for explaining a manufacturing process according to a fourth embodiment of the present invention.

First, after the formation of the lower layer wiring and the interlayer film 401, a first passivation film 402 such as a plasma oxide film or a plasma nitride film is grown to 3000.degree., And then the uppermost aluminum wiring 403 is formed as a barrier film (TiN / Ti). And sputter with a thickness of 1.2 μm including the anti-glare film (TiN). Subsequently, the uppermost aluminum wiring 403 is patterned by using a normal photolithography technique and a dry etching technique (see FIG. 4A). Next, after forming a second passivation film 404 with a thickness of 2 μm, the uppermost aluminum wiring 4 including the pad region is formed by using a wafer polishing technique.
Polishing is performed until the upper surface of No. 03 is exposed (see FIG. 4B). Next, a third passivation film 405 is formed, and a pad electrode portion 403a is opened using a normal photolithography technique and an etching technique. (FIG. 4
(C)).

The fourth embodiment is different from the third embodiment in that the uppermost aluminum wiring 303 is the first passivation film 3.
02, the uppermost aluminum wiring 4
03 also has a structure covered with the passivation film 405, and further improvement in reliability can be expected.

In this structure, the uppermost aluminum wiring 4
Since the second passivation film 404 is buried between the electrodes 03, the opening of the pad electrode portion 403a is not influenced by the size or pattern of the electrode, and the size and shape are freely set so as not to hinder the bonding. it can.

[0029]

As described above, in the semiconductor device according to the first to third embodiments of the present invention, since the upper surface of the passivation film and the upper surface of the pad electrode are flush with each other, even if the pad electrode area is reduced. Interference between the passivation film and the bonding wire or TAB lead does not occur, and good bonding can be performed. Further, the semiconductor device according to the fourth embodiment has the same advantages as the semiconductor device according to the first to third embodiments, since the opening of the bonding portion can be made large without being affected by the size of the pad electrode.
Therefore, even if the bonding position is slightly deviated, there is no fear that the passivation film is pushed and cracked due to the spread of the wires and leads during bonding, and there is no fear that the passivation film becomes an obstacle and a bonding failure occurs. It is not necessary to increase the area of the pad opening in consideration of the margin. Accordingly, since the pad electrode can be miniaturized, high integration of the LSI and bonding with good controllability and reliability can be realized.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view for explaining a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view for explaining a manufacturing method according to a second embodiment of the present invention.

FIG. 3 is a process cross-sectional view for explaining a manufacturing method according to a third embodiment of the present invention.

FIG. 4 is a process cross-sectional view for explaining a manufacturing method according to a fourth embodiment of the present invention.

FIG. 5 is a plan layout view near a standard pad electrode.

FIG. 6 is a sectional view of a conventional example.

FIG. 7 is an explanatory diagram of a cause of a failure occurring in the conventional example shown in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Interlayer film 102 Insulating film 103 Top layer aluminum wiring 103a Pad electrode part 104 Passivation film 201 Interlayer film 202 Top layer aluminum wiring 203 Passivation film 301 Interlayer film 302 First passivation film 303 Top layer aluminum wiring 303a Pad electrode part 304 Second Passivation film 401 Interlayer film 402 First passivation film 403 Uppermost layer aluminum wiring 403a Pad electrode section 404 Second passivation film 405 Third passivation film 501 Topmost layer wiring 502 Pad lead-out section 503 Pad opening 504 Scribe line

Claims (8)

(57) [Claims] A passivation film that covers a sidewall of an uppermost layer wiring provided on a semiconductor substrate and has an upper surface flush with an upper surface of the uppermost layer wiring to expose the uppermost layer wiring; A semiconductor device having a passivation film also under a wiring. 2. The semiconductor device according to claim 1, wherein a surface of said semiconductor substrate is covered with a passivation film. 3. A step of forming a step in a region to be a pad section, a step of forming an uppermost layer wiring including the pad section, and a step of forming a passivation film on a surface including a sidewall of the uppermost layer wiring. Polishing the passivation film to expose the pad electrode portion. 4. A step of forming an uppermost layer wiring, a step of forming a passivation film on a surface including a side wall of the uppermost layer wiring, and a step of polishing the passivation film to expose the uppermost layer wiring. A method for manufacturing a semiconductor device, comprising: 5. A step of forming a first passivation film, a step of forming an uppermost wiring on the first passivation film, and forming a second passivation film on a surface including a side wall of the uppermost wiring. And a step of polishing the second passivation film to expose the uppermost layer wiring. 6. A step of forming a first passivation film, a step of forming an uppermost layer wiring on the first passivation film, and forming a second passivation film on a surface including a side wall of the uppermost layer wiring. Performing the step of: polishing the second passivation film to expose the uppermost layer wiring; forming a third passivation film on the uppermost layer wiring and the second passivation film; Forming an opening for bonding in the third passivation film. 7. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 3, wherein the pad electrode portion provided on the semiconductor substrate is the other one. A passivation film which is formed higher than the upper wiring and covers the surface including the side wall of the uppermost wiring including the pad electrode portion, and has the upper surface flush with the upper surface of the pad electrode portion to expose the pad electrode. A semiconductor device characterized by the above-mentioned. 8. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 3, wherein the side wall of the uppermost wiring provided on the semiconductor substrate is covered. And a passivation film having an upper surface flush with the upper surface of the uppermost layer wiring and exposing the uppermost layer wiring.