JPH09283554A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease a necessary margin at the time of bonding by a method wherein a pad electrode part is formed higher than other uppermost wiring layer, the surfaces comprising the surface of the pad electrode part and the surfaces of the sidewalls of the uppermost wiring layer are covered with a passivation film to make the upper surface of the passivation film flush with the upper surface of the pad electrode part and to expose the pad electrode part. SOLUTION: A lower wiring layer and an interlayer film 101 are formed and thereafter, an insulating film 102 is grown, the film 102 is patterned in such a way as to remain on a position where a pad electrode part 103a is formed, and the pad electrode part 103a is formed higher then other uppermost aluminum wiring layer 103. The surfaces comprising the surface of the electrode part 103a and the sidewall surfaces of the layer 103 are coated with a passiavation film 104, such as a plasma oxide film, then, the upper surface of the film 104 and the upper surface of the electrode part 104a are formed into the same surface to expose the electrode part 103a selectively. Accordingly, good bonding is made possible.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a conventional semiconductor device, first, as shown in FIG. 6, a passivation film 603 is formed so as to cover an uppermost layer wiring 602 formed on an interlayer film 601, and a photolithography technique and an etching technique are used. The passivation film 603 was removed and the pad opening 604 was formed. Since the etching opening is provided with a margin so that the passivation film 603 remains on the pad electrode, the opening 604 is concave.

[0003]

In the semiconductor device described above, the pad opening is concave, and when the pad opening is miniaturized with the miniaturization of an integrated circuit, the depth of the opening relative to the area of the opening is reduced. The ratio becomes large, and as shown in FIG.
1 and the passivation film 702 interfere with each other,
This causes bonding failure to the aluminum wiring 703. 7B and 7C, when the bonding position is shifted, the passivation film 702 is spread due to the spread of the wire / lead wire 701 during bonding at the position indicated by the arrow in the figure. Is pressed and cracks occur, or the passivation film 702 becomes an obstacle, resulting in poor bonding. Therefore, it is necessary to increase the area of the pad opening 704 in consideration of a margin depending on bonding accuracy.

Therefore, an object of the present invention is to provide a structure and a manufacturing method of a semiconductor device which enables high integration of an LSI by reducing a margin necessary for bonding and enables bonding with good controllability. It is a thing.

[0005]

According to the first aspect of the invention, the pad electrode portion provided on the semiconductor substrate is formed higher than the other uppermost layer wiring, and the sidewall of the uppermost layer wiring including the pad electrode portion. A semiconductor device is provided which has a passivation film which covers the surface including the above and has the upper surface flush with the upper surface of the pad electrode portion and exposing the pad electrode.

According to the second aspect of the present invention, the passivation is formed by covering the side wall of the uppermost layer wiring provided on the semiconductor substrate and exposing the uppermost layer wiring by making the upper surface flush with the upper surface of the uppermost layer wiring. A semiconductor device having a film is obtained.

According to the third aspect of the present invention, there is provided a semiconductor device according to the second aspect, characterized in that a passivation film is also provided under the uppermost wiring.

According to a fourth aspect of the invention, there is provided a semiconductor device according to the third aspect, characterized in that the surface of the semiconductor substrate is covered with a passivation film.

According to a fifth aspect of the present invention, a step of forming a step in a region to be a pad portion, a step of forming an uppermost layer wiring including the pad portion, and a surface including a sidewall of the uppermost layer wiring A method for manufacturing a semiconductor device is obtained which includes a step of forming a passivation film and a step of polishing the passivation film to expose the pad electrode portion.

According to the invention of claim 6, the step of forming the uppermost layer wiring, the step of forming a passivation film on the surface including the sidewall of the uppermost layer wiring, and the step of polishing the passivation film to form the uppermost layer. A method of manufacturing a semiconductor device is provided, including the step of exposing wiring.

According to the seventh aspect of the invention, the step of forming the first passivation film, the step of forming the uppermost layer wiring on the first passivation film, and the surface including the side wall of the uppermost layer wiring And a step of forming a second passivation film, and a step of polishing the second passivation film to expose the uppermost wiring layer.

According to an eighth aspect of the present invention, a step of forming a first passivation film, a step of forming an uppermost layer wiring on the first passivation film, and a surface including a sidewall of the uppermost layer wiring. A second passivation film, a step of polishing the second passivation film to expose the uppermost layer wiring, and a third passivation film on the uppermost layer wiring and the second passivation film. A method of manufacturing a semiconductor device including a step of forming a film and a step of forming an opening for bonding in the third passivation film can be obtained.

[0013]

Next, the present invention will be described with reference to the drawings.

FIG. 5 is a plan layout near a standard pad.
It is sectional drawing between A '. In FIG. 5, reference numeral 501 denotes an uppermost layer wiring, 502 denotes a pad lead-out portion of the uppermost layer wiring, 503 denotes a pad opening, and 504 denotes a scribe line.

[First Embodiment] FIGS. 1A to 1D are process cross-sectional views for explaining a manufacturing process of a first embodiment of the present invention.

First, after the formation of the lower wiring and the interlayer film 101 is completed, the insulating film 102 is grown to 5000 °. Next, patterning is performed using ordinary photolithography technology and etching technology so that the insulating film 102 remains at the position where the pad electrode is formed (FIG. 1A).
reference). Subsequently, the uppermost aluminum wiring 103 is sputtered to a total thickness of 1.2 μm including the barrier film (Ti / TiN) and the antiglare film (TiN). Next, the uppermost aluminum wiring 103 is patterned by a normal photolithography technique and a dry etching technique (see FIG. 1B). Subsequently, a passivation film 104 such as a plasma oxide film or a plasma nitride film is
(FIG. 1 (c)), and the passivation film 104 is exposed using a wafer polishing technique until the pad electrode portion 103a is exposed.
Is polished (see FIG. 1D). By the above steps, the upper surface of the passivation film 104 and the upper surface of the pad electrode portion 103a are flush with each other and the pad electrode portion 103
It is possible to obtain a structure in which a is selectively exposed.

[Second Embodiment] FIGS. 2A and 2B are process cross-sectional views for explaining a manufacturing process of a second embodiment of the present invention.

First, after a lower wiring and an interlayer film 201 are formed, an uppermost aluminum wiring 202 is formed by a barrier film (TiN / T
i) Sputtering is performed to a thickness of 1.2 μm including the antiglare film (TiN). Next, the uppermost aluminum layer wiring 20 is formed by ordinary photolithography and dry etching.
2 is patterned, and then a passivation film 203 such as a plasma oxide film or a plasma nitride film is grown to a thickness of 2 μm (see FIG. 2A). Next, the passivation film 203 is polished using a wafer polishing technique until the uppermost aluminum wiring 202 is exposed (see FIG. 2B).

By the above steps, the passivation film 20
3 and the uppermost aluminum layer wiring 202 including the pad electrode portion
Can be obtained, and the surface of the uppermost aluminum wiring 202 including the pad electrode is selectively exposed.

In the second embodiment, most of the uppermost wiring is exposed and the uppermost wiring can be used as a part of the passivation film. However, the second embodiment is different from the first embodiment. The step of forming one step under the pad for one PR can be reduced.

[Third Embodiment] FIGS. 3A and 3B are process cross-sectional views for explaining a manufacturing process of a third embodiment of the present invention.

First, after forming a lower wiring and an interlayer film 301, a first passivation film 302 such as a plasma oxide film or a plasma nitride film is grown by 3000.degree., And then an uppermost aluminum wiring 303 is formed as a barrier film (TiN / Ti). And sputter with a thickness of 1.2 μm including the anti-glare film (TiN). Subsequently, the uppermost aluminum wiring 303 is patterned using a normal photolithography technique and a dry etching technique (see FIG. 3A). Next, after a second passivation film 304 is formed with a thickness of 2 μm, it is polished using a wafer polishing technique until the upper surface of the uppermost aluminum wiring 303 including the pad region 303a is exposed (FIG. 3).
(B)).

By the above steps, the passivation film 30
4, the upper surface of the uppermost aluminum wiring 303 including the pad electrode 303a is on the same plane, and the surface of the pad electrode 303a including the uppermost aluminum wiring 303 is selectively exposed. I can.

In the third embodiment, a part of the wiring is used as a passivation film in the second embodiment. On the other hand, by forming a passivation film below the uppermost aluminum wiring, the uppermost aluminum wiring is formed. Although only the wiring is not covered with the passivation film, the lower layers are all covered with the passivation film.

[Fourth Embodiment] FIGS. 4A to 4C are process cross-sectional views for explaining a manufacturing process of a fourth embodiment of the present invention.

First, after the formation of the lower layer wiring and the interlayer film 401, a first passivation film 402 such as a plasma oxide film or a plasma nitride film is grown to 3000.degree., And then the uppermost aluminum wiring 403 is formed as a barrier film (TiN / Ti). And sputter with a thickness of 1.2 μm including the anti-glare film (TiN). Subsequently, the uppermost aluminum wiring 403 is patterned by using a normal photolithography technique and a dry etching technique (see FIG. 4A). Next, after forming a second passivation film 404 with a thickness of 2 μm, the uppermost aluminum wiring 4 including the pad region is formed by using a wafer polishing technique.
Polishing is performed until the upper surface of No. 03 is exposed (see FIG. 4B). Next, a third passivation film 405 is formed, and a pad electrode portion 403a is opened using a normal photolithography technique and an etching technique. (FIG. 4
(C)).

The fourth embodiment is different from the third embodiment in that the uppermost aluminum wiring 303 is the first passivation film 3.
02, the uppermost aluminum wiring 4
03 also has a structure covered with the passivation film 405, and further improvement in reliability can be expected.

In this structure, the uppermost aluminum wiring 4
Since the second passivation film 404 is buried between the electrodes 03, the opening of the pad electrode portion 403a is not influenced by the size or pattern of the electrode, and the size and shape are freely set so as not to hinder the bonding. it can.

[0029]

As described above, in the semiconductor device according to the first to third embodiments of the present invention, since the upper surface of the passivation film and the upper surface of the pad electrode are flush with each other, even if the pad electrode area is reduced. Interference between the passivation film and the bonding wire or TAB lead does not occur, and good bonding can be performed. Further, the semiconductor device according to the fourth embodiment has the same advantages as the semiconductor device according to the first to third embodiments, since the opening of the bonding portion can be made large without being affected by the size of the pad electrode.
Therefore, even if the bonding position is slightly deviated, there is no fear that the passivation film is pushed and cracked due to the spread of the wires and leads during bonding, and there is no fear that the passivation film becomes an obstacle and a bonding failure occurs. It is not necessary to increase the area of the pad opening in consideration of the margin. Accordingly, since the pad electrode can be miniaturized, high integration of the LSI and bonding with good controllability and reliability can be realized.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view for explaining a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view for explaining a manufacturing method according to a second embodiment of the present invention.

FIG. 3 is a process cross-sectional view for explaining a manufacturing method according to a third embodiment of the present invention.

FIG. 4 is a process cross-sectional view for explaining a manufacturing method according to a fourth embodiment of the present invention.

FIG. 5 is a plan layout view near a standard pad electrode.

FIG. 6 is a sectional view of a conventional example.

FIG. 7 is an explanatory diagram of a cause of a failure occurring in the conventional example shown in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Interlayer film 102 Insulating film 103 Top layer aluminum wiring 103a Pad electrode part 104 Passivation film 201 Interlayer film 202 Top layer aluminum wiring 203 Passivation film 301 Interlayer film 302 First passivation film 303 Top layer aluminum wiring 303a Pad electrode part 304 Second Passivation film 401 Interlayer film 402 First passivation film 403 Uppermost layer aluminum wiring 403a Pad electrode section 404 Second passivation film 405 Third passivation film 501 Topmost layer wiring 502 Pad lead-out section 503 Pad opening 504 Scribe line

Claims (8)

[Claims] 1. A pad electrode portion provided on a semiconductor substrate is formed higher than other uppermost layer wirings, covers a surface including a side wall of the uppermost layer wiring including the pad electrode portion, and has an upper surface on the pad electrode portion. A semiconductor device having a passivation film in which the pad electrode is exposed on the same plane as the upper surface of the semiconductor device. 2. A passivation film which covers the side wall of the uppermost layer wiring provided on the semiconductor substrate and has the upper surface flush with the upper surface of the uppermost layer wiring and exposing the uppermost layer wiring. Semiconductor device. 3. The semiconductor device according to claim 2, further comprising a passivation film in a lower layer of the uppermost wiring. 4. The semiconductor device according to claim 3, wherein the surface of the semiconductor substrate is covered with a passivation film. 5. A step of forming a step in a region to be a pad section, a step of forming an uppermost layer wiring including the pad section, and a step of forming a passivation film on a surface including a sidewall of the uppermost layer wiring, And a step of exposing the pad electrode portion by polishing the passivation film. 6. A step of forming an uppermost layer wiring, a step of forming a passivation film on a surface including a sidewall of the uppermost layer wiring, and a step of polishing the passivation film to expose the uppermost layer wiring. A method of manufacturing a semiconductor device, comprising: 7. A step of forming a first passivation film, a step of forming an uppermost layer wiring on the first passivation film, and a second passivation film on a surface including a sidewall of the uppermost layer wiring. And a step of polishing the second passivation film to expose the uppermost wiring, and a method of manufacturing a semiconductor device. 8. A step of forming a first passivation film, a step of forming an uppermost layer wiring on the first passivation film, and a step of forming a second passivation film on a surface including a sidewall of the uppermost layer wiring. A step of polishing the second passivation film to expose the uppermost layer wiring, forming a third passivation film on the uppermost layer wiring and the second passivation film, And a step of forming an opening for bonding in the third passivation film.