JPH0595048A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To promote high integration, and improve electric reliability, and speed up the operation, and improve the yield, in the manufacture of a semiconductor integrated circuit device. CONSTITUTION:A first interlayer film 4 thinner than first wiring 3 is made on this first wiring 3, and a connection hole 6, where the inside diameter is larger than the depth, is made, and wiring 7 for connection is made, and in the region excluding this wiring 7 for connection, a second interlayer insulating film 9, the surface level of which approximately agrees with the wiring 7 for connection, is made, and second wiring 11 is made. Accordingly, the connection hole 6 can be filled up easily with the wiring 7 for connection. The inside diameter of the connection hole 6 can be made smaller than the pattern of a photoresist film. The thickness of the second interlayer film 9 can be made thick similar to the wiring 7 for connection. The base step of the second wiring 11 can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having multi-layer wiring.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device having multi-layered wiring, when the degree of integration is increased, the aspect ratio (aspect ratio) of a connection hole for connecting an upper wiring and a lower wiring Will grow. When the aspect ratio of the connection hole is increased, the step coverage (coverage at the step) is reduced when the conductive film forming the wiring, for example, the aluminum film is formed, and the inside of the connection hole is filled with the conductive film. However, there is a problem in that the reliability of the electrical connection between the upper layer wiring and the lower layer wiring is reduced. To solve this problem, for example, by reducing the film thickness of the interlayer film, the aspect ratio can be reduced, the coverage of the conductive film in the connection hole can be improved, and the reliability of electrical connection cannot be improved. It is possible. However, when the film thickness of the interlayer film is thinned, the surface of the interlayer film cannot be sufficiently flattened, the coverage of the wiring formed in the upper layer of this interlayer film decreases, and the short circuit between the wirings occurs. There is a problem in that the power consumption is deteriorated or disconnection occurs due to defective formation of wiring. In addition, when the film thickness of the interlayer film is reduced, there is a problem that inter-wiring capacitance (coupling capacitance) increases and signal transmission delay in the wiring increases.

Therefore, as one method for improving the reliability of electrical connection between the upper layer wiring and the lower layer wiring, after forming a connection hole in the interlayer film on the lower layer wiring, the inside of the connection hole is formed. Buried with tungsten formed by the selective CVD method, an upper wiring is formed on the interlayer film, and through the tungsten,
A method for electrically connecting the upper layer and the lower layer wiring has been proposed. According to this method, the upper layer wiring and the lower layer wiring can be electrically connected through the connection hole having a large aspect ratio. Further, the film thickness of the interlayer film can be set to the extent that the capacitance between wirings can be reduced. Further, since the surface of the interlayer film can be flattened, disconnection failure and short circuit failure of the wiring in the upper layer of the interlayer film can be reduced.

[0004]

However, as a result of examining the above-mentioned prior art, the present inventor has found the following problems.

When the tungsten film is formed by the selective CVD method, the selectivity is lowered, and tungsten is formed not only in the connection hole but also on the interlayer film, resulting in a decrease in yield.

Further, there is a problem in that the film thickness of the tungsten film varies, and the reliability of electrical connection between the upper wiring and the lower wiring is lowered.

Further, since the tungsten film has a larger specific resistance than the aluminum film, there is a problem that the signal transmission delay in the wiring becomes large.

An object of the present invention is to provide a technique capable of achieving high integration in a method of manufacturing a semiconductor integrated circuit device having multi-layer wiring.

Another object of the present invention is to provide a technique capable of improving electrical reliability in the method of manufacturing a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of increasing the operating speed in the method for manufacturing a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique capable of improving the yield in the method of manufacturing a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0013]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

(1) A step of forming a first wiring on the main surface of a semiconductor substrate, and a first interlayer film whose film thickness on the first wiring is smaller than that of the first wiring. The step of forming in the upper layer of the first wiring, and the step of forming a connection hole in the first interlayer film on the first wiring, which has a larger inner diameter than the depth and exposes the surface of the first wiring. A step of forming by a lithographic technique and an etching technique, a second conductive film forming a connection wiring is formed on an upper layer of the first interlayer film, and the second conductive film is passed through the connection hole to form the first conductive film. Connecting to the wiring, the step of patterning the second conductive film by a photolithography technique and an etching technique to leave the connecting wiring on the connecting hole, and a region other than the connecting wiring. A second interlayer film is formed, and the surface of the connection wiring and the first Comprising of a step of substantially matching the surface of the interlayer film, and forming a second wiring connected to the connection wiring in the upper layer of the second interlayer film.

(2) The first wiring, the connection wiring, and the second wiring
Each of the wirings is mainly formed of an aluminum film or an aluminum alloy film.

(3) The second conductive film forming the connection wiring is formed thicker than the depth of the connection hole formed in the first interlayer film.

[0017]

According to the above-mentioned means (1), since the inner diameter of the connection hole formed in the first interlayer film is formed larger than the depth, the connection hole can be easily filled with the second conductive film. Since it can be embedded, the reliability of the electrical connection between the second conductive film and the first wiring can be improved. As a result, the electrical reliability of the semiconductor integrated circuit device can be improved.

Further, since the film thickness of the first interlayer film on the first wiring is thinner than the film thickness of the first wiring, the first interlayer film is patterned to form the connection hole. At this time, the side etching amount becomes small, and the inner diameter of the connection hole can be made close to the inner diameter of the connection hole pattern of the photoresist film. That is, since the connection holes can be miniaturized, the semiconductor integrated circuit device can be highly integrated.

When patterning the connection wiring, the connection wiring is formed smaller by side etching with respect to the pattern of the photoresist film. Therefore, the size of the connection wiring, that is, the second interlayer is formed. The size of the connection hole formed in the film can be reduced. That is, since the connection portion can be miniaturized, the semiconductor integrated circuit device can be highly integrated.

Further, a second interlayer film is formed in a region other than the connection wiring, and the height of the surface of the connection wiring and the height of the surface of the second interlayer film are made substantially equal to each other. The underlying step of the second wiring formed on the second interlayer film is reduced. As a result, the coverage when forming the second wiring can be improved, so that disconnection failure, short circuit failure, etc. of the second wiring due to the decrease in the coverage can be reduced and the yield of the semiconductor integrated circuit device can be improved. can do.

According to the above-mentioned means (2), since the specific resistance of the aluminum film or the aluminum alloy film is smaller than that of the tungsten film, the signal transmission delay in the wiring due to the resistance is reduced and the operation speed of the semiconductor integrated circuit device is reduced. It can speed up.

Further, the formation of the aluminum film can use a well-known and well-known formation technique, so that the selected CV is used.
The problem that occurs when the tungsten film is formed by the D method does not occur. As a result, the electrical reliability of the semiconductor integrated circuit device can be improved, the operating speed can be increased, and the yield can be improved.

According to the above-mentioned means (3), since the film thickness of the second interlayer film can be made as thick as the film thickness of the connection wiring, the first wiring and the second wiring can be formed. The inter-wiring capacitance (coupling capacitance) between and is reduced. As a result, it is possible to reduce the signal transmission delay in the wiring due to the capacitance between the wirings and increase the operating speed of the semiconductor integrated circuit device.

[0024]

Embodiments of the present invention will be specifically described below with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[Embodiment 1] The configuration of a semiconductor integrated circuit device according to Embodiment 1 of the present invention will be described with reference to FIG.

As shown in FIG. 1, the semiconductor integrated circuit device according to the first embodiment is mainly composed of a semiconductor substrate 1.
The semiconductor substrate 1 is made of, for example, single crystal silicon.

An insulating film 2 is formed on the main surface of the semiconductor substrate 1.
Is provided. The insulating film 2 is made of, for example, a silicon oxide film. On the main surface portion of the semiconductor substrate 1,
Elements not shown are provided. The insulating film 2 is provided on this element.

A first wiring 3 is provided on the insulating film 2. The first wiring 3 is made of, for example, an aluminum film or an aluminum alloy film.
The film thickness of the first wiring 3 is, for example, about 1 μm. The width of the first wiring 3 is, for example, about 2 to 3 μm. The first wiring 3 is electrically connected to the element (not shown) through a connection hole (not shown) of the insulating film 2.

An interlayer insulating film 4 is provided on the upper layer of the first wiring 3. The interlayer insulating film 4 is composed of, for example, a silicon oxide film. The silicon oxide film forming the interlayer insulating film 4 is formed by, for example, the bias sputtering method. By forming this silicon oxide film by the bias sputtering method, the surface of this interlayer insulating film 4 can be flattened. The thickness of the interlayer insulating film 4 is, for example, 1.2 to 1.1 on the side wall of the first wiring 3.
It is about 3 μm. On the other hand, the film thickness of the interlayer insulating film 4 is
On the first wiring 3, for example, 0.2 to 0.3 μm
It is a degree. The first wiring 3 is formed on the interlayer insulating film 4.
Is provided with a connection hole 6 for exposing the surface thereof. The inner diameter of the connection hole 5 is, for example, about 1 to 1.5 μm.

A connection wiring 7 is provided on the connection hole 6. The connection wiring 7 is made of, for example, an aluminum film or an aluminum alloy film. The connection wiring 7 is thicker than the depth of the connection hole 6 and has a film thickness of, for example, about 1.5 μm. The width of the connection wiring 7 is, for example, about 2 to 3 μm.

A second interlayer insulating film 9 is provided in a region other than the connection wiring 7. The second interlayer insulating film 9 is provided so that the height of the surface thereof is substantially the same as the height of the surface of the connection wiring 7. This interlayer insulating film 9
Is made of, for example, a silicon oxide film. This silicon oxide film is formed by, for example, a flattening etching (etchback) so that the surface of the connection wiring 7 is exposed after being deposited by the CVD method.

A second layer is formed on the second interlayer insulating film 9.
Wiring 11 is provided. The second wiring 11 is
It is electrically connected to the surface of the first wiring 3 exposed from the second interlayer insulating film 9. This second wiring 11
Is composed of, for example, an aluminum film or an aluminum film. A surface protection film (not shown) is provided on the second wiring 11.

Next, a method of manufacturing the semiconductor integrated circuit device will be described with reference to FIGS. 2 to 7 (cross-sectional views of essential parts shown in each manufacturing process).

First, an element (not shown) is formed on the main surface portion of the semiconductor substrate 1. After that, the insulating film 2 is formed on the main surface of the semiconductor substrate 1.

Next, an aluminum film or an aluminum alloy film having a thickness of about 1 μm is formed on the insulating film 2 by, for example, a sputtering method. After that, the aluminum film or the aluminum alloy film is patterned by the photolithography technique and the etching technique to form the first wiring 3 as shown in FIG. The width of the wiring 3 is, for example, about 2 to 3 μm.

Next, a silicon oxide film is formed on the first wiring 3 by the bias sputtering method, for example. By forming the silicon oxide film by the bias sputtering method, the surface of the silicon oxide film can be flattened. This silicon oxide film constitutes the first interlayer insulating film 4. The film thickness of the first interlayer insulating film 4 is the same as that of the first
In the side wall portion of the wiring 3, the thickness is, for example, about 1.2 to 1.3 μm. On the other hand, the interlayer insulating film 4 on the first wiring 3
Has a film thickness of, for example, about 0.2 to 0.3 μm. After that, a photoresist film 5 is formed on the first interlayer insulating film 4.

Next, the photoresist film 5 is exposed and developed to form a pattern of connection holes (6). After that, as shown in FIG. 3, the first interlayer insulating film 4 is etched using the photoresist film 5 as a mask, and the first interlayer insulating film 4 is etched.
A connection hole 6 exposing the surface of the first wiring 3 is formed in the interlayer insulating film 4. The inner diameter of the connection hole 6 is, for example,
It is about 1 to 1.5 μm. In this step, the film thickness of the first interlayer insulating film 4 on the first wiring 3, that is, the depth of the connection hole 6 is the film thickness of the first wiring 3 (about 1 μm).
Since the thickness is thinner than about 0.2 to 0.3, the side etching amount when patterning the first interlayer insulating film 3 to form the connection hole 6 becomes small, and the inner diameter of the connection hole 6 is set to the photoresist film. It is possible to approach the inner diameter of the connection hole pattern of No. 5. That is, since the connection hole 6 can be miniaturized, the semiconductor integrated circuit device can be highly integrated.

Next, on the upper layer of the first interlayer insulating film 4,
For example, as shown in FIG. 4, an aluminum film forming the connection wiring 7 is formed by a sputtering method. The inner diameter of the connection hole 6 is about 1 to 1.5 μm, and the depth thereof is about 0.2 to 0.3 μm. Therefore, this connection hole 6
Since the aspect ratio of is small, the connection hole 6 can be easily filled with this aluminum film. Thereby, the reliability of the electrical connection between the aluminum film and the first wiring 3 can be improved. As a result, the electrical reliability of the semiconductor integrated circuit device can be improved. Then, a photoresist film 8 is formed on the aluminum film.

Next, the photoresist film 8 is exposed and developed to form a pattern of connection wiring (7). After that, the aluminum film is etched by using the photoresist film 8 as a mask to form the connection wiring 7 as shown in FIG. Here, when the connection wiring 7 is patterned, the connection wiring 7 is formed smaller than the pattern of the photoresist film 8 by side etching. The size of the connection hole formed in the interlayer insulating film (9) can be reduced. That is, since the connection portion can be miniaturized, the semiconductor integrated circuit device can be highly integrated. Then, the photoresist film 8 is removed.

Next, a second interlayer insulating film 9 is formed on the connection wiring 7. The second interlayer insulating film 9 is
For example, it is formed by depositing a silicon oxide film by the CVD method. Thereafter, as shown in FIG. 6, a photoresist film 10 is formed on the second interlayer insulating film 9.

Next, each of the photoresist film 10 and the second interlayer insulating film 9 is uniformly etched (etched back) by anisotropic etching, and as shown in FIG. The second interlayer film 9 is formed in the region of (1), and the height of the surface of the second interlayer insulating film 9 and the height of the surface of the first wiring 3 are made substantially equal. By this step, the surface of the first wiring 3 is exposed.

Next, on the upper layer of the second interlayer insulating film 9,
For example, an aluminum film or an aluminum alloy film is formed by a sputtering method. Thereafter, this aluminum film or aluminum alloy film is patterned by photolithography technology and etching technology, and the second wiring 1
1 is formed. The second wiring 11 is electrically connected to the exposed surface of the first wiring 3. Here, since the height of the surface of the second interlayer insulating film 9 and the height of the surface of the first wiring 3 are substantially the same, the underlying step of the second wiring 11 is reduced. .. As a result, the coverage when forming the aluminum film or the aluminum alloy film forming the second wiring 11 can be improved, so that the disconnection failure, the short-circuit failure, etc. of the second wiring 11 due to the decrease in the coverage. Can be reduced and the yield of the semiconductor integrated circuit device can be improved.

Next, a surface protection film (not shown) is formed on the second wiring 11 to complete the semiconductor integrated circuit device of the first embodiment shown in FIG.

As described above, according to the manufacturing method of the first embodiment, since the inner diameter of the connection hole 6 formed in the first interlayer insulating film 4 is formed larger than its depth, the connection is made. Since the connection wiring 6 can be easily filled with the connection wiring 7, the reliability of the electrical connection between the connection wiring 7 and the first wiring 3 can be improved. As a result, the electrical reliability of the semiconductor integrated circuit device can be improved.

Since the thickness of the first interlayer insulating film 4 on the first wiring 3 is thinner than that of the first wiring 3, the first interlayer insulating film 4 is patterned and connected. The amount of side etching when forming the holes 6 becomes small, and the inner diameter of the connection hole 6 can be brought close to the inner diameter of the connection hole pattern of the photoresist film 5. That is, since the connection hole 6 can be miniaturized, high integration of the semiconductor integrated circuit device can be achieved.

When patterning the connection wiring 7, since the connection wiring 7 is formed smaller than the pattern of the photoresist film 8 by side etching, the dimension of the connection wiring 7 is The size of the connection hole formed in the second interlayer saturated film 9 can be reduced.
That is, since the connecting portion can be miniaturized, high integration of the semiconductor integrated circuit device can be achieved.

Further, the second interlayer insulating film 9 is formed in a region other than the connecting wiring 7, and the height of the surface of the connecting wiring 7 and the height of the surface of the second interlayer insulating film 9 are substantially the same. By doing so, the underlying step of the second wiring 11 formed on the second interlayer insulating film 9 is reduced. This allows
Since the coverage when forming the second wiring 11 can be improved, disconnection failure, short circuit failure, etc. of the second wiring 11 due to the decrease in the coverage can be reduced, and the yield of the semiconductor integrated circuit device can be improved. be able to.

Further, since the specific resistance of the aluminum film or aluminum alloy film is smaller than that of the tungsten film, the first wiring 3, the connection wiring 7, and the second wiring 11 are formed by the resistance.
It is possible to reduce the signal transmission delay and increase the operation speed of the semiconductor integrated circuit device.

The formation of the aluminum film can be performed by using a well-known established formation technique, so that the selective CV method is used.
The problem that occurs when the tungsten film is formed by the D method does not occur. As a result, the electrical reliability of the semiconductor integrated circuit device can be improved, the yield can be improved, and the operating speed can be increased.

The film thickness of the second interlayer insulating film 9 is
Since the thickness can be made to be the same as the film thickness of the connection wiring 7, the wiring capacitance (coupling capacitance) between the first wiring 3 and the second wiring 11 is reduced. As a result, the signal transmission delay in the first wiring 3 and the second wiring 11 due to the capacitance between the wirings can be reduced, and the operation speed of the semiconductor integrated circuit device can be increased.

[Embodiment 2] Next, a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention will be described with reference to FIGS. 8 to 10 (cross-sectional views showing a part of the manufacturing process). explain.

First, an element (not shown) is formed on the main surface portion of the semiconductor substrate 1, and the main surface portion of the semiconductor substrate 1 is connected in the connection region between the first wiring (3) and the second wiring (11). The protrusion 12 is formed in the area where the hole is formed. This protrusion 12 may be formed at the same time in the step of forming the gate electrode of the MISFET, for example. Or
For example, after forming the insulating film 2, a silicon oxide film is formed,
The protrusion 12 may be formed by patterning this silicon oxide film by a photolithography technique.

Thereafter, the element and the protrusion 1 not shown
An interlayer insulating film 13 is formed on the second layer. At this time, a convex region corresponding to the shape of the protrusion 12 is formed in the interlayer insulating film 13 on the protrusion 12.

Next, the first wiring 3 is formed on the interlayer insulating film 13. At this time, since a convex region corresponding to the protrusion 12 is formed in the interlayer insulating film 13 under the first wiring 3, the convex region is also formed in the first wiring 3. It

Next, a first interlayer insulating film 4 is formed on the first wiring 3. At this time, a convex region due to the protrusion 12 is also formed on the surface of the interlayer insulating film 4. Then, a photoresist film 14 is formed on the interlayer insulating film 4.

Next, each of the photoresist film 14 and the first interlayer insulating film 4 is uniformly etched by anisotropic etching to expose the surface of the first wiring 3 and the other portions. Interlayer insulating film 4 is formed in the region.

Thereafter, the steps after the step of forming the second wiring 11 are performed in the same manner as in the first embodiment, whereby the semiconductor integrated circuit device of the second embodiment is completed.

As described above, according to the manufacturing method of the second embodiment, the connection region between the first wiring 3 and the second wiring 11 is self-aligned with the first wiring 3. Therefore, the connection portion can be miniaturized by the amount corresponding to the alignment margin. As a result, the semiconductor integrated circuit device can be highly integrated.

Further, it corresponds to the step of forming the connection wiring 7 and the second interlayer insulating film 9 by simultaneously forming the protrusion 12 in the step of forming the gate electrode of the MISFET as described above. Therefore, the number of manufacturing steps can be reduced.

[Third Embodiment] Next, a method for manufacturing a semiconductor integrated circuit device according to a third embodiment of the present invention will be described with reference to FIGS. 11 and 12 (cross-sectional views showing a part of the manufacturing process). explain.

First, the steps up to the step shown in FIG. 3 of the first embodiment are performed. After that, an aluminum film or an aluminum alloy film is selectively formed by the photo CVD method, and the connection hole 6 is formed.
The connection wiring 7 is formed thereon. Thereafter, steps subsequent to the step of forming the second interlayer insulating film 9 are performed to complete the semiconductor integrated circuit device of the third embodiment.

As described above, according to the manufacturing method of the third embodiment, when the aluminum film or the aluminum alloy film is formed by the photo CVD method, the connection wiring is selectively formed on the selection hole 6. Since 7 is formed, the connection portion can be miniaturized by the amount corresponding to the alignment margin. As a result, the semiconductor integrated circuit device can be highly integrated.

The number of manufacturing steps can be reduced by the amount corresponding to the step of forming the second interlayer insulating film 9.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. ..

For example, in the first to third embodiments,
Although the example in which each of the first wiring 3, the connection wiring 7, and the second wiring 11 is formed of an aluminum film or an aluminum alloy film has been shown, the present invention shows that all or any of these wirings is different from the others. It can also be formed of a conductive film.

Further, although the example in which the first interlayer insulating film 4 is formed by the bias sputtering method has been shown, the present invention shows that the first interlayer insulating film 4 is formed by, for example, the CVD method in the silicon oxide film. It can also be configured with.

[0068]

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.

In the method of manufacturing a semiconductor integrated circuit device,
High integration can be achieved.

In addition, in the method of manufacturing the semiconductor integrated circuit device, electrical reliability can be improved.

In the method of manufacturing a semiconductor integrated circuit device, the operating speed can be increased.

Further, in the method of manufacturing the semiconductor integrated circuit device, the yield can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a semiconductor integrated circuit device according to a first embodiment.

FIG. 2 is a sectional view of an essential part showing the semiconductor integrated circuit device in each manufacturing step.

FIG. 3 is a sectional view of an essential part showing the semiconductor integrated circuit device in each manufacturing step.

FIG. 4 is a cross-sectional view of essential parts showing the semiconductor integrated circuit device in each manufacturing step.

FIG. 5 is a cross-sectional view of essential parts showing the semiconductor integrated circuit device in each manufacturing step.

FIG. 6 is a sectional view of an essential part showing the semiconductor integrated circuit device in each manufacturing step.

FIG. 7 is a sectional view of an essential part showing the semiconductor integrated circuit device in each manufacturing step.

FIG. 8 is a cross-sectional view of essential parts showing part of the process of manufacturing a semiconductor integrated circuit device according to a second embodiment.

FIG. 9 is a sectional view of an essential part showing a part of the manufacturing process of the semiconductor integrated circuit device;

FIG. 10 is a cross-sectional view of essential parts showing part of the process of manufacturing the semiconductor integrated circuit device.

FIG. 11 is a cross-sectional view of essential parts showing part of the process of manufacturing a semiconductor integrated circuit device according to a third embodiment.

FIG. 12 is a sectional view of an essential part showing a part of the manufacturing process of the semiconductor integrated circuit device;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Insulating film, 3 ... 1st wiring, 4 ... 1st interlayer insulating film, 6 ... Connection hole, 7 ... Connection wiring, 9 ... 2nd interlayer insulating film, 11 ... 2nd Wiring.

Claims (3)

[Claims] 1. A step of forming a first wiring on a main surface of a semiconductor substrate, and a step of forming a first interlayer film in which a film thickness on the first wiring is smaller than a film thickness of the first wiring. The step of forming in the upper layer of the first wiring, and the photolithography in the first interlayer film on the first wiring, a connection hole having an inner diameter larger than the depth and exposing the surface of the first wiring. Forming by a technique and an etching technique, a second conductive film forming a connection wiring is formed on an upper layer of the first interlayer film, and the second conductive film is passed through the connection hole to form the first conductive film. A step of connecting to a wiring, a step of patterning the second conductive film by a photolithography technique and an etching technique to leave a connection wiring on the connection hole, and a step of forming a connection wiring in a region other than the connection wiring. Second interlayer film is formed, and the surface of the connection wiring and the second layer are formed. A semiconductor integrated circuit device comprising: a step of substantially matching the surfaces of the interlayer films; and a step of forming a second wiring connected to the connection wiring on an upper layer of the second interlayer film. Production method. 2. The semiconductor integrated circuit device according to claim 1, wherein each of the first wiring, the connection wiring, and the second wiring is formed mainly of an aluminum film or an aluminum alloy film. Manufacturing method. 3. The film thickness of the second conductive film forming the connection wiring is thicker than the depth of the connection hole formed in the first interlayer film. Alternatively, the method for manufacturing the semiconductor integrated circuit device according to claim 2.