JPH11214513A - Wiring structure of integrated circuit, and wiring formation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide wiring structure which is low in resistance at a connection and easy of manufacturing. SOLUTION: A first insulating film 16 is made, covering a connection to be covered, on a substrate 10, and then a connection hole is made in the insulating film 16, corresponding to the connection to be connected. A barrier layer, an Al metallic layer, and a reflection preventive layer are stacked in order, and then these stacked layers are patterned to form a plug 24 mainly composed of Al metal projecting from a connection hole. A second insulating film 26 is formed, covering the insulating film 16 and the plug 24, and then, the insulating film is etched back until the plug 24 is exposed. That is, a wiring layer 32 leading to the plug 24 is made by patterning the stacked layers after accumulating the Al alloy layer 28a and the reflection preventive layer 30a in order.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure and a wiring forming method for an integrated circuit such as an LSI, and more particularly to a plug mainly composed of an Al (aluminum) metal so as to protrude from a connection hole provided in a first insulating film. And a wiring layer formed so as to be connected to the plug via the second insulating film, thereby realizing a wiring structure with low resistance at the connection portion and easy manufacture. In this specification, the Al-based metal means Al or an Al alloy.

[0002]

2. Description of the Related Art Hitherto, as a method for forming wiring of an integrated circuit such as an LSI, the method shown in FIGS. 10 to 12 or FIGS.

In a process shown in FIG. 10, a field insulating film 2 of silicon oxide or the like is formed on a surface of a semiconductor substrate 1 made of, for example, silicon by a selective oxidation method.
The impurity doped region 3 is formed by an ion implantation method or the like corresponding to the element hole of FIG. Then, an insulating film 4 of silicon oxide or the like is formed on the upper surface of the substrate by a CVD (Chemical Vapor Deposition) method or the like, and the insulating film 4 reaches a part of the impurity doped region 3 by photolithography and dry etching. A connection hole 4a is formed. After this,
An Al alloy layer 6 is formed by a sputtering method via a barrier layer 5 such as a TiN / Ti (Ti lower layer) laminate.

[0004] Next, in the step of FIG.
The 1 alloy layer 6 is fluidized to fill the connection holes 4a with the Al alloy layer 6, thereby improving the flatness of the Al alloy layer 6. As another method for obtaining the Al alloy layer 6 as shown in FIG.
There is a method of heating the substrate when sputtering the alloy, or a method of continuing the sputtering while heating the substrate from the state of FIG.

Next, in the step of FIG. 12, the barrier layer 5 and the Al layer are formed by photolithography and dry etching.
The lamination of the alloy layer 6 is patterned to form a wiring layer 6A including the remaining portion 5a of the barrier layer 5 and the remaining portion 6a of the Al alloy layer 6. The wiring layer 6A is connected to the impurity-doped region 3 via the connection hole 4a.

In FIGS. 13 to 15, the same parts as those in FIGS. 10 to 12 are denoted by the same reference numerals, and the detailed description will be omitted. In the step shown in FIG. 13, a W (tungsten) layer 8 is formed on the upper surface of the substrate by a blanket CVD method via an adhesion layer 7 such as a TiN / Ti laminate. The W layer 8 is formed so as to fill the connection hole 4a.

Next, in the step of FIG. 14, the W layer 8 is etched back until the insulating film 4 is exposed, and a part of the W layer 8 is left in the connection hole 4a. Is formed.

Thereafter, in the step shown in FIG.
A wiring material layer such as an alloy is deposited. Then, the wiring layer 9 including the remaining portion 7a of the adhesion layer 7 and the remaining portion 9a of the wiring material layer is formed by patterning the lamination of the adhesion layer 7 and the attached wiring material layer according to a desired wiring pattern. The wiring layer 9 includes a plug 8a and a remaining adhesion layer 7b in the connection hole 4a.
And is connected to the impurity-doped region 3.

[0009]

Problems to be Solved by the Invention FIGS.
According to the method described above, when the aspect ratio of the connection hole (the ratio D / R of the depth D to the diameter R) increases with the miniaturization of the wiring,
It becomes difficult to form the connection hole with high dimensional accuracy. Also,
If a normal sputtering method is used to form the barrier layer 5, the sputter atoms do not reach the bottom of the connection hole having a large aspect ratio, and the bottom coverage is reduced. Therefore, it has been proposed to use a sputtering method with good bottom coverage, such as a collimated sputtering method or a long throw sputtering method. However, these sputtering methods have a low film formation rate and cause a decrease in throughput.

In the process of heating and fluidizing an Al-based metal during or after sputtering, sufficient embedding cannot be expected if the aspect ratio of the connection hole becomes large to some extent.

Therefore, the method of FIGS. 10 to 12 has a problem that it is not easy to form a wiring structure having a connection hole with a high aspect ratio with a high yield.

On the other hand, according to the methods shown in FIGS. 13 to 15, there is a problem similar to that described above with respect to the barrier layer 5 when the adhesion layer 7 is formed. That is, when an adhesion layer is formed in a connection hole with a large aspect ratio using a normal sputtering method, the bottom coverage is reduced.

[0013] In addition, since W as a plug material has a higher resistivity than an Al-based alloy, the resistance of a connection portion formed of a W plug increases.

Therefore, the method shown in FIGS. 13 to 15 has a problem that it is not easy to form a wiring structure having a low-resistance connection part with high yield.

An object of the present invention is to provide a novel wiring structure which has a low-resistance connection portion and can be easily manufactured.

Another object of the present invention is to provide a novel wiring forming method capable of forming a wiring structure having a low-resistance connection portion with high yield.

[0017]

According to the present invention, there is provided an integrated circuit wiring structure comprising: a substrate having a portion to be connected on one main surface;
A first insulating film formed so as to cover the one main surface, wherein the first insulating film has a connection hole reaching the connected portion;
An Al-based metal-based conductive plug that fills the connection hole and protrudes from the connection hole, the plug being connected to the connected portion at the bottom of the connection hole, and the top of the plug is exposed. A second insulating film formed so as to cover the first insulating film, and a wiring layer formed on the second insulating film and connected to the plug.

According to the wiring structure of the integrated circuit according to the present invention, the wiring layer formed on the second insulating film is made of a conductive material mainly composed of an Al-based metal penetrating through the lamination of the first and second insulating films. Is connected to the connected portion of the substrate via a plug having a characteristic. Since the Al-based metal such as Al or an Al alloy has a smaller resistivity than W, the resistance of the connecting portion formed of the plug is reduced. In addition, since the insulating film serving as the base of the wiring layer has a structure in which the second insulating film is overlapped with the first insulating film provided with the connection holes and the plugs, a thin first insulating film may be used. This facilitates formation of connection holes and plugs.

According to the wiring forming method of the present invention, there is provided a step of forming a first insulating film on one main surface of a substrate so as to cover a connected portion, and forming a connection hole reaching the connected portion with the first insulating film. Forming a film, and forming a conductive material layer mainly composed of an Al-based metal layer over the first insulating film so as to be connected to the portion to be connected at the bottom of the connection hole and to fill the connection hole. Forming a conductive plug consisting of a remaining portion of the conductive material layer by patterning the conductive material layer and leaving a part of the conductive material layer in a form protruding from the connection hole. Forming a second insulating film covering the plug and the first insulating film, and thinning the second insulating film until the top of the plug is exposed to form the second insulating film. Leaving a portion overlapping the first insulating film; It is intended to include a step of forming a wiring layer to be connected to the plug on the remaining portion of the film.

According to the wiring forming method of the present invention, the first
Since a thin insulating film can be used, a connection hole having a small aspect ratio can be formed in the first insulating film. Therefore, it is easy to form the connection hole with high dimensional accuracy, and it is easy to sufficiently fill the connection hole with an Al-based metal.

In the step of forming a conductive material layer mainly composed of an Al-based metal layer, a conductive barrier layer is formed by covering the connection hole and the first insulating film before forming the Al-based metal layer. Is also good. When forming the barrier layer, since the aspect ratio of the connection hole is small, it is not necessary to use a special sputtering method such as a collimated sputtering method, and good bottom coverage can be obtained by a normal sputtering method.

In the step of forming the conductive material layer, the Al-based metal layer may be heated and fluidized during or after formation.
By doing so, the flatness of the Al-based metal layer is improved, so that the patterning accuracy is improved when patterning the conductive material layer. After the Al-based metal layer is formed, a conductive anti-reflection layer may be formed to cover the Al-based metal layer.
This improves the patterning accuracy when patterning the conductive material layer.

When the conductive plug is formed by patterning the conductive material layer, the first insulating film serves as a substrate protective film and an etching stopper, so that the patterning can be performed smoothly. As the conductive plug, a low-resistance plug mainly composed of an Al-based metal can be obtained.

[0024]

1 to 9 show a wiring forming method according to an embodiment of the present invention. Steps (1) to (9) corresponding to the respective drawings will be sequentially described.

(1) A field insulating film 12 such as silicon oxide is formed on the surface of a semiconductor substrate 10 made of, for example, silicon by a selective oxidation method or the like. And the insulating film 1
Impurity-doped regions 14 are formed by ion implantation or the like corresponding to the two element holes.

Next, the impurity doped region 14 and the insulating film 1
2 to cover the insulating film 16 such as silicon oxide by CVD.
It is formed by a method or the like. The insulating film 16 corresponds to the insulating film 26 shown in FIG.
5 and protects the substrate surface from dry etching in the plug forming step of FIG. 5, and may have a thickness of about 1/2 of a normal thickness, for example, 100 to 4
It can be as thick as 00 nm.

(2) A connection hole 16a reaching a part of the impurity doped region 14 is formed in the insulating film 16 by well-known photolithography and dry etching. Insulating film 16
Is thin, the aspect ratio of the connection hole 16a is reduced, and the connection hole 16a can be formed with high dimensional accuracy.

(3) A barrier layer 18 is formed to cover the inner surface of the connection hole 16a and the insulating film 16 by a sputtering method. As the barrier layer 18, for example, a T layer having a thickness of 10 to 20 nm is used.
The i-layer has a thickness of 50-100 nm of TiN (or TiO
N) It is possible to form a laminate in which layers are stacked.

Since the aspect ratio of the connection hole 16a is small, it is not necessary to use a special sputtering method such as a collimating sputtering method or a long throw sputtering method, and a good bottom coverage can be obtained by using a normal sputtering method. The barrier layer 18 can be formed. In addition, the ordinary sputtering method has a higher film forming rate than the collimated sputtering method or the long throw sputtering method, so that the throughput is improved.

Next, an Al alloy layer 20 is formed at room temperature by covering the barrier layer 18 by a sputtering method. Al alloy layer 20
For example, Al-C having a thickness of 300 to 400 nm
u or an Al-Si-Cu alloy layer can be formed. At this time, a recess 20a is formed in the Al alloy layer 20 corresponding to the connection hole 16a.

(4) Heat treatment (reflow treatment)
The connection hole 16a is filled by fluidizing the alloy layer 20 (the concave portion 2).
Oa is eliminated) and the flatness of the Al alloy layer 20 is improved.
In order to obtain the Al alloy layer 20 as shown in FIG. 4, a method of performing sputtering while heating the substrate, a method of performing sputtering at room temperature followed by sputtering while heating the substrate (cold-
Hot sputtering) may be used.

Next, a conductive anti-reflection layer 22 is formed to cover the Al alloy layer 20 by a sputtering method. As the antireflection layer 22, for example, TiN having a thickness of 50 to 200 nm is used.
(Or TiON) layer can be formed.

(5) A conductive material layer comprising a laminate of the barrier layer 18, the Al alloy layer 20, and the antireflection layer 22 is patterned by photolithography and dry etching, and a part of the conductive material layer corresponds to the connection hole 16a. The conductive plug 24 made of the remaining portion of the conductive material layer.
To form At this time, since the insulating film 16 functions as an etching stopper, the substrate surface is protected from etching.

In the photolithography process, the flatness of the Al alloy layer 20 is improved and the anti-reflection layer 2
2 suppresses light reflection from the Al alloy layer 20, so that a resist layer as an etching mask can be formed with high dimensional accuracy, and patterning accuracy of the conductive material layers including the layers 18, 20, and 22 is improved. Accordingly, a fine pattern plug can be easily formed as the plug 24.

The conductive plug 24 is formed so as to protrude from the connection hole 16a, and is connected to the impurity doped region 14 at the bottom of the connection hole 16a. The plug 24 is connected to the barrier layer 1
8 has a remaining portion 18a, a remaining portion 20a of the Al alloy layer 20, and a remaining portion 22a of the antireflection layer 22, and has a low resistance mainly composed of an Al alloy.

(6) An insulating film 26 is formed to cover the plug 24 and the insulating film 16. The insulating film 26 may be a single layer or a stacked layer, but is preferably formed with good flatness. As an example, after a hydrogen silsesquioxane resin film is formed into a flat shape with a thickness of 300 to 400 nm by a spin coating method, a heat treatment for preceramic formation and ceramic formation is performed to form a ceramic silicon oxide film. Can be formed. On this silicon oxide film, a silicon oxide film or the like may be formed by a CVD method as needed.

As another method of forming the insulating film 26,
After a BPSG (boron-phosphorus-silicate glass) film is formed by a CVD method, a method of forming a flat SOG (spin-on glass) film on the BPSG film by a spin coating method may be used. In this case, a silicon oxide film or a PSG film may be formed on the SOG film by CVD if necessary.
A (phosphorus-silicate glass) film or the like may be formed.

(7) Insulating film 26 by etch-back process
Is removed flatly until the top of the plug 24 is exposed, and the insulating film 26 is left in a portion overlapping the insulating film 16. As a method for removing the insulating film 26 in a flat shape, a CMP (chemical mechanical polishing) process may be used, or a constant velocity etch-back process may be used. In constant velocity etchback processing,
For example, a resist layer is formed in a flat shape by a spin coating method on an insulating film 26 of BPSG or the like formed in a non-flat shape by a CVD method. Then, the stack of the insulating films 26 is etched back.

(8) An Al alloy layer 28 of Al—Cu or the like is formed by sputtering to cover the plug 24 and the insulating film 26. Then, the anti-reflection layer 30 covering the Al alloy layer 28 is formed.
To form The anti-reflection layer 30 is the same as the anti-reflection layer 22 described above.
Can be formed in the same manner as described above.

(9) The wiring material layer composed of the laminated layer of the Al alloy layer 28 and the antireflection layer 30 is patterned by photolithography and dry etching to leave a part of the wiring material layer so as to be connected to the plug 24. Thus, the wiring layer 32 including the remaining portion of the wiring material layer is formed. The wiring layer 32 includes a remaining portion 28a of the Al alloy layer 28 and a remaining portion 30a of the antireflection layer 30, and has a low resistance mainly composed of an Al alloy.

The present invention is not limited to the above embodiment, but can be implemented in various modified forms. For example, an Al layer may be used instead of the Al alloy layers 20 and 28. Further, the wiring structure and the wiring forming method according to the present invention are not limited to the wiring directly connected to the connected portion made of a semiconductor such as silicon as shown in the above-described embodiment, but may be connected to such wiring. It can also be applied to upper layer wiring. In this case, the plug (corresponding to the plug 24) of the upper wiring is connected to a part (connected portion) of the lower wiring.

[0042]

As described above, according to the present invention, the wiring base film is constituted by a laminated structure in which the second insulating film is laminated on the first insulating film, and an Al-based metal mainly penetrating the laminated structure. Since the wiring layer on the second insulating film is connected to the connected portion of the substrate via the conductive plug, a wiring structure with low resistance of the connecting portion and easy manufacture can be realized.

According to the wiring forming method of the present invention, a connection hole having a small aspect ratio is formed in the first insulating film, and a conductive material layer mainly composed of an Al-based metal layer is filled so as to fill the connection hole. Is formed, and the conductive plug is formed by patterning the conductive material layer. Therefore, it is possible to easily form the connection hole and bury the connection hole, and to smoothly perform the patterning of the conductive material layer. As a result, a wiring structure having a low-resistance plug (connection portion) can be formed with high yield. Since the height of the low-resistance plug can be easily increased by increasing the thickness of the conductive material layer, a wiring structure equivalent to forming a connection hole having a high aspect ratio can be easily formed.

In addition, when a conductive material layer mainly composed of an Al-based metal layer is formed, a conductive barrier layer can be formed by a normal sputtering method as a lower layer of the Al-based metal layer, thereby improving the throughput. If a conventional sputtering apparatus is modified to be a collimated sputtering apparatus or a long throw sputtering apparatus, or if a tungsten CVD apparatus is installed, a new investment is required.
A fine wiring process of about 0.35 μm can be realized by using a sputtering apparatus used in a process of about m.

Further, when the conductive material layer is formed on the first insulating film so as to cover the connection holes, the Al-based metal layer is heated and fluidized to improve the flatness. When an anti-reflection layer is formed on the conductive material layer, the patterning accuracy when patterning the conductive material layer is improved, and a fine pattern plug can be easily formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a substrate showing an insulating film forming step in a wiring forming method according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a substrate showing a connection hole forming step following the step of FIG. 1;

FIG. 3 is a cross-sectional view of a substrate showing a conductive material layer forming step following the step of FIG. 2;

FIG. 4 is a cross-sectional view of the substrate showing an Al alloy reflow step and an antireflection layer forming step following the step of FIG. 3;

FIG. 5 is a cross-sectional view of the substrate showing a plug forming step following the step of FIG. 4;

FIG. 6 is a cross-sectional view of a substrate showing an insulating film forming step following the step of FIG. 5;

FIG. 7 is a cross-sectional view of the substrate showing an etch-back step following the step of FIG. 6;

8 is a cross-sectional view of the substrate showing a wiring material layer forming step following the step of FIG. 7;

FIG. 9 is a cross-sectional view of the substrate showing a wiring patterning step following the step of FIG. 8;

FIG. 10 illustrates an example of a conventional method for forming a wiring by using Al.
FIG. 3 is a cross-sectional view of a substrate illustrating an alloy layer forming step.

FIG. 11 is a cross-sectional view of the substrate showing an Al alloy reflow step following the step of FIG. 10;

FIG. 12 is a substrate cross-sectional view showing a wiring patterning step that follows the step of FIG. 11;

FIG. 13 shows a conventional example of a conventional method of forming a wiring W
It is a board | substrate sectional drawing which shows a layer formation process.

FIG. 14 is a cross-sectional view of the substrate showing an etch-back step following the step of FIG.

FIG. 15 is a substrate cross-sectional view showing a wiring layer forming step following the step in FIG. 14;

[Explanation of symbols]

10: semiconductor substrate, 12, 16, 26: insulating film, 14:
Impurity doped region, 18: barrier layer, 20, 28: Al
Alloy layer, 22, 30: anti-reflection layer, 24: plug, 3
2: Wiring layer.

Claims (5)

[Claims] 1. A substrate having a portion to be connected on one main surface, and a first insulating film formed to cover the one main surface, wherein a connection hole reaching the portion to be connected is formed. An Al-based metal-based conductive plug that fills the connection hole and protrudes from the connection hole, the plug being connected to the connected part at the bottom of the connection hole; An integrated circuit comprising: a second insulating film formed so as to cover the first insulating film so as to be exposed; and a wiring layer formed on the second insulating film and connected to the plug. Wiring structure. A first main surface of the substrate covering a portion to be connected;
Forming a connecting hole reaching the connected portion in the first insulating film; and forming a conductive material layer mainly composed of an Al-based metal layer on the bottom of the connecting hole. Forming the first insulating film so as to cover the first insulating film so as to be connected to the connection portion and fill the connection hole; and patterning the conductive material layer to project a part of the conductive material layer from the connection hole. Forming a conductive plug made of the remaining portion of the conductive material layer by leaving the plug, and forming a second insulating film covering the plug and the first insulating film; Thinning the second insulating film until the top is exposed, and leaving the second insulating film in a portion overlapping the first insulating film; and forming the second insulating film on the remaining portion of the second insulating film. Forming a wiring layer so as to be connected to the plug. Line forming method. 3. In the step of forming the conductive material layer, a conductive barrier layer is formed to cover an inner surface of the connection hole and the first insulating film before forming the Al-based metal layer. 3. The method according to claim 2, wherein a laminate including a barrier layer and the Al-based metal layer is used as the conductive material layer. 4. In the step of forming the conductive material layer, the Al-based metal layer is heated and fluidized during or after the formation of the Al-based metal layer to improve the flatness of the Al-based metal layer. The method for forming a wiring according to claim 2. 5. In the step of forming the conductive material layer, after forming the Al-based metal layer, a conductive anti-reflection layer is formed to cover the Al-based metal layer, and the Al-based metal layer and the reflective layer are formed. 3. The wiring forming method according to claim 2, wherein a laminate including a prevention layer is used as the conductive material layer.