JPS62219541A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62219541A JPS62219541A JP6130586A JP6130586A JPS62219541A JP S62219541 A JPS62219541 A JP S62219541A JP 6130586 A JP6130586 A JP 6130586A JP 6130586 A JP6130586 A JP 6130586A JP S62219541 A JPS62219541 A JP S62219541A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- pad
- opening
- contact
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 15
- 239000011574 phosphorus Substances 0.000 claims abstract description 15
- 230000002093 peripheral effect Effects 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 13
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 12
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 230000008021 deposition Effects 0.000 abstract description 4
- 239000004033 plastic Substances 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000005536 corrosion prevention Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000002991 molded plastic Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
素子の形成された基板上に、燐を含む第一の絶縁膜およ
び第一の絶縁膜上の燐を含まぬ第二の絶縁膜を具える半
導体装置における上記絶縁膜の配線導出用パッドに対す
る開口部において、第二の絶縁膜を開口の周縁部全域で
パッドの表面に接しせしめることにより、
外部から侵入する水と第一の絶縁膜に含まれる燐との作
用によるパッドの腐食を防止したものである。[Detailed Description of the Invention] [Summary] A semiconductor device comprising a first insulating film containing phosphorus and a second insulating film not containing phosphorus on the first insulating film on a substrate on which an element is formed. By bringing the second insulating film into contact with the surface of the pad throughout the periphery of the opening in the insulating film for the wiring lead-out pad, water entering from the outside and phosphorus contained in the first insulating film are prevented. This prevents the pad from corroding due to the action of
本発明は、素子の形成された基板上に、燐を含む第一の
絶縁膜および第一の絶縁膜上の燐を含まぬ第二の絶縁膜
を具える半導体装置に係り、例えばプラスチックパッケ
ージ半導体装置などにおける上記絶縁膜の配線導出用パ
ッドに対する開口部の構成に関す。The present invention relates to a semiconductor device comprising a first insulating film containing phosphorus and a second insulating film not containing phosphorus on the first insulating film on a substrate on which an element is formed, such as a plastic package semiconductor. The present invention relates to a configuration of an opening for a wiring lead-out pad of the insulating film in a device or the like.
半導体装置例えば半導体集積回路（ＩＣ）などは、素子
の形成された基板に対するパッシベーション技術の向上
から、モールドによるプラスチックパッケージを採用し
て製造コストの低減が図られている。2. Description of the Related Art Semiconductor devices, such as semiconductor integrated circuits (ICs), have been manufactured using molded plastic packages to reduce manufacturing costs due to improved passivation technology for substrates on which elements are formed.
このパッシベーション技術は、外部から侵入する水など
から基板を保護して半導体装置の特性が損なわれないよ
うにするものであり、基板−にに設けられた配線導出用
パノ１−の部分についても考慮される必要がある。This passivation technology protects the board from water entering from the outside and prevents the characteristics of the semiconductor device from being impaired.It also takes into consideration the wiring lead-out pano 1 provided on the board. need to be done.
第３図は、プラスチックパッケージ半導体装置における
素子の形成された基板トに設けられた配線導出用パッド
部分の従来構成例を示す側断面図である。FIG. 3 is a side cross-sectional view showing a conventional configuration example of a wiring lead-out pad portion provided on a substrate on which elements are formed in a plastic package semiconductor device.
同図において、１は素子の形成された基板、２はアルミ
ニウム（ＡＩ）の配線導出用バット、３は燐珪酸ガラス
（ＰＳＧ）の第一の絶縁膜、４は窒化シリコン（ＳｉＮ
）の第二の絶縁膜、３ａと４８は絶縁膜３と４のバット
２部分にそれぞれ設けられた開口、５はパッド２にボン
ディングされた金（Ａｕ）の接続ワイヤ、６はパッケー
ジを形成するプラスチック領域、である。In the figure, 1 is a substrate on which an element is formed, 2 is an aluminum (AI) wiring lead-out batt, 3 is a first insulating film made of phosphosilicate glass (PSG), and 4 is a silicon nitride (SiN
), 3a and 48 are openings provided in the butt 2 portions of the insulating films 3 and 4, 5 is a gold (Au) connection wire bonded to the pad 2, and 6 forms a package. This is the plastic area.
絶縁膜３は主として基板１に形成された素子を保護する
機能を有し、絶縁１＊４は主として水などが外部から侵
入するのをμ■止する機能を有してい開口３ａと４８は
、接続ワイー１〜５をパッド２にボンディングするため
の窓であり、絶縁膜３と４が堆積された後一括して形成
されている。従って絶縁膜３はパッド２に接し、絶縁膜
４はパノ１２から離れている。The insulating film 3 mainly has the function of protecting the elements formed on the substrate 1, the insulating film 1*4 mainly has the function of preventing water etc. from entering from the outside, and the openings 3a and 48 are This is a window for bonding the connection wires 1 to 5 to the pad 2, and is formed all at once after the insulating films 3 and 4 are deposited. Therefore, the insulating film 3 is in contact with the pad 2, and the insulating film 4 is separated from the pan 12.
〔発明が解決しようとする問題点〕
一般にプラスチックパッケージ半導体装置は、大気中に
含まれる水がプラスチックパッケージの表面からも侵入
するが特にリード端子とプラスチック領域の界面を伝っ
て侵入し易い。[Problems to be Solved by the Invention] In general, in a plastic packaged semiconductor device, water contained in the atmosphere enters from the surface of the plastic package, but particularly tends to enter through the interface between the lead terminal and the plastic region.
そしてこの水は、第３図図示の接続ワイヤ５の表面を伝
ってバット２の表面に達する。This water then reaches the surface of the bat 2 along the surface of the connecting wire 5 shown in FIG.
従って第３図図示構成の半導体装置では、上記水が開口
３ａの内面に達し絶縁膜３材料のＰＳＧに含まれる燐（
Ｐ）と反応して燐酸（Ｈ３ＰＯａ）となるので、アルミ
ニウムのバソ１−２が腐食されて信頼性が低下し甚だし
くは断線状態に至る問題を有する。Therefore, in the semiconductor device having the configuration shown in FIG. 3, the water reaches the inner surface of the opening 3a and phosphorus (
Since it reacts with P) to form phosphoric acid (H3POa), there is a problem that the aluminum batho 1-2 is corroded, resulting in decreased reliability and even disconnection.
ｒ問題点を解決するための手段〕
第１図は本発明第一の実施例における第３図図示相当部
分の側断面図である。全図を通し同−省号は同一材料同
一機能の対象物を示す。Means for Solving Problems] FIG. 1 is a side sectional view of a portion corresponding to that shown in FIG. 3 in the first embodiment of the present invention. Throughout the drawings, the same ministry name indicates objects with the same material and the same function.
上記問題点は、第１図に示される如く、素子の形成され
た基板ｌトに、接続ワイヤ５のホンディングされた配線
導出用バット２と、共にバット２の部分に開口３ａまた
は４ａを有する燐を含む第一の絶縁膜３および第一の絶
縁Ｂ＊３−１−の燐を含まぬ第二の絶縁膜４とを具え、
第二の絶縁膜４がその開口４ａの周縁部全域でパッド２
の表面に接している本発明のプラスチックパッケージ半
導体装置によって解決される。The above problem is that, as shown in FIG. 1, the wiring lead-out bat 2 on which the connecting wire 5 is bonded to the substrate on which the element is formed has an opening 3a or 4a in the bat 2. A first insulating film 3 containing phosphorus and a second insulating film 4 not containing phosphorus of the first insulation B*3-1-,
The second insulating film 4 covers the pad 2 over the entire peripheral edge of the opening 4a.
The problem is solved by the plastic packaged semiconductor device of the present invention, which is in contact with the surface of the semiconductor device.
この構成の半導体装置では、先に述べた如くバソｌ”
２の表面に達した水は、絶縁膜３部への侵入をパッド２
に接している絶縁膜４にμ■止されて燐酸になることが
ない。In a semiconductor device with this configuration, as mentioned earlier, the baso
The water that reaches the surface of pad 2 is prevented from entering the insulation film 3.
The insulating film 4, which is in contact with the phosphoric acid, prevents the phosphoric acid from being blocked by the insulating film 4.
かくしてパッド２の腐食が防止されてその腐食に起因す
る信頼性の低下を抑えることが出来る。Corrosion of the pad 2 is thus prevented, and deterioration in reliability due to the corrosion can be suppressed.
以下、第１図および本発明第二の実施例における第３図
図示相当部分を示す第２図の側断面図を用い実施例につ
いて説明する。Hereinafter, an embodiment will be described using FIG. 1 and a side sectional view of FIG. 2 showing a portion corresponding to that shown in FIG. 3 in a second embodiment of the present invention.
第１図に示す第一の実施例では、第二の絶縁膜４の開口
４ａの大きさを第一の絶縁膜３の開口３ａより小さくし
、両者の間の領域で絶縁膜４がパッド２に接している。In the first embodiment shown in FIG. 1, the size of the opening 4a of the second insulating film 4 is made smaller than the opening 3a of the first insulating film 3, and the insulating film 4 covers the pad 2 in the area between them. is in contact with
パッド２が通常の配列をなす場合、絶縁膜４がパッド２
に接する幅を１０μｍ以１−にすることが可能である。When the pads 2 are in a normal arrangement, the insulating film 4
It is possible to make the width in contact with 10 μm or more.
この構成は、パッド２の形成、絶縁膜３の堆積、開口３
ａの形成、絶縁１１ｉ４の堆積、開口４ａの形成、の順
にした工程により製造可能である。This configuration includes the formation of the pad 2, the deposition of the insulating film 3, and the opening 3.
It can be manufactured by the steps of forming the insulator 11i4, depositing the insulator 11i4, and forming the opening 4a in this order.
このように構成された半導体装置では、パッド２の部分
で外部から侵入した水が燐酸とならずしてパッド２の腐
食が防Ｉトされることは、先に説明した通りである。As described above, in the semiconductor device configured in this manner, water that has entered the pad 2 from the outside does not turn into phosphoric acid, thereby preventing corrosion of the pad 2.
第２図に示す第二の実施例では、パット２を基板１トの
配線と繋がる下パッド２ａと単独の十バッド２ｂ （材
料は何れもアルミニウム）の２層構成にし、トパソＦ２
ｂの周縁部が第一の絶縁膜３と第二の絶縁膜４との間に
挿入されている。In the second embodiment shown in FIG. 2, the pad 2 has a two-layer structure consisting of a lower pad 2a connected to the wiring on the board 1 and a single pad 2b (all made of aluminum), and the top pad 2 is made of aluminum.
The peripheral edge portion b is inserted between the first insulating film 3 and the second insulating film 4.
下パッド２ａおよびドパノド２ｂの厚さは、それぞれ例
えば０．５〜１μｍ程度および１μｍ程度で良く、バッ
ド２が通常の配列をなす場合、絶縁１！４がパッド２に
接する幅を３０μｍ以トにすることが可能である。The thickness of the lower pad 2a and the dopant pad 2b may be, for example, about 0.5 to 1 μm and about 1 μm, respectively, and when the pads 2 are arranged in a normal arrangement, the width where the insulation 1!4 contacts the pad 2 should be 30 μm or more. It is possible to do so.
この構成は、下パッド２ａの形成、絶縁膜３の堆積、開
口３ａの形成、上パッド２ｂの形成、絶縁１！ｉ４の堆
積、開口４ａの形成、の順にした工程により製造可能で
ある。This configuration includes the formation of the lower pad 2a, the deposition of the insulating film 3, the formation of the opening 3a, the formation of the upper pad 2b, and the insulation 1! It can be manufactured by the steps of depositing i4 and forming the opening 4a in this order.
この第二実施例は、製造が第一の実施例より複雑になる
が、絶縁膜４のパッド２に接する幅が第一の実施例より
大きくすることが出来て、バッド２に対する腐食防止に
繋がる水の侵入１！１１．＋ト機能が強化される。This second embodiment is more complicated to manufacture than the first embodiment, but the width of the insulating film 4 in contact with the pad 2 can be made larger than in the first embodiment, which leads to corrosion prevention of the pad 2. Water intrusion 1!11. +To function will be strengthened.
なお上記実施例では第二の絶縁膜４の材料を窒化シリコ
ンにしたが、その材料は燐を含まないものであるならば
他の材料例えば二酸化シリコン（Ｓｉ０２）などであっ
ても良い。Although silicon nitride is used as the material for the second insulating film 4 in the above embodiment, other materials such as silicon dioxide (Si02) may be used as long as the material does not contain phosphorus.
また上記実施例ではプラスチックパッケージ半導体装置
の場合を述べたが、セラミ’７クバソケージ半導体装置
などの場合であっても、何かの事情でパッケージ内に水
が侵入した際に本発明が有効であることは容易に理解出
来る。Furthermore, although the above embodiment describes the case of a plastic package semiconductor device, the present invention is effective even in the case of a ceramic '7 cage semiconductor device, etc., when water enters the package for some reason. This is easy to understand.
以上説明したように本発明の構成によれば、素子の形成
された基板上に、燐を含む第一の絶縁膜および第一の絶
縁股上の燐を含まぬ第二の絶縁膜を具える半導体装置に
おいて、基板トに設けられた配線導出用バッドに対する
外部から侵入する水と第一の絶縁膜に含まれる燐との作
用による腐食を防止することが出来て、その腐食に起因
する信頼性の低下を抑える効果がある。As explained above, according to the configuration of the present invention, a semiconductor device includes a first insulating film containing phosphorus and a second insulating film not containing phosphorus on the first insulating layer, on a substrate on which an element is formed. In the device, it is possible to prevent corrosion caused by the action of water entering from the outside and phosphorus contained in the first insulating film on the wiring lead-out pad provided on the board, and to reduce the reliability caused by the corrosion. It has the effect of suppressing the decline.
第１図は本発明第一の実施例の要部側断面図、第２図は
本発明第二の実施例の要部側断面図、第３図は従来例の
要部側断面図、
である。
図において、
１は基板、
２は配線導出用パッド、
２ａは下パッド、
２ｂは上パッド、
３は第一の絶縁膜、
３ａは３の開口、
４は第二の絶縁膜、
４ａは４の開口、
５は接続ワイヤ、
６はプラスチック領域、
である。
＄発明篇−の実施例の要部！則断面図
箋 １ 図
本発明第二の実施イ列の要部側断面図
第２図
従来弁ｊの要部側断面図
第 ３ 図Fig. 1 is a side sectional view of the main part of the first embodiment of the present invention, Fig. 2 is a side sectional view of the main part of the second embodiment of the invention, and Fig. 3 is a side sectional view of the main part of the conventional example. be. In the figure, 1 is a substrate, 2 is a wiring lead-out pad, 2a is a lower pad, 2b is an upper pad, 3 is a first insulating film, 3a is an opening in 3, 4 is a second insulating film, and 4a is an upper pad in 4. 5 is a connecting wire; 6 is a plastic area; The main part of the $ invention version - example! Figure 1: Side sectional view of the main part of the second embodiment of the present invention, Figure 2. Side sectional view of the main part of the conventional valve j.
Claims (1)
ボンディングされた配線導出用パッド（２）と、共に該
パッドの部分に開口（３ａ、４ａ）を有する燐を含む第
一の絶縁膜（３）および該第一の絶縁膜（３）上の燐を
含まぬ第二の絶縁膜（４）とを具え、該第二の絶縁膜（
４）がその上記開口（４ａ）の周縁部全域で該パッド（
２）の表面に接していることを特徴とする半導体装置。On the substrate (1) on which the element is formed, there is a wiring lead-out pad (2) to which the connection wire (5) is bonded, and a first layer containing phosphorus having openings (3a, 4a) in the pad portion. an insulating film (3) and a second insulating film (4) not containing phosphorus on the first insulating film (3);
4) covers the entire peripheral edge of the opening (4a).
A semiconductor device characterized by being in contact with the surface of 2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6130586A JPS62219541A (en) | 1986-03-19 | 1986-03-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6130586A JPS62219541A (en) | 1986-03-19 | 1986-03-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62219541A true JPS62219541A (en) | 1987-09-26 |
Family
ID=13167330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6130586A Pending JPS62219541A (en) | 1986-03-19 | 1986-03-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62219541A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03276602A (en) * | 1990-03-26 | 1991-12-06 | Murata Mfg Co Ltd | Noise filter |
| JPH0436230U (en) * | 1990-07-20 | 1992-03-26 | ||
| JP2023163403A (en) * | 2022-04-28 | 2023-11-10 | 日機装株式会社 | Semiconductor light-emitting element and method of manufacturing semiconductor light-emitting element |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5748247A (en) * | 1980-09-05 | 1982-03-19 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit device |
-
1986
- 1986-03-19 JP JP6130586A patent/JPS62219541A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5748247A (en) * | 1980-09-05 | 1982-03-19 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03276602A (en) * | 1990-03-26 | 1991-12-06 | Murata Mfg Co Ltd | Noise filter |
| JPH0436230U (en) * | 1990-07-20 | 1992-03-26 | ||
| JP2023163403A (en) * | 2022-04-28 | 2023-11-10 | 日機装株式会社 | Semiconductor light-emitting element and method of manufacturing semiconductor light-emitting element |
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