JPS6034256B2 - Manufacturing method for resin-encapsulated semiconductor devices - Google Patents
Manufacturing method for resin-encapsulated semiconductor devicesInfo
- Publication number
- JPS6034256B2 JPS6034256B2 JP59083702A JP8370284A JPS6034256B2 JP S6034256 B2 JPS6034256 B2 JP S6034256B2 JP 59083702 A JP59083702 A JP 59083702A JP 8370284 A JP8370284 A JP 8370284A JP S6034256 B2 JPS6034256 B2 JP S6034256B2
- Authority
- JP
- Japan
- Prior art keywords
- resin
- piq
- semiconductor substrate
- whole
- pads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229920005989 resin Polymers 0.000 claims abstract description 42
- 239000011347 resin Substances 0.000 claims abstract description 42
- 239000011248 coating agent Substances 0.000 claims description 11
- 238000000576 coating method Methods 0.000 claims description 10
- 229920006015 heat resistant resin Polymers 0.000 claims description 3
- 239000011247 coating layer Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 20
- 238000000034 method Methods 0.000 abstract description 5
- 229920001721 polyimide Polymers 0.000 abstract description 4
- 239000004642 Polyimide Substances 0.000 abstract description 3
- 239000002966 varnish Substances 0.000 abstract description 3
- 239000003822 epoxy resin Substances 0.000 abstract description 2
- 229920000647 polyepoxide Polymers 0.000 abstract description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 239000000463 material Substances 0.000 description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 238000007789 sealing Methods 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 2
- IZJSTXINDUKPRP-UHFFFAOYSA-N aluminum lead Chemical compound [Al].[Pb] IZJSTXINDUKPRP-UHFFFAOYSA-N 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 125000001301 ethoxy group Chemical group [H]C([H])([H])C([H])([H])O* 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000005871 repellent Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Formation Of Insulating Films (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、封止型半導体装置の製法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a sealed semiconductor device.
従来、樹脂封止型半導体装置として、半導体素子が水分
によって特性劣化を生じないよう半導体素子表面をはつ
水性樹脂等でおおし、、さらに素子全体をェポキシ樹脂
等の絶縁性樹脂でおおう構造が知られている（例えば実
公昭４１−２２５９０号公報）。Conventionally, resin-sealed semiconductor devices have a structure in which the surface of the semiconductor element is covered with a water-repellent resin or the like to prevent the characteristics of the semiconductor element from deteriorating due to moisture, and the entire element is then covered with an insulating resin such as epoxy resin. It is known (for example, Japanese Utility Model Publication No. 41-22590).
ところで、この種の樹脂封止型半導体装置においては、
耐湿一性は優れているが、特に高温動作時の特性におい
てリーク不良等の問題があった。By the way, in this type of resin-sealed semiconductor device,
Although the moisture resistance is excellent, there are problems such as leakage failure, especially in the characteristics during high-temperature operation.
この原因としては、チップコート剤として使用されるシ
ＩＪコン系樹脂の○又はＯＣ２日３（ェトキシ基）が高
温中で分解し活発に運動し、その際素子に加えられたバ
イアスによってこれらの０又はＯＣ２日５が、電極間又
は配線間にバイアスを形成し、それによって電極間又は
配線間にリーク電流が発生するためと考えられる。本発
明者は、この高温でのりーク電流を防止するために、チ
ップコートとして、例えばＰＴＶ等のＳｉ系樹脂の他に
、新たな材料を検討した所、近年開発されたＰＩＱ樹脂
（ポリィミドィソィンドロキナゾリンジオン：Ｐｏｌｙ
ｉｍｉｄｅ ｉｓｏｉｎｄｒｏｑｕ−ｌｎａｚｏｌｉｎ
ｄｉｏｎｅ）が素子の保護膜として、特に高温動作時に
おけるリーク電流に対して有利であることがわかった。The reason for this is that the ○ or OC2day3 (ethoxy group) of the silicone resin used as a chip coating agent decomposes at high temperatures and moves actively, and at that time, the bias applied to the element causes these 0 Alternatively, it is considered that the OC2 day 5 forms a bias between the electrodes or between the wirings, which causes leakage current to occur between the electrodes or between the wirings. In order to prevent leakage current at high temperatures, the present inventor investigated new materials for the chip coat, in addition to Si-based resins such as PTV, and discovered that the recently developed PIQ resin (polyimide resin) Isoindroquinazolinedione: Poly
imide isoindroqu-lnazolin
dione) was found to be effective as a protective film for devices, especially against leakage current during high-temperature operation.
そこで、まず、このＰＩＱ樹脂を、チップコートとして
使用することを本願発明者は考えた。ところが、このＰ
ＩＱ樹脂は半導体素子、特に、素子上の絶縁膜との接着
性が、封止用の樹脂との接着性よりも悪いため、チップ
コート材として、ＰＩＱ樹脂のみを使用した場合ＰＩＱ
樹脂の素子間に「剥離」を生じ、その間隙から水分が素
子表面にまで侵透し、半導体素子の耐湿性をそこねる欠
点があった。本発明の目的は、高信頼度の封止型半導体
装置を得ることにある。Therefore, the inventor of the present application first considered using this PIQ resin as a chip coat. However, this P
IQ resin has worse adhesion to semiconductor elements, especially the insulating film on the element, than to sealing resin, so if only PIQ resin is used as a chip coating material, PIQ
This has the disadvantage that "peeling" occurs between the resin elements, and moisture penetrates through the gaps to the element surface, impairing the moisture resistance of the semiconductor element. An object of the present invention is to obtain a highly reliable sealed semiconductor device.
まず、本発明の方法によって得られた具体的な構造を示
す。First, a specific structure obtained by the method of the present invention will be shown.
第１図に示すように、複数の素子領域２，３，４，５が
形成された半導体基体１の主表面上に、これら複数の素
子領域と電気的に接続するように形成された電極部材の
一部、すなわちボンディングパッド部８を残すように、
素子領域上にＰＩＱ樹脂７が塗布されている。これは後
述するように半導体ウェハ状態で塗布される。さらに、
このＰＩＱ樹脂７におおし、、かつ、上記ボンディング
パッド部も含む半導体基体１の一主表面全体にわたって
Ｓｉ系樹脂の如きアンダーコート材９が形成されている
。このような半導体基体１は、タブリード１１上に固着
され、このタブリード１１の一部、外部取出し用リード
１２の一部及び、半導体基体１、Ｓｉ系のアンダーコー
ト材９、アルミニウムのリード線１０をおおつて、更に
他の封止用樹脂１３で封止され、半導体装置として完成
されている。次に本発明の封止方法を、第１図、第２図
ａ〜ｉに従い述べる。As shown in FIG. 1, an electrode member is formed on the main surface of a semiconductor substrate 1 on which a plurality of element regions 2, 3, 4, 5 are formed so as to be electrically connected to the plurality of element regions. , leaving a part of the bonding pad portion 8.
PIQ resin 7 is applied onto the element region. This is applied on a semiconductor wafer as described below. moreover,
An undercoat material 9 such as a Si-based resin is formed over the PIQ resin 7 and over the entire main surface of the semiconductor substrate 1 including the bonding pad portion. Such a semiconductor substrate 1 is fixed on a tab lead 11, and a part of this tab lead 11, a part of the external lead 12, the semiconductor substrate 1, a Si-based undercoat material 9, and an aluminum lead wire 10 are attached. Finally, it is further sealed with another sealing resin 13 to complete the semiconductor device. Next, the sealing method of the present invention will be described with reference to FIGS. 1 and 2 a to i.
まず、第１図及び第２図ａ〜ｃに示すように、ゥェハ状
態の半導体基板１中に、周知の技術により素子領域２，
３，４を複数個形成し、該素子領域２，３，４上にアル
ミニウム電極６及びアルミニウム配線１４を形成する。First, as shown in FIGS. 1 and 2 a to c, an element region 2,
A plurality of aluminum electrodes 3 and 4 are formed, and an aluminum electrode 6 and an aluminum wiring 14 are formed on the element regions 2, 3, and 4.
さらに、同図ａ，ｅを示すように、素子領域上相当部分
、いいかえれば、ボンディングパッド部８以外の場所に
、ＰＩＱ樹脂７を約４ｒ程度塗布形成し、ボンディング
パッド部８のＰＩＱ樹脂７を選択的にエッチング処理し
て取りのぞく、そして、ＰＩＱ樹脂７が塗布された半導
体基板１をべレット分割するため、同図ｆに示すように
ダイシングを行う。次に、同図ｇ，ｈに示すように、タ
ブリード１１へべレツト付けを行ない、そのあと、ベレ
ット状態の半導体基板１のボンディングパッド部８と、
外部取出し用１」−ド１２とを、アルミニウム線１０で
、ワイヤボンディングにより接続する。そして、半導体
基板１の一主面上全面を、Ｓｉ系のラバー、ゲル、ワニ
ス等のアンダーコート材９でチップコートする。そのあ
と、第２図ｉに示したように、Ｓｉ系及びェポキシ系の
封止用樹脂により、半導体基板１及びＳｉ系のチップコ
ート材９、タブリード１１の一部、外部取出し用リード
１２の一部及び、アルミニウム線１０を、完全に封止す
る。上言己方法によれば、特にＰＩＱ樹脂の如きポリア
ミド系の耐熱性樹脂を半導体ウヱハの状態で被覆し、電
極あるいは配線を保護している。Furthermore, as shown in Figures a and e, approximately 4r of PIQ resin 7 is applied to a corresponding portion of the element area, in other words, to a location other than the bonding pad portion 8, and the PIQ resin 7 of the bonding pad portion 8 is coated. The semiconductor substrate 1 coated with the PIQ resin 7 is selectively etched and removed, and dicing is performed as shown in FIG. Next, as shown in FIG.
The aluminum wire 10 is connected to the external lead 1'' by wire bonding. Then, the entire surface of one principal surface of the semiconductor substrate 1 is chip-coated with an undercoat material 9 such as Si-based rubber, gel, or varnish. Thereafter, as shown in FIG. 2i, the semiconductor substrate 1, the Si-based chip coating material 9, a part of the tab lead 11, and the external lead 12 are sealed with Si-based and epoxy-based sealing resin. and the aluminum wire 10 are completely sealed. According to the above method, the semiconductor wafer is coated with a polyamide-based heat-resistant resin such as PIQ resin to protect the electrodes or wiring.
このため、その耐熱性樹脂は半導体ウェハの搬送時に電
極あるいは配線への損傷を防止してくれる。また、半導
体ゥェハのダィシング時に、半導体の徴粉がとびちるが
、このような徴粉に対して電極あるいは配線を保護して
くれる。ざらにべレツトボンディング時にもそれらを保
護してくれる。したがって、製造歩留が低下することな
く高信頼度の樹脂封止型半導体装置が得られる。本発明
に関しては、第３図に示すような構造も考えられる。Therefore, the heat-resistant resin prevents damage to the electrodes or wiring during transportation of the semiconductor wafer. Further, when semiconductor wafers are diced, semiconductor particles are scattered, but the electrodes or wiring are protected from such particles. It also protects them during rough beret bonding. Therefore, a highly reliable resin-sealed semiconductor device can be obtained without decreasing manufacturing yield. Regarding the present invention, a structure as shown in FIG. 3 is also conceivable.
すなわち、素子領域２１，２２，２３が形成された半導
体基板２４の一主面上全体に、ボンディングパッド部３
３もおおつて、ＰＩＱ樹脂２７を塗布形成する。すなわ
ち、第２図において、ｄに示すＰＩＱ塗布をｈ‘こ示す
ワイヤボンディング後に行ったものである。この形成さ
れたＰＩＱ樹脂２７上全面（ＰＩＱ選択エッチは行なわ
ない）及び半導体基板２４の側面をおおし、、タブリー
ド２８の一部上をおおうように、Ｓｉ系のチップコート
材、例えば、Ｓｉラバ−、Ｓｉワニス、Ｓｉゲル等の樹
脂２０を塗布形成する。そのあと、この半導体基板２４
、ＰＩＱ樹脂２７、Ｓｉ系アンダーコート材２０、タブ
リード２８の一部及び、外部取出し用リード２９の一部
をＳｉ系及びェポキシ系の封止用樹脂３２で完全に封止
する。上述してきたように、本発明は、樹脂封止型半導
体装置に関するもので、本発明は単体、集積回路を問わ
ず、半導体装置全般に広く応用される。That is, the bonding pad portion 3 is formed on the entire main surface of the semiconductor substrate 24 on which the element regions 21, 22, and 23 are formed.
3 is also covered, and PIQ resin 27 is applied and formed. That is, in FIG. 2, PIQ coating shown in d was performed after wire bonding shown in h'. A Si-based chip coating material, for example, Si rubber, is applied to cover the entire surface of the formed PIQ resin 27 (PIQ selective etching is not performed) and the side surface of the semiconductor substrate 24, and to partially cover the tab lead 28. - A resin 20 such as Si varnish, Si gel, etc. is applied and formed. After that, this semiconductor substrate 24
, the PIQ resin 27, the Si-based undercoat material 20, a portion of the tab lead 28, and a portion of the external lead 29 are completely sealed with a Si-based and epoxy-based sealing resin 32. As described above, the present invention relates to a resin-sealed semiconductor device, and the present invention is widely applicable to semiconductor devices in general, regardless of whether they are single devices or integrated circuits.
尚、本明細書中、実施例に記載した第１図はバィポーラ
型集積回路装置を、第３図はバィポーラ型トランジスタ
を対象とた。さらに、本発明の応用例として、Ｓｉ系の
コート材は、ＰＩＱ樹脂上全体におおわなくても、第４
図ａに示すように、ＰＩＱ樹脂４９の周端部を取り囲む
ように、Ｓｉ系コート材５０を形成してもよい。Incidentally, in this specification, FIG. 1 described in the embodiments is directed to a bipolar integrated circuit device, and FIG. 3 is directed to a bipolar transistor. Furthermore, as an application example of the present invention, the Si-based coating material does not need to cover the entire surface of the PIQ resin;
As shown in Figure a, a Si-based coating material 50 may be formed to surround the peripheral end of the PIQ resin 49.
第４図ｂに、その破断面を示す。Ｓｉ系のコ−ト材５０
が、ＰＩＱ樹脂４９の周端をおおつて、半導体基板４０
上に延びているのがわかる。Figure 4b shows the fracture surface. Si-based coating material 50
covers the peripheral edge of the PIQ resin 49, and the semiconductor substrate 40
You can see that it extends upwards.
次に、本発明によれば、目的が達成できる理由は、以下
に示すことからである。Next, according to the present invention, the reason why the object can be achieved is as follows.
少なくとも、素子領域上は、熱的に安定なＰＩＱ樹脂で
おおわれているため、高温動作時ＰＩＱ樹脂中の分子の
影響によって電極間、配線間で、リーク電流が発生する
ことはない。At least the element region is covered with a thermally stable PIQ resin, so that no leakage current is generated between electrodes or wiring due to the influence of molecules in the PIQ resin during high-temperature operation.
さらに、このＰＩＱ樹脂上から、半導体基板にかけて、
半導体基板との接着性が良いＳｉ系のコート材で、ＰＩ
Ｑ樹脂をおおってアンダーコートしているため、ＰＩＱ
樹脂と半導体基板との接着性が良くなくても半導体基板
表面への水分の浸透は防げる。従って、従来よりも耐湿
性が劣化することはない。Furthermore, from above this PIQ resin to the semiconductor substrate,
A Si-based coating material with good adhesion to semiconductor substrates.
Since the Q resin is covered and undercoated, the PIQ
Even if the adhesiveness between the resin and the semiconductor substrate is poor, moisture can be prevented from penetrating into the surface of the semiconductor substrate. Therefore, the moisture resistance does not deteriorate compared to the conventional case.
【図面の簡単な説明】
第１図は、本発明をバィポーラ型集積回路装置に実施し
た場合を示す。
第２図ａ〜ｉは、第１図の構造のものを本発明の製造方
法に従って製造する工程を示したものである。第３図は
、本発明をハィポーラトランジスタに応用した場合を示
す。第４図ａ，ｂは、本発明の他の実施例を示す。１，
２４，４０・…・・半導体基板、２，３，４，２１，２
２，２３，４１，４２，４３・・・・・・半導体素子領
域、５，２５，４４・・・・・・絶縁膜、１４，２６，
４８・・・・・・アルミニウム配線、７，２７，４９…
…ＰＩＱ樹脂、９，２０，５０……Ｓｉ系コート材、８
，３３，４７……ボンディングパッド部、１３，３２，
５２・・…・封止用樹脂、１０，３１，５１……アルミ
ニウムリード線。
第１図
第３図
第２図
第４図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a case where the present invention is implemented in a bipolar integrated circuit device. FIGS. 2a to 2i show steps for manufacturing the structure shown in FIG. 1 according to the manufacturing method of the present invention. FIG. 3 shows the case where the present invention is applied to a hyperpolar transistor. Figures 4a and 4b show another embodiment of the invention. 1,
24, 40... Semiconductor substrate, 2, 3, 4, 21, 2
2, 23, 41, 42, 43... Semiconductor element region, 5, 25, 44... Insulating film, 14, 26,
48... Aluminum wiring, 7, 27, 49...
...PIQ resin, 9,20,50...Si-based coating material, 8
, 33, 47... bonding pad section, 13, 32,
52... Sealing resin, 10, 31, 51... Aluminum lead wire. Figure 1 Figure 3 Figure 2 Figure 4
Claims (1)
ハ主面にそのボンデイングパツドを露出するように耐熱
性樹脂被覆層を形成する工程と、その半導体ウエハをダ
イシングし、上記ボンデイングパツドをもつ複数のチツ
プとなす工程と、そのチツプのボンデイングパツドに対
しワイヤボンデイングを行う工程と、しかる後そのチツ
プ主面に他の樹脂を被覆する工程とより成ることを特徴
とする樹脂封止型半導体装置の製法。1. Forming a heat-resistant resin coating layer on the main surface of a semiconductor wafer on which a plurality of bonding pads are formed so as to expose the bonding pads, and dicing the semiconductor wafer to form a plurality of bonding pads on the main surface of the semiconductor wafer. A resin-sealed semiconductor device comprising the steps of forming a chip, performing wire bonding on bonding pads of the chip, and then coating the main surface of the chip with another resin. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59083702A JPS6034256B2 (en) | 1984-04-27 | 1984-04-27 | Manufacturing method for resin-encapsulated semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59083702A JPS6034256B2 (en) | 1984-04-27 | 1984-04-27 | Manufacturing method for resin-encapsulated semiconductor devices |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11770875A Division JPS6025902B2 (en) | 1975-10-01 | 1975-10-01 | Resin-encapsulated semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59210645A JPS59210645A (en) | 1984-11-29 |
| JPS6034256B2 true JPS6034256B2 (en) | 1985-08-07 |
Family
ID=13809823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59083702A Expired JPS6034256B2 (en) | 1984-04-27 | 1984-04-27 | Manufacturing method for resin-encapsulated semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6034256B2 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4122590Y1 (en) * | 1964-05-04 | 1966-11-14 | ||
| JPS49105466A (en) * | 1973-02-07 | 1974-10-05 | ||
| JPS5072588A (en) * | 1973-10-29 | 1975-06-16 | ||
| JPS50115978A (en) * | 1974-02-25 | 1975-09-10 | ||
| JPS51147962A (en) * | 1975-06-02 | 1976-12-18 | Fairchild Camera Instr Co | Method of mounting semiconductor devices |
| JPS5243367A (en) * | 1975-10-01 | 1977-04-05 | Hitachi Ltd | Resin seal type semiconductor device |
-
1984
- 1984-04-27 JP JP59083702A patent/JPS6034256B2/en not_active Expired
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4122590Y1 (en) * | 1964-05-04 | 1966-11-14 | ||
| JPS49105466A (en) * | 1973-02-07 | 1974-10-05 | ||
| JPS5072588A (en) * | 1973-10-29 | 1975-06-16 | ||
| JPS50115978A (en) * | 1974-02-25 | 1975-09-10 | ||
| JPS51147962A (en) * | 1975-06-02 | 1976-12-18 | Fairchild Camera Instr Co | Method of mounting semiconductor devices |
| JPS5243367A (en) * | 1975-10-01 | 1977-04-05 | Hitachi Ltd | Resin seal type semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59210645A (en) | 1984-11-29 |
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